/*
实验名称：PIT触发ADC
实验平台：渡鸦开发板
板载芯片：MK60DN512ZVQ10
实验效果：使用PIT模块周期性的触发ADC模块进行数据采集
通过调节开发板上的电位器，可以更改ad采集结果
*/
int main(void)
{
DelayInit();
GPIO_QuickInit(HW_GPIOE, 6, kGPIO_Mode_OPP);
UART_QuickInit(UART0_RX_PD06_TX_PD07, 115200);
printf("PIT tirgger ADC test\r\n");
/* 配置ADC0 硬件触发源 */
SIM->SOPT7 |= SIM_SOPT7_ADC0TRGSEL(4); /* 使用PIT0 触发 */
SIM->SOPT7 &= ~SIM_SOPT7_ADC0PRETRGSEL_MASK; /* 使用trigger A */
SIM->SOPT7 |= SIM_SOPT7_ADC0ALTTRGEN_MASK; /*使用除PDB之外的硬件触发源 此触发源可能因芯片而异*/
/* 初始化ADC模块 ADC0_SE19_DM0 */
ADC_InitTypeDef AD_InitStruct1;
AD_InitStruct1.instance = HW_ADC0;
AD_InitStruct1.clockDiv = kADC_ClockDiv2; /* ADC采样时钟2分频 */
AD_InitStruct1.resolutionMode = kADC_SingleDiff10or11; /*单端 10位精度 查分 11位精度 */
AD_InitStruct1.triggerMode = kADC_TriggerHardware; /* 硬件触发转换 */
AD_InitStruct1.singleOrDiffMode = kADC_Single; /*单端模式 */
AD_InitStruct1.continueMode = kADC_ContinueConversionDisable;
AD_InitStruct1.hardwareAveMode = kADC_HardwareAverageDisable; /*禁止 硬件平均 功能 */
ADC_Init(&AD_InitStruct1);
/* 初始化对应引脚 */
/* DM0引脚为专门的模拟引脚 ADC时 无需设置复用 DM0也无法当做普通的数字引脚 */
/* 启动一次ADC转换 填入通道值*/
ADC_StartConversion(HW_ADC0, 19, kADC_MuxA);
/* 初始化 PIT模块 */
PIT_QuickInit(HW_PIT_CH0, 1000*200); /* 200 ms 触发一次 */
while(1)
{
/* 如果ADC转换完成 读取转换结果*/
if(ADC_IsConversionCompleted(HW_ADC0, kADC_MuxA) == 0)
{
printf("ADC:%04d\r", ADC_ReadValue(HW_ADC0, kADC_MuxA));
}
}
}
/***********************************************************************
* PURPOSE: Initialize ADC0
*
* INPUTS:
* RETURNS:
***********************************************************************/
void init_ADC0(void) {
unsigned int calib;
// Turn on ADC0
SIM_SCGC6 |= SIM_SCGC6_ADC0_MASK;
// Single ended 16 bit conversion, no clock divider
ADC0_CFG1 |= ADC_CFG1_MODE_MASK;
//ADC0_CFG1 |= ADC_CFG1_ADLSMP_MASK | ADC_CFG1_MODE_MASK;
// Do ADC Calibration for Singled Ended ADC. Do not touch.
ADC0_SC3 = ADC_SC3_CAL_MASK;
while ( (ADC0_SC3 & ADC_SC3_CAL_MASK) != 0 );
calib = ADC0_CLP0; calib += ADC0_CLP1; calib += ADC0_CLP2;
calib += ADC0_CLP3; calib += ADC0_CLP4; calib += ADC0_CLPS;
calib = calib >> 1; calib |= 0x8000;
ADC0_PG = calib;
// Select hardware trigger.
ADC0_SC2 |= ADC_SC2_ADTRG_MASK;
// Set to single ended mode
//ADC0_SC1A = 0x0000;
//ADC0_SC1A |= ADC_SC1_AIEN_MASK | ADC_SC1_ADCH(0x1);
ADC0_SC1A = 0x41;
// Set up FTM2 trigger on ADC0
// FTM2 select
SIM_SOPT7 |= SIM_SOPT7_ADC0TRGSEL(0xA);
// Alternative trigger en.
SIM_SOPT7 |= SIM_SOPT7_ADC0ALTTRGEN_MASK;
// Pretrigger A
SIM_SOPT7 &= ~SIM_SOPT7_ADC0PRETRGSEL_MASK;
// Enable NVIC interrupt
NVIC_EnableIRQ(ADC0_IRQn);
}
int adc_init() {
adc_pixelIndex = 0;
// disable ADC irq - not ready yet
disable_irq(ADC_IRQ_NUM);
// turn on clock to ADC0
SIM_SCGC6 |= (SIM_SCGC6_ADC0_MASK);
// to setup SW trigger on FTM2
SIM_SOPT7 = SIM_SOPT7_ADC0TRGSEL(10);
// to calibrate the ADC module
unsigned short cal_var;
cal_var = 0x0000;
// add the plus-side calibration results
cal_var += ADC_CLP0_REG(ADC0_BASE_PTR);
cal_var += ADC_CLP1_REG(ADC0_BASE_PTR);
cal_var += ADC_CLP2_REG(ADC0_BASE_PTR);
cal_var += ADC_CLP3_REG(ADC0_BASE_PTR);
cal_var += ADC_CLP4_REG(ADC0_BASE_PTR);
cal_var += ADC_CLPS_REG(ADC0_BASE_PTR);
cal_var /= 2;
cal_var |= 0x8000;
// store value in plus-side gain calibration register (PG)
ADC_PG_REG(ADC0_BASE_PTR) = ADC_PG_PG(cal_var);
cal_var = 0x0000;
// add the minus-side calibration results
cal_var += ADC_CLM0_REG(ADC0_BASE_PTR);
cal_var += ADC_CLM1_REG(ADC0_BASE_PTR);
cal_var += ADC_CLM2_REG(ADC0_BASE_PTR);
cal_var += ADC_CLM3_REG(ADC0_BASE_PTR);
cal_var += ADC_CLM4_REG(ADC0_BASE_PTR);
cal_var += ADC_CLMS_REG(ADC0_BASE_PTR);
cal_var /= 2;
cal_var |= 0x8000;
// store value in minus-side gain calibration register (MG)
ADC_MG_REG(ADC0_BASE_PTR) = ADC_MG_MG(cal_var);
ADC_SC3_REG(ADC0_BASE_PTR) &= ~ADC_SC3_CAL_MASK;
// to set the configuration register 1 (CFG1) to select the mode of
// operation, clock source, clock divide, and configuration for low
// power or long sample time
ADC_CFG1_REG(ADC0_BASE_PTR) = ADLPC_NORMAL
| ADC_CFG1_ADIV(ADIV_1)
| ADLSMP_SHORT
| ADC_CFG1_MODE(MODE_8)
| ADC_CFG1_ADICLK(ADICLK_BUS);
// to set the configuration register 2 (CFG2) to select the special
// high-speed configuration for very high speed conversions and
// select the long sample time duration during long sample mode
ADC_CFG2_REG(ADC0_BASE_PTR) = MUXSEL_ADCA
| ADACKEN_DISABLED
| ADHSC_HISPEED
| ADC_CFG2_ADLSTS(ADLSTS_2);
// to configure the status and control register 2 (SC2)
ADC_SC2_REG(ADC0_BASE_PTR) = ADTRG_SW
| ACFE_DISABLED
| ACFGT_GREATER
| ACREN_DISABLED
| DMAEN_DISABLED
| ADC_SC2_REFSEL(REFSEL_EXT);
// to configure the status and control register 3 (SC3)
// enable hw averaging, 16 samples taken
ADC_SC3_REG(ADC0_BASE_PTR) = CAL_OFF
| ADCO_SINGLE
| AVGE_ENABLED
| ADC_SC3_AVGS(AVGS_16);
// to configure the status and control register 1 (SC1)
// enable the interrupt, single-ended conversion, on AD18
ADC_SC1_REG(ADC0_BASE_PTR, A)= AIEN_ON
| DIFF_SINGLE
| ADC_SC1_ADCH(18);
// to configure the PGA register
ADC_PGA_REG(ADC0_BASE_PTR) = PGAEN_DISABLED
| PGACHP_NOCHOP
| PGALP_NORMAL
| ADC_PGA_PGAG(PGAG_64);
// enable ADC irq
enable_irq(ADC_IRQ_NUM);
return ADC_RET_SUCCESS;
}
void CIO::startInt()
{
// Initialise the DAC
SIM_SCGC2 |= SIM_SCGC2_DAC0;
DAC0_C0 = DAC_C0_DACEN | DAC_C0_DACRFS; // 3.3V VDDA is DACREF_2
// Initialise ADC0
SIM_SCGC6 |= SIM_SCGC6_ADC0;
ADC0_CFG1 = ADC_CFG1_ADIV(1) | ADC_CFG1_ADICLK(1) | // Single-ended 12 bits, long sample time
ADC_CFG1_MODE(1) | ADC_CFG1_ADLSMP;
ADC0_CFG2 = ADC_CFG2_MUXSEL | ADC_CFG2_ADLSTS(2); // Select channels ADxxxb
ADC0_SC2 = ADC_SC2_REFSEL(0) | ADC_SC2_ADTRG; // Voltage ref external, hardware trigger
ADC0_SC3 = ADC_SC3_AVGE | ADC_SC3_AVGS(0); // Enable averaging, 4 samples
ADC0_SC3 |= ADC_SC3_CAL;
while (ADC0_SC3 & ADC_SC3_CAL) // Wait for calibration
;
uint16_t sum0 = ADC0_CLPS + ADC0_CLP4 + ADC0_CLP3 + // Plus side gain
ADC0_CLP2 + ADC0_CLP1 + ADC0_CLP0;
sum0 = (sum0 / 2U) | 0x8000U;
ADC0_PG = sum0;
ADC0_SC1A = ADC_SC1_AIEN | PIN_ADC; // Enable ADC interrupt, use A0
NVIC_ENABLE_IRQ(IRQ_ADC0);
#if defined(SEND_RSSI_DATA)
// Initialise ADC1
SIM_SCGC3 |= SIM_SCGC3_ADC1;
ADC1_CFG1 = ADC_CFG1_ADIV(1) | ADC_CFG1_ADICLK(1) | // Single-ended 12 bits, long sample time
ADC_CFG1_MODE(1) | ADC_CFG1_ADLSMP;
ADC1_CFG2 = ADC_CFG2_MUXSEL | ADC_CFG2_ADLSTS(2); // Select channels ADxxxb
ADC1_SC2 = ADC_SC2_REFSEL(0); // Voltage ref external, software trigger
ADC1_SC3 = ADC_SC3_AVGE | ADC_SC3_AVGS(0); // Enable averaging, 4 samples
ADC1_SC3 |= ADC_SC3_CAL;
while (ADC1_SC3 & ADC_SC3_CAL) // Wait for calibration
;
uint16_t sum1 = ADC1_CLPS + ADC1_CLP4 + ADC1_CLP3 + // Plus side gain
ADC1_CLP2 + ADC1_CLP1 + ADC1_CLP0;
sum1 = (sum1 / 2U) | 0x8000U;
ADC1_PG = sum1;
#endif
#if defined(EXTERNAL_OSC)
// Set ADC0 to trigger from the LPTMR at 24 kHz
SIM_SOPT7 = SIM_SOPT7_ADC0ALTTRGEN | // Enable ADC0 alternate trigger
SIM_SOPT7_ADC0TRGSEL(14); // Trigger ADC0 by LPTMR0
CORE_PIN13_CONFIG = PORT_PCR_MUX(3);
SIM_SCGC5 |= SIM_SCGC5_LPTIMER; // Enable Low Power Timer Access
LPTMR0_CSR = 0; // Disable
LPTMR0_PSR = LPTMR_PSR_PBYP; // Bypass prescaler/filter
LPTMR0_CMR = (EXTERNAL_OSC / 24000) - 1; // Frequency divided by CMR + 1
LPTMR0_CSR = LPTMR_CSR_TPS(2) | // Pin: 0=CMP0, 1=xtal, 2=pin13
LPTMR_CSR_TMS; // Mode Select, 0=timer, 1=counter
LPTMR0_CSR |= LPTMR_CSR_TEN; // Enable
#else
// Setup PDB for ADC0 at 24 kHz
SIM_SCGC6 |= SIM_SCGC6_PDB; // Enable PDB clock
PDB0_MOD = (F_BUS / 24000) - 1; // Timer period - 1
PDB0_IDLY = 0; // Interrupt delay
PDB0_CH0C1 = PDB_CHnC1_TOS | PDB_CHnC1_EN; // Enable pre-trigger for ADC0
PDB0_SC = PDB_SC_TRGSEL(15) | PDB_SC_PDBEN | // SW trigger, enable interrupts, continuous mode
PDB_SC_PDBIE | PDB_SC_CONT | PDB_SC_LDOK; // No prescaling
PDB0_SC |= PDB_SC_SWTRIG; // Software trigger (reset and restart counter)
#endif
digitalWrite(PIN_PTT, m_pttInvert ? HIGH : LOW);
digitalWrite(PIN_COSLED, LOW);
digitalWrite(PIN_LED, HIGH);
}
uint8_t Hw_Trig_Test(void)
{
// Notes:
// PDB settings : continous mode, started by sotware trigger.
// This means that once the software "pulls the trigger" by setting a certain bit, the PDB starts counting
// and handing out four triggers per cycle of its counter.
// PDB settings: CH0_DLY0, CH0_DLY1 , CH1_DLY0, CH1_DLY1
// set to different values to distinguish effect on ADCx_Ry register
// need to provide 4 different voltages to convert at two ADC0 and two ADC1 input channels
// PDB counter clock prescaled to allow time for printf's and slow down things to they are visible, each trigger.
// Using adiclk= BUS , and adidiv/4 to get 12,5MHz on Tower demonstration.
// visibility of PDB start trigger is obtained by generating a toggling edge on
// GPIOxx with PDBisr set to trigger immediatly at zero value of PDB counter.
// Conversion end of each ADC and channel within the ADC ( A,B ) will be done by
// toggling second GPIO pin inside ADCisr ( this pin is also reset by PDB isr )
// GPIO PIN to low voltage .. this macro sets the PIN low.
PIN_LOW
// Initialize PIN1 and PIN2 GPIO outputs
Init_Gpio2();
// Disable ADC and PDB interrupts
disable_irq(ADC0_irq_no) ; // not ready for this interrupt yet. Plug vector first.
disable_irq(ADC1_irq_no) ; // not ready for this interrupt yet. Plug vector first.
disable_irq(PDB_irq_no) ; // not ready for this interrupt yet. Plug vector first.
// Dynamic interrupt vector modification whilst those interruts are disabled
__VECTOR_RAM[73] = (uint32)adc0_isr; // plug isr into vector table in case not there already
__VECTOR_RAM[74] = (uint32)adc1_isr; // plug isr into vector table in case not there already
__VECTOR_RAM[88] = (uint32)pdb_isr; // plug isr into vector table in case not there already
// The System Integration Module largely determines the role of the different ball map locations on Kinetis.
// When an external pin is used, the System Integration Module should be consulted and invoked as needed.
// System integration module registers start with SIM_
// Turn on the ADC0 and ADC1 clocks as well as the PDB clocks to test ADC triggered by PDB
SIM_SCGC6 |= (SIM_SCGC6_ADC0_MASK );
SIM_SCGC3 |= (SIM_SCGC3_ADC1_MASK );
SIM_SCGC6 |= SIM_SCGC6_PDB_MASK ;
// Configure System Integration Module for defaults as far as ADC
SIM_SOPT7 &= ~(SIM_SOPT7_ADC1ALTTRGEN_MASK | // selects PDB not ALT trigger
SIM_SOPT7_ADC1PRETRGSEL_MASK |
SIM_SOPT7_ADC0ALTTRGEN_MASK | // selects PDB not ALT trigger
SIM_SOPT7_ADC0ALTTRGEN_MASK) ;
SIM_SOPT7 = SIM_SOPT7_ADC0TRGSEL(0); // applies only in case of ALT trigger, in which case
// PDB external pin input trigger for ADC
SIM_SOPT7 = SIM_SOPT7_ADC1TRGSEL(0); // same for both ADCs
/////////////////////////////////////////////////////////////////////////////////////////
//PDB configured below 以下是PDB配置
// Configure the Peripheral Delay Block (PDB):
// enable PDB, pdb counter clock = busclock / 20 , continous triggers, sw trigger , and use prescaler too
PDB0_SC = PDB_SC_CONT_MASK // Contintuous, rather than one-shot, mode
| PDB_SC_PDBEN_MASK // PDB enabled
| PDB_SC_PDBIE_MASK // PDB Interrupt Enable
| PDB_SC_PRESCALER(0x5) // Slow down the period of the PDB for testing
| PDB_SC_TRGSEL(0xf) // Trigger source is Software Trigger to be invoked in this file
| PDB_SC_MULT(2); // Multiplication factor 20 for the prescale divider for the counter clock
// the software trigger, PDB_SC_SWTRIG_MASK is not triggered at this time.
PDB0_IDLY = 0x0000; // need to trigger interrupt every counter reset which happens when modulus reached
PDB0_MOD = 0xffff; // largest period possible with the slections above, so slow you can see each conversion.
// channel 0 pretrigger 0 and 1 enabled and delayed
PDB0_CH0C1 = PDB_C1_EN(0x01)
| PDB_C1_TOS(0x01)
| PDB_C1_EN(0x02)
| PDB_C1_TOS(0x02) ;
PDB0_CH0DLY0 = ADC0_DLYA ;
PDB0_CH0DLY1 = ADC0_DLYB ;
// channel 1 pretrigger 0 and 1 enabled and delayed
PDB0_CH1C1 = PDB_C1_EN(0x01)
| PDB_C1_TOS(0x01)
| PDB_C1_EN(0x02)
| PDB_C1_TOS(0x02) ;
PDB0_CH1DLY0 = ADC1_DLYA ;
PDB0_CH1DLY1 = ADC1_DLYB ;
PDB0_SC = PDB_SC_CONT_MASK // Contintuous, rather than one-shot, mode
| PDB_SC_PDBEN_MASK // PDB enabled
| PDB_SC_PDBIE_MASK // PDB Interrupt Enable
| PDB_SC_PRESCALER(0x5) // Slow down the period of the PDB for testing
| PDB_SC_TRGSEL(0xf) // Trigger source is Software Trigger to be invoked in this file
| PDB_SC_MULT(2) // Multiplication factor 20 for the prescale divider for the counter clock
| PDB_SC_LDOK_MASK; // Need to ok the loading or it will not load certain regsiters!
// the software trigger, PDB_SC_SWTRIG_MASK is not triggered at this time.
//PDB configured above 以上是PDB配置
/////////////////////////////////////////////////////////////////////////////////////////
//ADC configured below 以下是ADC配置
// setup the initial ADC default configuration
Master_Adc_Config.CONFIG1 = ADLPC_NORMAL
| ADC_CFG1_ADIV(ADIV_4)
| ADLSMP_LONG
| ADC_CFG1_MODE(MODE_16)
| ADC_CFG1_ADICLK(ADICLK_BUS);
Master_Adc_Config.CONFIG2 = MUXSEL_ADCA
| ADACKEN_DISABLED
| ADHSC_HISPEED
| ADC_CFG2_ADLSTS(ADLSTS_20) ;
Master_Adc_Config.COMPARE1 = 0x1234u ; // can be anything
Master_Adc_Config.COMPARE2 = 0x5678u ; // can be anything
// since not using
// compare feature
Master_Adc_Config.STATUS2 = ADTRG_HW
| ACFE_DISABLED
| ACFGT_GREATER
| ACREN_ENABLED
| DMAEN_DISABLED
| ADC_SC2_REFSEL(REFSEL_EXT);
Master_Adc_Config.STATUS3 = CAL_OFF
| ADCO_SINGLE
| AVGE_ENABLED
| ADC_SC3_AVGS(AVGS_32);
Master_Adc_Config.PGA = PGAEN_DISABLED
| PGACHP_NOCHOP
| PGALP_NORMAL
| ADC_PGA_PGAG(PGAG_64);
Master_Adc_Config.STATUS1A = AIEN_OFF | DIFF_SINGLE | ADC_SC1_ADCH(31);
Master_Adc_Config.STATUS1B = AIEN_OFF | DIFF_SINGLE | ADC_SC1_ADCH(31);
// Configure ADC as it will be used, but becuase ADC_SC1_ADCH is 31,
// the ADC will be inactive. Channel 31 is just disable function.
// There really is no channel 31.
ADC_Config_Alt(ADC0_BASE_PTR, &Master_Adc_Config); // config ADC
// Calibrate the ADC in the configuration in which it will be used:
ADC_Cal(ADC0_BASE_PTR); // do the calibration
// The structure still has the desired configuration. So restore it.
// Why restore it? The calibration makes some adjustments to the
// configuration of the ADC. The are now undone:
// config the ADC again to desired conditions
ADC_Config_Alt(ADC0_BASE_PTR, &Master_Adc_Config);
// REPEAT for BOTH ADC's. However we will only 'use' the results from
// the ADC wired to the Potentiometer on the Kinetis Tower Card.
// Repeating for ADC1:
ADC_Config_Alt(ADC1_BASE_PTR, &Master_Adc_Config); // config ADC
ADC_Cal(ADC1_BASE_PTR); // do the calibration
// ADC_Read_Cal(ADC1_BASE_PTR,&CalibrationStore[0]); // store the cal
// config the ADC again to default conditions
ADC_Config_Alt(ADC1_BASE_PTR, &Master_Adc_Config);
// *****************************************************************************
// ADC0 and ADC1 using the PDB trigger in ping pong
// *****************************************************************************
// use interrupts, single ended mode, and real channel numbers now:
Master_Adc_Config.STATUS1A = AIEN_ON | DIFF_SINGLE | ADC_SC1_ADCH(ADC0_CHANA);
Master_Adc_Config.STATUS1B = AIEN_ON | DIFF_SINGLE | ADC_SC1_ADCH(ADC0_CHANB);
ADC_Config_Alt(ADC0_BASE_PTR, &Master_Adc_Config); // config ADC0
Master_Adc_Config.STATUS1A = AIEN_ON | DIFF_SINGLE | ADC_SC1_ADCH(ADC1_CHANA);
Master_Adc_Config.STATUS1B = AIEN_ON | DIFF_SINGLE | ADC_SC1_ADCH(ADC1_CHANB);
ADC_Config_Alt(ADC1_BASE_PTR, &Master_Adc_Config); // config ADC1
// Note that three different balls are being sampled:
// ADC0_CHANA not used in this demo, but readings are shown
// ADC0_CHANB not used in this demo, but readings are shown
// ADC1_CHANA POT channel set the same as the following for demo: 20
// ADC1_CHANB POT channel set the same as the above for demo: 20
// The potentiometer is only on ADC1. That is the one used
// to calculate the change of the potentiometer below.
while(char_present()) in_char(); // flush terminal buffer
printf ("\n\n\n");
printf("********************************************************\n");
printf("* Running ADC0 & ADC1 HARDWARE TRIGGER by PDB *\n");
printf("* The one PDB is triggering both ADC0 and ADC1 *\n");
printf("* ADC1 A,B is the POT. Vary the POT setting. *\n");
printf("* Hit any key to exit (ADC0 readings not used) *\n");
printf("********************************************************\n");
printf ("\n\n");
// Enable the ADC and PDB interrupts in NVIC
enable_irq(ADC0_irq_no) ; // ready for this interrupt.
enable_irq(ADC1_irq_no) ; // ready for this interrupt.
enable_irq(PDB_irq_no) ; // ready for this interrupt.
// In case previous test did not end with interrupts enabled, enable used ones.
EnableInterrupts ;
cycle_flags=0;
PDB0_SC |= PDB_SC_SWTRIG_MASK ; // kick off the PDB - just once
//The system is now working!!!! The PDB is *continuously* triggering ADC
// conversions. Now, to display the results! The line above
// was the SOFTWARE TRIGGER...
// The demo will continue as long as no character is pressed on the terminal.
while(!char_present()) // as long as no operater intervention, keep running this:
{
while( cycle_flags != ( ADC0A_DONE | ADC0B_DONE | ADC1A_DONE | ADC1B_DONE )); // wait for one complete cycle
printf("R0A=%6d R0B=%6d R1A=%6d R1B=%6d POT=%6d\r",
result0A,result0B,result1A,result1B, exponentially_filtered_result1);
}
// disable the PDB
PDB0_SC = 0 ;
// Disable the ADC and PDB interrupts in NVIC
disable_irq(ADC0_irq_no) ; // through with this interrupt.
disable_irq(ADC1_irq_no) ; // through with this interrupt.
disable_irq(PDB_irq_no) ; // through with this interrupt.
printf ("\n\n\n");
printf("********************************************************\n");
printf("* Demonstration ended at operator request *\n");
printf("* ADC0 & ADC1 PDB TRIGGER DEMO COMPLETE *\n");
printf("********************************************************\n");
printf ("\n\n");
return 0;
}
/*************************************************************************
* 野火嵌入式開發工作室
*
* 函數名稱：adc_init
* 功能說明：AD初始化，使能時鐘
* 參數說明：ADCn 模塊號（ ADC0、 ADC1）
* 函數返回：無
* 修改時間：2012-2-10
* 備 注：參考蘇州大學的例程
*************************************************************************/
void adc_init(ADCn adcn,ADC_Ch ch)
{
ASSERT( ((adcn == ADC0) && (ch>=AD8 && ch<=AD18)) || ((adcn == ADC1)&& (ch>=AD4a && ch<=AD17)) ) ; //使用斷言檢測ADCn_CHn是否正常
switch(adcn)
{
case ADC0: /* ADC0 */
SIM_SCGC6 |= (SIM_SCGC6_ADC0_MASK ); //開啟ADC0時鐘
SIM_SOPT7 &= ~(SIM_SOPT7_ADC0ALTTRGEN_MASK |SIM_SOPT7_ADC0PRETRGSEL_MASK);
SIM_SOPT7 = SIM_SOPT7_ADC0TRGSEL(0);
switch(ch)
{
case AD8: //ADC0_SE8 -- PTB0
case AD9: //ADC0_SE9 -- PTB1
SIM_SCGC5 |= SIM_SCGC5_PORTB_MASK;
PORT_PCR_REG(PORTB_BASE_PTR, ch-AD8+0) = PORT_PCR_MUX(0);
break;
case AD10: //ADC0_SE10 -- PTA7
case AD11: //ADC0_SE11 -- PTA8
SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;
PORT_PCR_REG(PORTA_BASE_PTR, ch-AD10+7) = PORT_PCR_MUX(0);
break;
case AD12: //ADC0_SE12 -- PTB2
case AD13: //ADC0_SE13 -- PTB3
SIM_SCGC5 |= SIM_SCGC5_PORTB_MASK;
PORT_PCR_REG(PORTB_BASE_PTR, ch-AD12+2) = PORT_PCR_MUX(0);
break;
case AD14: //ADC0_SE14 -- PTC0
case AD15: //ADC0_SE15 -- PTC1
SIM_SCGC5 |= SIM_SCGC5_PORTC_MASK;
PORT_PCR_REG(PORTC_BASE_PTR, ch-AD14+0) = PORT_PCR_MUX(0);
break;
case AD17: //ADC0_SE17 -- PTE24
case AD18: //ADC0_SE17 -- PTE25
SIM_SCGC5 |= SIM_SCGC5_PORTE_MASK;
PORT_PCR_REG(PORTE_BASE_PTR, ch-AD17+24) = PORT_PCR_MUX(0);
break;
default:
return;
}
return;
case ADC1: /* ADC1 */
SIM_SCGC3 |= (SIM_SCGC3_ADC1_MASK );
SIM_SOPT7 &= ~(SIM_SOPT7_ADC1ALTTRGEN_MASK |SIM_SOPT7_ADC1PRETRGSEL_MASK) ;
SIM_SOPT7 = SIM_SOPT7_ADC1TRGSEL(0);
switch(ch)
{
case AD4a: //ADC1_SE4a -- PTE0
case AD5a: //ADC1_SE5a -- PTE1
case AD6a: //ADC1_SE6a -- PTE2
case AD7a: //ADC1_SE7a -- PTE3
SIM_SCGC5 |= SIM_SCGC5_PORTE_MASK;
PORT_PCR_REG(PORTE_BASE_PTR, ch-AD4a+0) = PORT_PCR_MUX(0);
break;
case AD8: //ADC1_SE8 -- PTB0
case AD9: //ADC1_SE9 -- PTB1
SIM_SCGC5 |= SIM_SCGC5_PORTB_MASK;
PORT_PCR_REG(PORTB_BASE_PTR, ch-AD8+0) = PORT_PCR_MUX(0);
break;
case AD10: //ADC1_SE10 -- PTB4
case AD11: //ADC1_SE11 -- PTB5
case AD12: //ADC1_SE12 -- PTB6
case AD13: //ADC1_SE13 -- PTB7
SIM_SCGC5 |= SIM_SCGC5_PORTB_MASK;
PORT_PCR_REG(PORTB_BASE_PTR, ch-6) = PORT_PCR_MUX(0);
break;
case AD14: //ADC1_SE14 -- PTB10
case AD15: //ADC1_SE15 -- PTB11
SIM_SCGC5 |= SIM_SCGC5_PORTB_MASK;
PORT_PCR_REG(PORTB_BASE_PTR, ch-AD10+4) = PORT_PCR_MUX(0);
break;
case AD17: //ADC1_SE17 -- PTA17
SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;
PORT_PCR_REG(PORTA_BASE_PTR, ch) = PORT_PCR_MUX(0);
break;
default:
break;
}
break;
default:
break;
}
}