int SIM_arbiter_init(SIM_power_arbiter_t *arb, int arbiter_model, int ff_model, u_int req_width, double length, SIM_power_array_info_t *info)
{
if ((arb->model = arbiter_model) && arbiter_model < ARBITER_MAX_MODEL) {
arb->req_width = req_width;
SIM_arbiter_clear_stat(arb);
/* redundant field */
arb->mask = HAMM_MASK(req_width);
switch (arbiter_model) {
case RR_ARBITER:
arb->e_chg_req = SIM_rr_arbiter_req_cap(length) / 2 * EnergyFactor;
/* two grant signals switch together, so no 1/2 */
arb->e_chg_grant = SIM_rr_arbiter_grant_cap() * EnergyFactor;
arb->e_chg_carry = SIM_rr_arbiter_carry_cap() / 2 * EnergyFactor;
arb->e_chg_carry_in = SIM_rr_arbiter_carry_in_cap() / 2 * EnergyFactor;
arb->e_chg_mint = 0;
if (SIM_fpfp_init(&arb->pri_ff, ff_model, SIM_rr_arbiter_pri_cap()))
return -1;
break;
case MATRIX_ARBITER:
arb->e_chg_req = SIM_matrix_arbiter_req_cap(req_width, length) / 2 * EnergyFactor;
/* 2 grant signals switch together, so no 1/2 */
arb->e_chg_grant = SIM_matrix_arbiter_grant_cap(req_width) * EnergyFactor;
arb->e_chg_mint = SIM_matrix_arbiter_int_cap() / 2 * EnergyFactor;
arb->e_chg_carry = arb->e_chg_carry_in = 0;
if (SIM_fpfp_init(&arb->pri_ff, ff_model, SIM_matrix_arbiter_pri_cap(req_width)))
return -1;
break;
case QUEUE_ARBITER:
arb->e_chg_req = arb->e_chg_grant = arb->e_chg_mint = 0;
arb->e_chg_carry = arb->e_chg_carry_in = 0;
return SIM_array_power_init(info, &arb->queue);
break;
default: /* some error handler */
break;
}
return 0;
}
else
return -1;
}
/* FIXME: request wire length estimation is ad hoc */
int SIM_router_power_init(SIM_power_router_info_t *info, SIM_power_router_t *router)
{
double cbuf_width, req_len = 0;
/* initialize crossbar */
if (info->crossbar_model)
SIM_crossbar_init(&router->crossbar, info->crossbar_model, info->n_switch_in, info->n_switch_out, info->flit_width, info->degree, info->connect_type, info->trans_type, info->crossbar_in_len, info->crossbar_out_len, &req_len);
/* initialize various buffers */
if (info->in_buf)
SIM_array_power_init(&info->in_buf_info, &router->in_buf);
if (info->cache_in_buf)
SIM_array_power_init(&info->cache_in_buf_info, &router->cache_in_buf);
if (info->mc_in_buf)
SIM_array_power_init(&info->mc_in_buf_info, &router->mc_in_buf);
if (info->io_in_buf)
SIM_array_power_init(&info->io_in_buf_info, &router->io_in_buf);
if (info->out_buf)
SIM_array_power_init(&info->out_buf_info, &router->out_buf);
if (info->central_buf) {
/* MUST initialize array before crossbar because the latter needs array width */
SIM_array_power_init(&info->central_buf_info, &router->central_buf);
/* WHS: use MATRIX_CROSSBAR, info->connect_type, info->trans_type rather than specifying new parameters */
cbuf_width = info->central_buf_info.data_arr_width + info->central_buf_info.tag_arr_width;
req_len = info->central_buf_info.data_arr_height;
SIM_crossbar_init(&router->in_cbuf_crsbar, MATRIX_CROSSBAR, info->n_switch_in, info->pipe_depth * info->central_buf_info.write_ports, info->flit_width, 0, info->connect_type, info->trans_type, cbuf_width, 0, NULL);
SIM_crossbar_init(&router->out_cbuf_crsbar, MATRIX_CROSSBAR, info->pipe_depth * info->central_buf_info.read_ports, info->n_switch_out, info->flit_width, 0, info->connect_type, info->trans_type, 0, cbuf_width, NULL);
/* dirty hack */
SIM_fpfp_init(&router->cbuf_ff, info->cbuf_ff_model, 0);
}
/* initialize arbiter */
if (info->in_arb_model) {
SIM_arbiter_init(&router->in_arb, info->in_arb_model, info->in_arb_ff_model, info->n_v_class, 0, &info->in_arb_queue_info);
if (info->n_cache_in)
SIM_arbiter_init(&router->cache_in_arb, info->in_arb_model, info->in_arb_ff_model, info->cache_class, 0, &info->cache_in_arb_queue_info);
if (info->n_mc_in)
SIM_arbiter_init(&router->mc_in_arb, info->in_arb_model, info->in_arb_ff_model, info->mc_class, 0, &info->mc_in_arb_queue_info);
if (info->n_io_in)
SIM_arbiter_init(&router->io_in_arb, info->in_arb_model, info->in_arb_ff_model, info->io_class, 0, &info->io_in_arb_queue_info);
}
/* WHS: must after switch initialization */
if (info->out_arb_model) {
SIM_arbiter_init(&router->out_arb, info->out_arb_model, info->out_arb_ff_model, info->n_total_in - 1, req_len, &info->out_arb_queue_info);
}
return 0;
}
/* FIXME: request wire length estimation is ad hoc */
int SIM_router_power_init(SIM_router_info_t *info, SIM_router_power_t *router)
{
double cbuf_width, req_len = 0;
router->I_static = 0;
router->I_buf_static = 0;
router->I_crossbar_static = 0;
router->I_vc_arbiter_static = 0;
router->I_sw_arbiter_static = 0;
/* initialize crossbar */
if (info->crossbar_model) {
SIM_crossbar_init(&router->crossbar, info->crossbar_model, info->n_switch_in, info->n_switch_out, info->xb_in_seg, info->xb_out_seg, info->flit_width, info->degree, info->connect_type, info->trans_type, info->crossbar_in_len, info->crossbar_out_len, &req_len);
/* static power */
router->I_crossbar_static = router->crossbar.I_static;
router->I_static += router->I_crossbar_static;
}
/* HACK HACK HACK */
if (info->exp_xb_model)
SIM_crossbar_init(&router->exp_xb, info->exp_xb_model, 2 * info->n_switch_in - 1, 2 * info->n_switch_out - 1, info->exp_in_seg, info->exp_out_seg, info->flit_width, info->degree, info->connect_type, info->trans_type, 0, 0, NULL);
/* initialize various buffers */
if (info->in_buf) {
SIM_array_power_init(&info->in_buf_info, &router->in_buf);
/* static power */
router->I_buf_static = router->in_buf.I_static * info->n_in * info->n_v_class * (info->in_share_buf ? 1 : info->n_v_channel);
}
if (info->cache_in_buf)
SIM_array_power_init(&info->cache_in_buf_info, &router->cache_in_buf);
if (info->mc_in_buf)
SIM_array_power_init(&info->mc_in_buf_info, &router->mc_in_buf);
if (info->io_in_buf)
SIM_array_power_init(&info->io_in_buf_info, &router->io_in_buf);
if (info->out_buf){
SIM_array_power_init(&info->out_buf_info, &router->out_buf);
/* static power */
router->I_buf_static += router->out_buf.I_static * info->n_out * info->n_v_class * (info->out_share_buf ? 1 : info->n_v_channel);
}
router->I_static += router->I_buf_static;
if (info->central_buf) {
/* MUST initialize array before crossbar because the latter needs array width */
SIM_array_power_init(&info->central_buf_info, &router->central_buf);
/* WHS: use MATRIX_CROSSBAR, info->connect_type, info->trans_type rather than specifying new parameters */
cbuf_width = info->central_buf_info.data_arr_width + info->central_buf_info.tag_arr_width;
req_len = info->central_buf_info.data_arr_height;
/* assuming no segmentation for central buffer in/out crossbars */
SIM_crossbar_init(&router->in_cbuf_crsbar, MATRIX_CROSSBAR, info->n_switch_in, info->pipe_depth * info->central_buf_info.write_ports, 0, 0, info->flit_width, 0, info->connect_type, info->trans_type, cbuf_width, 0, NULL);
SIM_crossbar_init(&router->out_cbuf_crsbar, MATRIX_CROSSBAR, info->pipe_depth * info->central_buf_info.read_ports, info->n_switch_out, 0, 0, info->flit_width, 0, info->connect_type, info->trans_type, 0, cbuf_width, NULL);
/* dirty hack */
SIM_fpfp_init(&router->cbuf_ff, info->cbuf_ff_model, 0);
}
/* initialize switch allocator arbiter */
if (info->sw_in_arb_model) {
SIM_arbiter_init(&router->sw_in_arb, info->sw_in_arb_model, info->sw_in_arb_ff_model, info->n_v_channel*info->n_v_class, 0, &info->sw_in_arb_queue_info);
if (info->n_cache_in)
SIM_arbiter_init(&router->cache_in_arb, info->sw_in_arb_model, info->sw_in_arb_ff_model, info->cache_class, 0, &info->cache_in_arb_queue_info);
if (info->n_mc_in)
SIM_arbiter_init(&router->mc_in_arb, info->sw_in_arb_model, info->sw_in_arb_ff_model, info->mc_class, 0, &info->mc_in_arb_queue_info);
if (info->n_io_in)
SIM_arbiter_init(&router->io_in_arb, info->sw_in_arb_model, info->sw_in_arb_ff_model, info->io_class, 0, &info->io_in_arb_queue_info);
router->I_sw_arbiter_static = router->sw_in_arb.I_static * info->in_n_switch * info->n_in;
}
/* WHS: must after switch initialization */
if (info->sw_out_arb_model) {
SIM_arbiter_init(&router->sw_out_arb, info->sw_out_arb_model, info->sw_out_arb_ff_model, info->n_total_in - 1, req_len, &info->sw_out_arb_queue_info);
router->I_sw_arbiter_static += router->sw_out_arb.I_static * info->n_switch_out;
}
/*static energy*/
router->I_static += router->I_sw_arbiter_static;
/* initialize virtual channel allocator arbiter */
if(info->vc_allocator_type == ONE_STAGE_ARB && info->n_v_channel > 1 && info->n_in > 1){
if (info->vc_out_arb_model)
{
SIM_arbiter_init(&router->vc_out_arb, info->vc_out_arb_model, info->vc_out_arb_ff_model,
(info->n_in - 1) * info->n_v_channel, 0, &info->vc_out_arb_queue_info);
router->I_vc_arbiter_static = router->vc_out_arb.I_static * info->n_out * info->n_v_channel * info->n_v_class;
}
else {
fprintf (stderr, "error in setting vc allocator parameters\n");
}
}
else if(info->vc_allocator_type == TWO_STAGE_ARB && info->n_v_channel > 1 && info->n_in > 1){
if (info->vc_in_arb_model && info->vc_out_arb_model)
{
// first stage
SIM_arbiter_init(&router->vc_in_arb, info->vc_in_arb_model, info->vc_in_arb_ff_model,
info->n_v_channel, 0, &info->vc_in_arb_queue_info);
router->I_vc_arbiter_static = router->vc_in_arb.I_static * info->n_in * info->n_v_channel * info->n_v_class;
//second stage
SIM_arbiter_init(&router->vc_out_arb, info->vc_out_arb_model, info->vc_out_arb_ff_model,
(info->n_in - 1) * info->n_v_channel, 0, &info->vc_out_arb_queue_info);
router->I_vc_arbiter_static += router->vc_out_arb.I_static * info->n_out * info->n_v_channel * info->n_v_class;
}
else {
fprintf (stderr, "error in setting vc allocator parameters\n");
}
}
else if(info->vc_allocator_type == VC_SELECT && info->n_v_channel > 1) {
SIM_array_power_init(&info->vc_select_buf_info, &router->vc_select_buf);
/* static power */
router->I_vc_arbiter_static = router->vc_select_buf.I_static * info->n_out * info->n_v_class;
}
router->I_static += router->I_vc_arbiter_static;
return 0;
}
int SIM_arbiter_init(SIM_arbiter_t *arb, int arbiter_model, int ff_model, u_int req_width, double length, SIM_array_info_t *info)
{
if ((arb->model = arbiter_model) && arbiter_model < ARBITER_MAX_MODEL)
{
arb->req_width = req_width;
SIM_arbiter_clear_stat(arb);
/* redundant field */
arb->mask = HAMM_MASK(req_width);
double I_static;
switch (arbiter_model)
{
case RR_ARBITER:
arb->e_chg_req = SIM_rr_arbiter_req_cap(length) / 2 * EnergyFactor;
/* two grant signals switch together, so no 1/2 */
arb->e_chg_grant = SIM_rr_arbiter_grant_cap() * EnergyFactor;
arb->e_chg_carry = SIM_rr_arbiter_carry_cap() / 2 * EnergyFactor;
arb->e_chg_carry_in = SIM_rr_arbiter_carry_in_cap() / 2 * EnergyFactor;
arb->e_chg_mint = 0;
if (SIM_fpfp_init(&arb->pri_ff, ff_model, SIM_rr_arbiter_pri_cap()))
return -1;
/*arbiter static power */
I_static = 0;
/* NOR */
I_static += (6 * arb->req_width * ((WdecNORp*NOR2_TAB[0] + WdecNORn*(NOR2_TAB[1] + NOR2_TAB[2] + NOR2_TAB[3]))/4));
/* inverter */
I_static += 2 * arb->req_width * ((Wdecinvn*NMOS_TAB[0] + Wdecinvp*PMOS_TAB[0])/2);
/* DFF */
I_static += (arb->req_width * Wdff*DFF_TAB[0]);
arb->I_static = I_static;
break;
case MATRIX_ARBITER:
arb->e_chg_req = SIM_matrix_arbiter_req_cap(req_width, length) / 2 * EnergyFactor;
/* 2 grant signals switch together, so no 1/2 */
arb->e_chg_grant = SIM_matrix_arbiter_grant_cap(req_width) * EnergyFactor;
arb->e_chg_mint = SIM_matrix_arbiter_int_cap() / 2 * EnergyFactor;
arb->e_chg_carry = arb->e_chg_carry_in = 0;
if (SIM_fpfp_init(&arb->pri_ff, ff_model, SIM_matrix_arbiter_pri_cap(req_width)))
return -1;
/*arbiter static power */
I_static = 0;
/* NOR */
I_static += ((2 * arb->req_width - 1) * arb->req_width) * ((WdecNORp*NOR2_TAB[0] + WdecNORn*(NOR2_TAB[1] + NOR2_TAB[2] + NOR2_TAB[3]))/4);
/* inverter */
I_static += arb->req_width * ((Wdecinvn*NMOS_TAB[0] + Wdecinvp*PMOS_TAB[0])/2);
/* DFF */
I_static += (arb->req_width * (arb->req_width - 1) / 2) * (Wdff*DFF_TAB[0]);
arb->I_static = I_static;
break;
case QUEUE_ARBITER:
arb->e_chg_req = arb->e_chg_grant = arb->e_chg_mint = 0;
arb->e_chg_carry = arb->e_chg_carry_in = 0;
return SIM_array_power_init(info, &arb->queue);
break;
default:
printf ("error\n"); /* some error handler */
}
return 0;
}
else
return -1;
}
