DLL_EXPORT void
init_local(void)
{
id_splitter_data.new_instance = id_splitter_new_instance;
id_splitter_data.description = "The id splitter module splits up memory operations into separate "
"data and instruction streams. Data operations are forwarded to "
"the timing interface of the object specified by the dbranch attribute and, "
"in the same manner, instruction operations are forwarded to the ibranch.";
if (!(id_splitter_class = SIM_register_class("id-splitter", &id_splitter_data))) {
pr("Could not create id-splitter class\n");
}
/* set up custom interfaces */
timing_interface.operate = id_splitter_operate;
SIM_register_interface(id_splitter_class, "timing-model", &timing_interface);
SIM_register_attribute(id_splitter_class, "ibranch",
get_ibranch, 0, set_ibranch, 0, Sim_Attr_Optional,
"Object to receive instruction transactions.");
SIM_register_attribute(id_splitter_class, "dbranch",
get_dbranch, 0, set_dbranch, 0, Sim_Attr_Optional,
"Object to receive data transactions.");
}
//**************************************************************************
void hfa_init_local( void )
{
attr_value_t attr;
conf_class_t *conf_class;
conf_object_t *conf_cpu;
memset( &attr, 0, sizeof(attr) );
hfa_checkerr("BEGIN INIT");
if (SIM_number_processors() == 0) {
#ifdef SIMICS22X
printf("opal: No processors defined -- load a checkpoint first!\n");
printf("opal: Please restart simics and try again.\n");
return;
#endif
#ifdef SIMICS30
/*
* This case arises because of Simics 3.0:
* Simics 3.0 loads and "digitally signs" modules immediately after compiling them.
* This raises havoc with Multifacet's modules, since most of them require a checkpoint
* to be loaded BEFORE the module.
*/
printf("\033[34;1m\n");
printf(" /***************************************************************************\\\n");
printf(" > Opal found no processors. If you are NOT compiling Opal and you see this <\n");
printf(" > message, something is wrong. <\n");
printf(" > This message is part of the normal compilation process. <\n");
printf(" \\***************************************************************************/\033[m\n\n");
SIM_clear_exception();
return;
#endif
}
/* Initialize and register the class "opal". */
memset(&hfa_class_data, 0, sizeof(class_data_t));
hfa_class_data.new_instance = hfa_new_instance;
conf_class = SIM_register_class("opal", &hfa_class_data);
/* Initialize and register the timing-model interface */
hfa_timing_interface.operate = NULL;
SIM_register_interface(conf_class, TIMING_MODEL_INTERFACE,
&hfa_timing_interface);
/* Initialize and register the snoop-device interface */
hfa_snoop_interface.operate = NULL;
SIM_register_interface(conf_class, SNOOP_MEMORY_INTERFACE,
&hfa_snoop_interface);
/* Initialize and register the event poster interface */
hfa_event_poster_interface.get_event_info = hfa_get_event;
hfa_event_poster_interface.set_event_info = hfa_set_event;
hfa_event_poster_interface.describe_event = hfa_describe_event;
SIM_register_interface(conf_class, "event-poster",
&hfa_event_poster_interface);
/* Initialize and register multifacet-ruby interface */
memset(&hfa_ruby_interface, 0, sizeof(hfa_ruby_interface));
SIM_register_interface(conf_class, "mf-opal-api", &hfa_ruby_interface);
/** create the hfa object */
hfa_conf_object = (hfa_object_t *) SIM_new_object(conf_class, "opal0");
/* register with cpu 0 event queue */
attr.kind = Sim_Val_Object;
conf_cpu = SIM_next_queue(0);
if (conf_cpu) {
attr.u.object = conf_cpu;
printf("Queue registration %s\n", conf_cpu->name );
set_error_t install_error = SIM_set_attribute( (conf_object_t *) hfa_conf_object, "queue", &attr );
if (install_error == Sim_Set_Ok) {
printf( "successful installation of the opal queue.\n");
} else {
printf( "error installing opal queue.\n");
exit(1);
}
} else {
printf("error: unable to register queue interface\n");
}
/* register interfaces on the hfa0 object */
/* event-poster interface */
SIM_register_attribute( conf_class, "install-event-poster",
hfa_post_get, (void *) "install-event-poster",
hfa_post_set, (void *) "install-event-poster",
Sim_Attr_Pseudo,
"Post a trace-related function to event queue" );
// Allocate and initialize a configuration reader
hfa_construct_initvar();
hfa_checkerr("hfa_construct_initvar(): check");
// register a number of commands
#define OPAL_COMMAND( COMMAND ) \
SIM_register_attribute( conf_class, COMMAND, \
initvar_dispatch_get, (void *) COMMAND, \
initvar_dispatch_set, (void *) COMMAND, \
Sim_Attr_Pseudo, \
"See documentation with associated opal command." )
/** read a configuration file */
OPAL_COMMAND( "init" );
OPAL_COMMAND( "readparam" );
OPAL_COMMAND( "saveparam" );
/** interfaces for recording a trace to disk */
OPAL_COMMAND( "trace-start" );
OPAL_COMMAND( "trace-stop" );
OPAL_COMMAND( "take-trace" );
OPAL_COMMAND( "skip-trace" );
OPAL_COMMAND( "branch-trace-start" );
OPAL_COMMAND( "branch-trace-stop" );
OPAL_COMMAND( "branch-trace-take" );
OPAL_COMMAND( "branch-trace-inf" );
OPAL_COMMAND( "stepper" );
OPAL_COMMAND( "param" );
/** interfaces to run inside of simics */
OPAL_COMMAND( "sim-flag" );
OPAL_COMMAND( "sim-start" );
OPAL_COMMAND( "sim-stop" );
OPAL_COMMAND( "sim-step" );
OPAL_COMMAND( "break_simulation" );
OPAL_COMMAND( "sim-inorder-step" );
OPAL_COMMAND( "sim-warmup" );
OPAL_COMMAND( "cycle" );
OPAL_COMMAND( "sim-stats" );
OPAL_COMMAND( "sim-inflight" );
OPAL_COMMAND( "sim-rd-check" );
OPAL_COMMAND( "sim-wr-check" );
OPAL_COMMAND( "debugtime" );
OPAL_COMMAND( "stall" );
OPAL_COMMAND( "togglemh" );
OPAL_COMMAND( "install-snoop" );
OPAL_COMMAND( "mlp-trace" );
// ADD_SIMCOMMAND
// check for errors
hfa_checkerr("class regististration");
// check that we are compatible with this version of the simulator
hfa_simcheck();
hfa_checkerr("hfa_simcheck(): check");
printf("hfa_init_local done:\n");
return;
}
void
init_local(void)
{
conf_class_t *conf_class;
/* Initialize and register the class "consistency_controller". */
memset(&class_data, 0, sizeof(class_data_t));
class_data.new_instance = consistency_controller_new_instance;
class_data.description =
"The consistency controller class implements a "
"memory hierarchy that communicates with the instruction tree "
"(in an out of order Simics) to enforce the architecturally "
"defined consistency model. This is done by stalling loads and stores "
"that would violate the consistency model but are otherwise ready to "
"issue to the memory system. The reason for not integrating the "
"consistency controller into the Simics core is to allow the user to "
"experiment with relaxed consistency model implementations. The user "
"can replace the consistency controller or modify the default one to "
"meet their needs (the source code is available in the distribution). "
"\n\n"
"The default consistency controller can be constrained through "
"attributes";
conf_class = SIM_register_class("consistency-controller", &class_data);
/* Initialize and register the timing-model interface */
consistency_controller_timing_interface = MM_ZALLOC(1, timing_model_interface_t);
consistency_controller_timing_interface->operate = consistency_controller_operate;
SIM_register_interface(conf_class, "timing-model", consistency_controller_timing_interface);
/* Initialize attributes */
SIM_register_attribute(conf_class, "timing_model",
get_timing_model_attribute, 0,
set_timing_model_attribute, 0, Sim_Attr_Optional,
"The next memory hierarchy object");
SIM_register_attribute(conf_class, "load-load",
get_load_load, 0,
set_load_load, 0, Sim_Attr_Optional,
"If set to non-zero load-load memory consistency will be enforced.");
SIM_register_attribute(conf_class, "load-store",
get_load_store, 0,
set_load_store, 0, Sim_Attr_Optional,
"If set to non-zero load-store memory consistency will be enforced.");
SIM_register_attribute(conf_class, "store-load",
get_store_load, 0,
set_store_load, 0, Sim_Attr_Optional,
"If set to non-zero store-load memory consistency will be enforced. This is the default");
SIM_register_attribute(conf_class, "store-store",
get_store_store, 0,
set_store_store, 0, Sim_Attr_Optional,
"If set to non-zero store-store memory consistency will be enforced. This is the default.");
SIM_register_attribute(conf_class, "prefetch",
get_prefetch, 0,
set_prefetch, 0, Sim_Attr_Optional,
"If set to non-zero prefetch memory transaction will be sent to the rest "
"of the memory hierarchy for transactions that breaks the memory consistency. "
"Zero is default.");
}