/*******************************************************************************
* Code for BOARD_BootClockVLPR configuration
******************************************************************************/
void BOARD_BootClockVLPR(void)
{
/* ERR010224 */
RSIM->RF_OSC_CTRL |= RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_EN_MASK; /* Prevent XTAL_OUT_EN from generating XTAL_OUT request */
/* Set the system clock dividers in SIM to safe value. */
CLOCK_SetSimSafeDivs();
/* Set MCG to BLPI mode. */
CLOCK_BootToBlpiMode(mcgConfig_BOARD_BootClockVLPR.fcrdiv,
mcgConfig_BOARD_BootClockVLPR.ircs,
mcgConfig_BOARD_BootClockVLPR.irclkEnableMode);
/* Set the clock configuration in SIM module. */
CLOCK_SetSimConfig(&simConfig_BOARD_BootClockVLPR);
/* Set VLPR power mode. */
SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
#if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI)
SMC_SetPowerModeVlpr(SMC, false);
#else
SMC_SetPowerModeVlpr(SMC);
#endif
while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
{
}
/* Set SystemCoreClock variable. */
SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK;
}
void hal_deepsleep(void)
{
#if (defined(FSL_FEATURE_SOC_MCG_COUNT) && FSL_FEATURE_SOC_MCG_COUNT)
#if (defined(FSL_FEATURE_MCG_HAS_PLL) && FSL_FEATURE_MCG_HAS_PLL)
mcg_mode_t mode = CLOCK_GetMode();
#endif // FSL_FEATURE_MCG_HAS_PLL
#endif // FSL_FEATURE_SOC_MCG_COUNT
SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
PreEnterStopModes();
SMC_SetPowerModeVlps(SMC);
PostExitStopModes();
#if (defined(FSL_FEATURE_SOC_MCG_COUNT) && FSL_FEATURE_SOC_MCG_COUNT)
#if (defined(FSL_FEATURE_MCG_HAS_PLL) && FSL_FEATURE_MCG_HAS_PLL)
/*
* If enter stop modes when MCG in PEE mode, then after wakeup, the MCG is in PBE mode,
* need to enter PEE mode manually.
*/
if (mode == kMCG_ModePEE) {
BOARD_BootClockRUN();
}
#endif // FSL_FEATURE_MCG_HAS_PLL
#endif // FSL_FEATURE_SOC_MCG_COUNT
}
// called before main
void mbed_sdk_init() {
SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
// check the power mode source
kinetisResetSource = (rcm_reset_source_t) (RCM_GetPreviousResetSources(RCM));
// if waking up from VLLS, do some cleanup
if (kinetisResetSource & kRCM_SourceWakeup) {
PMC_ClearPeriphIOIsolationFlag(PMC);
NVIC_ClearPendingIRQ(LLWU_IRQn);
}
BOARD_BootClockRUN();
}
void BOARD_BootClockVLPR(void)
{
CLOCK_SetSimSafeDivs();
CLOCK_SetMcgliteConfig(&g_defaultClockConfigVlpr.mcgliteConfig);
CLOCK_SetSimConfig(&g_defaultClockConfigVlpr.simConfig);
SystemCoreClock = g_defaultClockConfigVlpr.coreClock;
SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
SMC_SetPowerModeVlpr(SMC);
while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
{
}
}
void BOARD_BootClockVLPR(void)
{
CLOCK_SetSimSafeDivs();
CLOCK_BootToBlpiMode(g_defaultClockConfigVlpr.mcgConfig.fcrdiv, g_defaultClockConfigVlpr.mcgConfig.ircs,
g_defaultClockConfigVlpr.mcgConfig.irclkEnableMode);
CLOCK_SetSimConfig(&g_defaultClockConfigVlpr.simConfig);
SystemCoreClock = g_defaultClockConfigVlpr.coreClock;
SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
SMC_SetPowerModeVlpr(SMC, false);
while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
{
}
}
void BOARD_BootClockHSRUN(void)
{
SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
SMC_SetPowerModeHsrun(SMC);
while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateHsrun)
{
}
CLOCK_SetSimSafeDivs();
CLOCK_InitOsc0(&g_defaultClockConfigHsrun.oscConfig);
CLOCK_SetXtal0Freq(BOARD_XTAL0_CLK_HZ);
CLOCK_BootToPeeMode(g_defaultClockConfigHsrun.mcgConfig.oscsel, kMCG_PllClkSelPll0,
&g_defaultClockConfigHsrun.mcgConfig.pll0Config);
CLOCK_SetInternalRefClkConfig(g_defaultClockConfigHsrun.mcgConfig.irclkEnableMode,
g_defaultClockConfigHsrun.mcgConfig.ircs, g_defaultClockConfigHsrun.mcgConfig.fcrdiv);
CLOCK_SetSimConfig(&g_defaultClockConfigHsrun.simConfig);
SystemCoreClock = g_defaultClockConfigHsrun.coreClock;
}
void BOARD_BootClockVLPR(void)
{
/*
* Core clock: 4MHz
* Bus clock: 4MHz
*/
const sim_clock_config_t simConfig = {
.pllFllSel = 0U, /* PLLFLLSEL select MCG FLL. */
.er32kSrc = 2U, /* ERCLK32K selection, use RTC. */
.clkdiv1 = 0x00040000U, /* SIM_CLKDIV1. */
};
CLOCK_SetSimSafeDivs();
CLOCK_BootToBlpiMode(0U, kMCG_IrcFast, kMCG_IrclkEnable);
CLOCK_SetSimConfig(&simConfig);
SystemCoreClock = 4000000U;
SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
SMC_SetPowerModeVlpr(SMC);
while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
{
}
}
void BOARD_BootClockRUN(void)
{
/*
* Core clock: 72MHz
* Bus clock: 36MHz
* Flash clock: 26MHz
*/
const mcg_pll_config_t pll0Config = {
.enableMode = 0U, .prdiv = 0x07U, .vdiv = 0x0CU,
};
const sim_clock_config_t simConfig = {
.pllFllSel = 1U, /* PLLFLLSEL select MCG PLL. */
.er32kSrc = 3U, /* ERCLK32K selection, use LPO 1 kHz. */
.clkdiv1 = 0x01020000U, /* SIM_CLKDIV1. */
};
CLOCK_SetSimSafeDivs();
BOARD_InitOsc0();
CLOCK_BootToPeeMode(kMCG_OscselOsc, kMCG_PllClkSelPll0, &pll0Config);
CLOCK_SetInternalRefClkConfig(kMCG_IrclkEnable, kMCG_IrcSlow, 0);
CLOCK_SetSimConfig(&simConfig);
SystemCoreClock = 72000000U;
}
void BOARD_InitOsc0(void)
{
const osc_config_t oscConfig = {.freq = BOARD_XTAL0_CLK_HZ,
.capLoad = 10,
.workMode = kOSC_ModeExt,
.oscerConfig = {
.enableMode = kOSC_ErClkEnable,
#if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER)
.erclkDiv = 0U,
#endif
}};
CLOCK_InitOsc0(&oscConfig);
/* Passing the XTAL0 frequency to clock driver. */
CLOCK_SetXtal0Freq(BOARD_XTAL0_CLK_HZ);
/* Use RTC_CLKIN input clock directly. */
CLOCK_SetXtal32Freq(BOARD_XTAL32K_CLK_HZ);
}
void BOARD_BootClockVLPR(void)
{
/*
* Core clock: 4MHz
*/
const sim_clock_config_t simConfig = {
.pllFllSel = 3U, /* PLLFLLSEL select IRC48MCLK. */
.pllFllDiv = 0U, /* PLLFLLSEL clock divider divisor. */
.pllFllFrac = 0U, /* PLLFLLSEL clock divider fraction. */
.er32kSrc = 2U, /* ERCLK32K selection, use RTC. */
.clkdiv1 = 0x03040000U, /* SIM_CLKDIV1. */
};
CLOCK_SetSimSafeDivs();
CLOCK_BootToBlpiMode(0U, kMCG_IrcFast, kMCG_IrclkEnable);
CLOCK_SetSimConfig(&simConfig);
SystemCoreClock = 4000000U;
SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
SMC_SetPowerModeVlpr(SMC);
while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
{
}
}
void BOARD_BootClockRUN(void)
{
/*
* Core clock: 72MHz
*/
const mcg_pll_config_t pll0Config = {
.enableMode = 0U, .prdiv = 0x00U, .vdiv = 0x08U,
};
const sim_clock_config_t simConfig = {
.pllFllSel = 1U, /* PLLFLLSEL select PLL. */
.pllFllDiv = 0U, /* PLLFLLSEL clock divider divisor. */
.pllFllFrac = 0U, /* PLLFLLSEL clock divider fraction. */
.er32kSrc = 2U, /* ERCLK32K selection, use RTC. */
.clkdiv1 = 0x15051000U, /* SIM_CLKDIV1. */
};
CLOCK_SetSimSafeDivs();
BOARD_InitOsc0();
CLOCK_BootToPeeMode(kMCG_OscselOsc, kMCG_PllClkSelPll0, &pll0Config);
CLOCK_SetInternalRefClkConfig(kMCG_IrclkEnable, kMCG_IrcSlow, 0);
CLOCK_SetSimConfig(&simConfig);
SystemCoreClock = 72000000U;
}
void BOARD_BootClockHSRUN(void)
{
/*
* Core clock: 96MHz
*/
SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
SMC_SetPowerModeHsrun(SMC);
while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateHsrun)
{
}
CLOCK_SetSimSafeDivs();
BOARD_InitOsc0();
const sim_clock_config_t simConfig = {
.pllFllSel = 1U, /* PLLFLLSEL select PLL. */
.pllFllDiv = 0U, /* PLLFLLSEL clock divider divisor. */
.pllFllFrac = 0U, /* PLLFLLSEL clock divider fraction. */
.er32kSrc = 2U, /* ERCLK32K selection, use RTC. */
.clkdiv1 = 0x03030000U, /* SIM_CLKDIV1. */
};
const mcg_pll_config_t pll0Config = {
.enableMode = 0U, .prdiv = 0x00U, .vdiv = 0x00U,
};
CLOCK_BootToPeeMode(kMCG_OscselOsc, kMCG_PllClkSelPll0, &pll0Config);
CLOCK_SetInternalRefClkConfig(kMCG_IrclkEnable, kMCG_IrcSlow, 0);
CLOCK_SetSimConfig(&simConfig);
SystemCoreClock = 96000000U;
}
void BOARD_InitOsc0(void)
{
const osc_config_t oscConfig = {.freq = BOARD_XTAL0_CLK_HZ,
.capLoad = 0,
.workMode = kOSC_ModeOscLowPower,
.oscerConfig = {
.enableMode = kOSC_ErClkEnable,
#if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER)
.erclkDiv = 0U,
#endif
}};
CLOCK_InitOsc0(&oscConfig);
/* Passing the XTAL0 frequency to clock driver. */
CLOCK_SetXtal0Freq(BOARD_XTAL0_CLK_HZ);
CLOCK_SetXtal32Freq(BOARD_XTAL32K_CLK_HZ);
}
void hal_sleep(void)
{
SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
SMC_SetPowerModeWait(SMC);
}
/*!
* @brief main function
*/
int main(void)
{
int32_t currentTemperature = 0;
uint32_t updateBoundariesCounter = 0;
int32_t tempArray[UPDATE_BOUNDARIES_TIME * 2];
lowPowerAdcBoundaries_t boundaries;
/* Init hardware */
BOARD_InitPins();
BOARD_BootClockRUN();
BOARD_InitDebugConsole();
/* Init using Led in Demo app */
LED1_INIT();
LED2_INIT();
/* Set to allow entering vlps mode */
SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeVlp);
/* Calibrate param Temperature sensor */
ADC16_CalibrateParams(DEMO_ADC16_BASEADDR);
/* Initialize Demo ADC */
if (!ADC16_InitHardwareTrigger(DEMO_ADC16_BASEADDR))
{
PRINTF("Failed to do the ADC init\r\n");
return -1;
}
PRINTF("\n\r ADC LOW POWER DEMO\n");
PRINTF("\r The Low Power ADC project is designed to work with the Tower System or in a stand alone setting\n\n");
PRINTF("\r 1. Set your target board in a place where the temperature is constant.\n");
PRINTF("\r 2. Wait until two Led light turns on.\n");
PRINTF("\r 3. Increment or decrement the temperature to see the changes.\n");
PRINTF("\r Wait two led on...\n\r");
/* setup the HW trigger source */
LPTMR_InitTriggerSourceOfAdc(DEMO_LPTMR_BASE);
ADC16_EnableDMA(DEMO_ADC16_BASEADDR, false);
NVIC_EnableIRQ(DEMO_ADC16_IRQ_ID);
/* Warm up microcontroller and allow to set first boundaries */
while (updateBoundariesCounter < (UPDATE_BOUNDARIES_TIME * 2))
{
while (!conversionCompleted)
{
}
currentTemperature = GetCurrentTempValue();
tempArray[updateBoundariesCounter] = currentTemperature;
updateBoundariesCounter++;
conversionCompleted = false;
}
/* Temp Sensor Calibration */
boundaries = TempSensorCalibration(updateBoundariesCounter, tempArray);
updateBoundariesCounter = 0;
/* Two LED is turned on indicating calibration is done */
LED1_ON();
LED2_ON();
/* Wait for user input before beginning demo */
PRINTF("\r Enter any character to begin...\n");
GETCHAR();
PRINTF("\r ---> OK! Main process is running...!\n");
while (1)
{
/* Prevents the use of wrong values */
while (!conversionCompleted)
{
}
/* Get current Temperature Value */
currentTemperature = GetCurrentTempValue();
/* Store temperature values that are going to be use to calculate average temperature */
tempArray[updateBoundariesCounter] = currentTemperature;
if (currentTemperature > boundaries.upperBoundary)
{
LED2_OFF();
LED1_ON();
}
else if (currentTemperature < boundaries.lowerBoundary)
{
LED2_ON();
LED1_OFF();
}
else
{
LED2_ON();
LED1_ON();
}
/* Call update function */
if (updateBoundariesCounter >= (UPDATE_BOUNDARIES_TIME))
{
boundaries = TempSensorCalibration(updateBoundariesCounter, tempArray);
updateBoundariesCounter = 0;
}
else
{
updateBoundariesCounter++;
}
/* Clear conversionCompleted flag */
conversionCompleted = false;
/* Enter to Very Low Power Stop Mode */
SMC_SetPowerModeVlps(SMC);
}
}
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockVLPR
outputs:
- {id: Bus_clock.outFreq, value: 800 kHz}
- {id: Core_clock.outFreq, value: 4 MHz}
- {id: Flash_clock.outFreq, value: 800 kHz}
- {id: LPO_clock.outFreq, value: 1 kHz}
- {id: MCGIRCLK.outFreq, value: 4 MHz}
- {id: System_clock.outFreq, value: 4 MHz}
settings:
- {id: MCGMode, value: BLPI}
- {id: powerMode, value: VLPR}
- {id: MCG.CLKS.sel, value: MCG.IRCS}
- {id: MCG.FCRDIV.scale, value: '1'}
- {id: MCG.IRCS.sel, value: MCG.FCRDIV}
- {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
- {id: SIM.OUTDIV4.scale, value: '5'}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
void BOARD_BootClockVLPR(void)
{
const sim_clock_config_t simConfig = {
.er32kSrc = 0U, .clkdiv1 = 0x00040000U,
};
/* ERR010224 */
RSIM->RF_OSC_CTRL |= RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_EN_MASK; /* Prevent XTAL_OUT_EN from generating XTAL_OUT request */
CLOCK_SetSimSafeDivs();
CLOCK_BootToBlpiMode(0U, kMCG_IrcFast, kMCG_IrclkEnable);
CLOCK_SetSimConfig(&simConfig);
SystemCoreClock = 4000000U;
SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
SMC_SetPowerModeVlpr(SMC);
while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
{
}
}
/*******************************************************************************
********************** Configuration BOARD_BootClockRUN ***********************
******************************************************************************/
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockRUN
called_from_default_init: true
outputs:
- {id: Bus_clock.outFreq, value: 20 MHz}
- {id: Core_clock.outFreq, value: 40 MHz}
- {id: Flash_clock.outFreq, value: 20 MHz}
- {id: LPO_clock.outFreq, value: 1 kHz}
- {id: MCGFLLCLK.outFreq, value: 40 MHz}
- {id: MCGIRCLK.outFreq, value: 32.768 kHz}
- {id: OSCERCLK.outFreq, value: 32 MHz}
- {id: System_clock.outFreq, value: 40 MHz}
settings:
- {id: MCGMode, value: FEE}
- {id: MCG.FCRDIV.scale, value: '1'}
- {id: MCG.FLL_mul.scale, value: '1280'}
- {id: MCG.FRDIV.scale, value: '1024'}
- {id: MCG.IREFS.sel, value: MCG.FRDIV}
- {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
- {id: MCG_C2_RANGE0_FRDIV_CFG, value: Very_high}
- {id: MCG_C2_RANGE_CFG, value: Very_high}
- {id: RTC_CR_OSCE_CFG, value: Oscillator_enabled}
sources:
- {id: REFOSC.OSC.outFreq, value: 32 MHz, enabled: true}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
void BOARD_BootClockRUN(void)
{
const sim_clock_config_t simConfig = {
.er32kSrc = 0U, .clkdiv1 = 0x00010000U,
};
BOARD_RfOscInit();
CLOCK_SetSimSafeDivs();
BOARD_InitOsc0();
CLOCK_BootToFeeMode(kMCG_OscselOsc, 5U, kMCG_Dmx32Default, kMCG_DrsMid, CLOCK_SYS_FllStableDelay);
CLOCK_SetInternalRefClkConfig(kMCG_IrclkEnable, kMCG_IrcSlow, 0U);
CLOCK_SetSimConfig(&simConfig);
SystemCoreClock = 40000000U;
}
void BOARD_RfOscInit(void)
{
uint32_t temp, tempTrim;
uint8_t revId;
/* Obtain REV ID from SIM */
temp = SIM->SDID;
revId = (uint8_t)((temp & SIM_SDID_REVID_MASK) >> SIM_SDID_REVID_SHIFT);
if(0 == revId)
{
tempTrim = RSIM->ANA_TRIM;
RSIM->ANA_TRIM |= RSIM_ANA_TRIM_BB_LDO_XO_TRIM_MASK; /* Set max trim for BB LDO for XO */
}/* Workaround for Rev 1.0 XTAL startup and ADC analog diagnostics circuitry */
/* Turn on clocks for the XCVR */
/* Enable RF OSC in RSIM and wait for ready */
temp = RSIM->CONTROL;
temp &= ~RSIM_CONTROL_RF_OSC_EN_MASK;
RSIM->CONTROL = temp | RSIM_CONTROL_RF_OSC_EN(1);
/* ERR010224 */
RSIM->RF_OSC_CTRL |= RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_EN_MASK; /* Prevent XTAL_OUT_EN from generating XTAL_OUT request */
while((RSIM->CONTROL & RSIM_CONTROL_RF_OSC_READY_MASK) == 0); /* Wait for RF_OSC_READY */
if(0 == revId)
{
SIM->SCGC5 |= SIM_SCGC5_PHYDIG_MASK;
XCVR_TSM->OVRD0 |= XCVR_TSM_OVRD0_BB_LDO_ADCDAC_EN_OVRD_EN_MASK | XCVR_TSM_OVRD0_BB_LDO_ADCDAC_EN_OVRD_MASK; /* Force ADC DAC LDO on to prevent BGAP failure */
RSIM->ANA_TRIM = tempTrim; /* Reset LDO trim settings */
}/* Workaround for Rev 1.0 XTAL startup and ADC analog diagnostics circuitry */
}
void BOARD_InitOsc0(void)
{
const osc_config_t oscConfig = {
.freq = BOARD_XTAL0_CLK_HZ, .workMode = kOSC_ModeExt,
};
CLOCK_InitOsc0(&oscConfig);
/* Passing the XTAL0 frequency to clock driver. */
CLOCK_SetXtal0Freq(BOARD_XTAL0_CLK_HZ);
}
void BOARD_BootClockVLPR(void)
{
/*
* Core clock: 4MHz
*/
const sim_clock_config_t simConfig = {
.pllFllSel = 0U, /* PLLFLLSEL select FLL. */
.er32kSrc = 2U, /* ERCLK32K selection, use RTC. */
.clkdiv1 = 0x00030000U, /* SIM_CLKDIV1. */
};
CLOCK_SetSimSafeDivs();
CLOCK_BootToBlpiMode(0U, kMCG_IrcFast, kMCG_IrclkEnable);
CLOCK_SetSimConfig(&simConfig);
SystemCoreClock = 4000000U;
SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
SMC_SetPowerModeVlpr(SMC, false);
while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
{
}
}
void BOARD_BootClockRUN(void)
{
/*
* Core clock: 48MHz
* Bus clock: 24MHz
*/
const mcg_pll_config_t pll0Config = {
.enableMode = 0U,
.prdiv = 0x1U,
.vdiv = 0x0U,
};
const sim_clock_config_t simConfig = {
.pllFllSel = 1U, /* PLLFLLSEL select PLL. */
.er32kSrc = 2U, /* ERCLK32K selection, use RTC. */
.clkdiv1 = 0x00010000U, /* SIM_CLKDIV1. */
};
/* Perform initialization of the wireless modem clock output */
if (BOARD_ExtClk_Setup_HookUp(BOARD_XTAL0_CLK_HZ) != 1U)
{
/* If the initialization was not successfully, do not continue with clock setup */
return;
}
CLOCK_SetSimSafeDivs();
BOARD_InitOsc0();
CLOCK_BootToPeeMode(kMCG_OscselOsc, kMCG_PllClkSelPll0, &pll0Config);
CLOCK_SetInternalRefClkConfig(kMCG_IrclkEnable, kMCG_IrcSlow, 0);
CLOCK_SetSimConfig(&simConfig);
SystemCoreClock = 48000000U;
}
void BOARD_InitOsc0(void)
{
const osc_config_t oscConfig = {.freq = BOARD_XTAL0_CLK_HZ,
.capLoad = 0,
.workMode = kOSC_ModeOscLowPower,
.oscerConfig = {
.enableMode = kOSC_ErClkEnable | kOSC_ErClkEnableInStop,
#if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER)
.erclkDiv = 0U,
#endif
}};
CLOCK_InitOsc0(&oscConfig);
/* Passing the XTAL0 frequency to clock driver. */
CLOCK_SetXtal0Freq(BOARD_XTAL0_CLK_HZ);
}
