/*acore bus dfs handle*/
int bus_minfreq_handle(unsigned int req_value)
{
    /*get dfs switch flag*/
    if(RET_OK != pwrctrl_is_func_on(PWC_SWITCH_BDFS))
    {
        return RET_ERR;
    }

    if(DFS_BUS_FREQ_MIN >= req_value)
    {
        /*set SC_MCU_VOTE2DIS0 bit,vote lock,enable bus dfs*/
#if defined(CHIP_BB_HI6210) /*B020 Modify*/
	pwrctrl_set_bits(IO_ADDRESS(SOC_AO_SCTRL_SC_MCU_VOTE2DIS_ADDR(SOC_AO_SCTRL_BASE_ADDR)), BIT(BUS_DFS_BIT_ACPU));
#else
        pwrctrl_set_bits(IO_ADDRESS(SOC_AO_SCTRL_SC_MCU_VOTE2DIS0_ADDR(SOC_SC_ON_BASE_ADDR)), BIT(BUS_DFS_BIT_ACPU));
#endif
    }
    else
    {
        /*set SC_MCU_VOTE2EN0 bit,vote unlock,disable bus dfs*/
#if defined(CHIP_BB_HI6210)/*B020 Modify*/
		pwrctrl_set_bits(IO_ADDRESS(SOC_AO_SCTRL_SC_MCU_VOTE2EN_ADDR(SOC_AO_SCTRL_BASE_ADDR)), BIT(BUS_DFS_BIT_ACPU));
#else
        pwrctrl_set_bits(IO_ADDRESS(SOC_AO_SCTRL_SC_MCU_VOTE2EN0_ADDR(SOC_SC_ON_BASE_ADDR)), BIT(BUS_DFS_BIT_ACPU));
#endif
    }
    return RET_OK;

}
int buslow_minfreq_handle(unsigned int req_value)
{
    unsigned int reg_val;
    void __iomem *reg_addr;
    u32 busdfs = 0;
    struct device_node *root;

	root = of_find_compatible_node(NULL,NULL,"hisilicon,hi6210");
	if (!root){
		pr_err("[%s] find root node fail!\n",
			__func__);
		return RET_ERR;
	}

	if (of_property_read_u32(root, "power,busdfs", &busdfs)) {
		pr_err("[%s] node doesn't have this property!\n",
			__func__);
		return RET_ERR;
	}

	if (busdfs == 0){
		return RET_OK;
	}else{
        /*get dfs switch flag*/

        if(DFS_BUSLOW_FREQ_MIN >= req_value)
        {
            reg_addr = (void __iomem *)HISI_VA_ADDRESS(SOC_AO_SCTRL_SC_MCU_VOTE2DIS_ADDR(SOC_AO_SCTRL_BASE_ADDR));
            /*set SC_MCU_VOTE2DIS bit,vote lock,enable bus100M dfs*/
            reg_val = readl(reg_addr);
            writel((reg_val | BIT(BUS_DFS_BIT_ACPU)), reg_addr);
        }
        else
        {
            reg_addr = (void __iomem *)HISI_VA_ADDRESS(SOC_AO_SCTRL_SC_MCU_VOTE2EN_ADDR(SOC_AO_SCTRL_BASE_ADDR));
            /*set SC_MCU_VOTE2EN bit,vote unlock,disable bus100M dfs*/
            reg_val = readl(reg_addr);
            writel((reg_val | BIT(BUS_DFS_BIT_ACPU)), reg_addr);
        }
    }
    return RET_OK;

}

/*****************************************************************************
  2 全局变量定义
*****************************************************************************/
u32_t g_aAcpuStoreReg[PWC_STORE_MEM_SIZE] = {0};

u32_t g_aAcpuHwVoteBaseAddr[] =
{
#if defined(CHIP_BB_HI6210)/*B020 Modify*/
    IO_ADDRESS(SOC_AO_SCTRL_SC_MCPU_VOTEEN_ADDR(SOC_AO_SCTRL_BASE_ADDR)),
    IO_ADDRESS(SOC_AO_SCTRL_SC_PERI_VOTEEN_ADDR(SOC_AO_SCTRL_BASE_ADDR)),
    IO_ADDRESS(SOC_AO_SCTRL_SC_ACPU_VOTEEN_ADDR(SOC_AO_SCTRL_BASE_ADDR)),
    IO_ADDRESS(SOC_AO_SCTRL_SC_MCU_VOTEEN_ADDR(SOC_AO_SCTRL_BASE_ADDR)),
    IO_ADDRESS(SOC_AO_SCTRL_SC_MCU_VOTE1EN_ADDR(SOC_AO_SCTRL_BASE_ADDR)),
    IO_ADDRESS(SOC_AO_SCTRL_SC_MCU_VOTE2EN_ADDR(SOC_AO_SCTRL_BASE_ADDR)),
#else
    IO_ADDRESS(SOC_AO_SCTRL_SC_MCPU_VOTEEN0_ADDR(SOC_SC_ON_BASE_ADDR)),
    IO_ADDRESS(SOC_AO_SCTRL_SC_PERI_VOTEEN0_ADDR(SOC_SC_ON_BASE_ADDR)),
    IO_ADDRESS(SOC_AO_SCTRL_SC_ACPU_VOTEEN0_ADDR(SOC_SC_ON_BASE_ADDR)),
    IO_ADDRESS(SOC_AO_SCTRL_SC_MCU_VOTEEN0_ADDR(SOC_SC_ON_BASE_ADDR)),
    IO_ADDRESS(SOC_AO_SCTRL_SC_MCU_VOTE1EN0_ADDR(SOC_SC_ON_BASE_ADDR)),
    IO_ADDRESS(SOC_AO_SCTRL_SC_MCU_VOTE2EN0_ADDR(SOC_SC_ON_BASE_ADDR)),
#endif

};

ST_STORE_REG_ADDR_INFO g_aAcpuSocRegTable[] =
{
#if defined(CHIP_BB_HI6210)