static void nrf24l01_lock(FAR struct spi_dev_s *spi) { /* Lock the SPI bus because there are multiple devices competing for the * SPI bus */ (void)SPI_LOCK(spi, true); /* We have the lock. Now make sure that the SPI bus is configured for the * NRF24L01 (it might have gotten configured for a different device while * unlocked) */ SPI_SELECT(spi, SPIDEV_WIRELESS, true); SPI_SETMODE(spi, SPIDEV_MODE0); SPI_SETBITS(spi, 8); SPI_SETFREQUENCY(spi, NRF24L01_SPIFREQ); SPI_SELECT(spi, SPIDEV_WIRELESS, false); }
static void ads7843e_lock(FAR struct spi_dev_s *spi) { /* Lock the SPI bus because there are multiple devices competing for the * SPI bus */ (void)SPI_LOCK(spi, true); /* We have the lock. Now make sure that the SPI bus is configured for the * ADS7843 (it might have gotten configured for a different device while * unlocked) */ SPI_SELECT(spi, SPIDEV_TOUCHSCREEN, true); SPI_SETMODE(spi, CONFIG_ADS7843E_SPIMODE); SPI_SETBITS(spi, 8); SPI_SETFREQUENCY(spi, CONFIG_ADS7843E_FREQUENCY); SPI_SELECT(spi, SPIDEV_TOUCHSCREEN, false); }
static void ssd1351_select(FAR struct ssd1351_dev_s *priv) { FAR struct spi_dev_s *spi = priv->spi; /* Select the chip, locking the SPI bus in case there are multiple devices * competing for the SPI bus */ gdbg("SELECTED\n"); SPI_LOCK(spi, true); SPI_SELECT(spi, SPIDEV_DISPLAY, true); /* Now make sure that the SPI bus is configured for this device (it might * have gotten configured for a different device while unlocked) */ SPI_SETMODE(spi, CONFIG_SSD1351_SPIMODE); SPI_SETBITS(spi, SSD1351_SPIBITS); (void)SPI_HWFEATURES(spi, 0); (void)SPI_SETFREQUENCY(spi, CONFIG_SSD1351_SPIFREQ); }
static void pga11x_lock(FAR struct spi_dev_s *spi) { spivdbg("Locking\n"); /* On SPI busses where there are multiple devices, it will be necessary to * lock SPI to have exclusive access to the busses for a sequence of * transfers. The bus should be locked before the chip is selected. * * This is a blocking call and will not return until we have exclusiv access to * the SPI buss. We will retain that exclusive access until the bus is unlocked. */ SPI_LOCK(spi, true); /* After locking the SPI bus, the we also need call the setfrequency, setbits, and * setmode methods to make sure that the SPI is properly configured for the device. * If the SPI buss is being shared, then it may have been left in an incompatible * state. */ pga11x_configure(spi); }
static void ramtron_lock(FAR struct ramtron_dev_s *priv) { /* On SPI busses where there are multiple devices, it will be necessary to * lock SPI to have exclusive access to the busses for a sequence of * transfers. The bus should be locked before the chip is selected. * * This is a blocking call and will not return until we have exclusiv access to * the SPI buss. We will retain that exclusive access until the bus is unlocked. */ (void)SPI_LOCK(priv->dev, true); /* After locking the SPI bus, the we also need call the setfrequency, setbits, and * setmode methods to make sure that the SPI is properly configured for the device. * If the SPI buss is being shared, then it may have been left in an incompatible * state. */ SPI_SETMODE(priv->dev, SPIDEV_MODE3); SPI_SETBITS(priv->dev, 8); (void)SPI_SETFREQUENCY(priv->dev, priv->speed); }
static void ee25xx_lock(FAR struct spi_dev_s *dev) { /* On SPI buses where there are multiple devices, it will be necessary to * lock SPI to have exclusive access to the buses for a sequence of * transfers. The bus should be locked before the chip is selected. * * This is a blocking call and will not return until we have exclusive * access to the SPI bus. We will retain that exclusive access until the * bus is unlocked. */ (void)SPI_LOCK(dev, true); /* After locking the SPI bus, the we also need call the setfrequency, * setbits, and setmode methods to make sure that the SPI is properly * configured for the device. If the SPI bus is being shared, then it may * have been left in an incompatible state. */ SPI_SETMODE(dev, CONFIG_EE25XX_SPIMODE); SPI_SETBITS(dev, 8); (void)SPI_HWFEATURES(dev, 0); (void)SPI_SETFREQUENCY(dev, 10000000); /* This is the default speed */ }
static inline void ee25xx_unlock(FAR struct spi_dev_s *dev) { (void)SPI_LOCK(dev, false); }
static void max11802_unlock(FAR struct spi_dev_s *spi) { /* Relinquish the SPI bus. */ (void)SPI_LOCK(spi, false); }
void cc1101_access_end(struct cc1101_dev_s * dev) { SPI_SELECT(dev->spi, SPIDEV_WIRELESS, false); (void)SPI_LOCK(dev->spi, false); }
static void max6675_unlock(FAR struct spi_dev_s *spi) { (void)SPI_LOCK(spi, false); }
static inline void ramtron_unlock(FAR struct spi_dev_s *dev) { (void)SPI_LOCK(dev, false); }
static inline void pga11x_unlock(FAR struct spi_dev_s *spi) { spivdbg("Unlocking\n"); SPI_LOCK(spi, false); }
int mpu6000_attach(struct spi_dev_s *spi, int spi_id) { int result = ERROR; mpu6000_dev.spi = spi; mpu6000_dev.spi_id = spi_id; SPI_LOCK(mpu6000_dev.spi, true); // Set sensor-specific SPI mode SPI_SETFREQUENCY(mpu6000_dev.spi, 10000000); // 500 KHz SPI_SETBITS(mpu6000_dev.spi, 8); // Either mode 1 or mode 3 SPI_SETMODE(mpu6000_dev.spi, SPIDEV_MODE3); // Chip reset mpu6000_write_reg(MPUREG_PWR_MGMT_1, BIT_H_RESET); up_udelay(10000); // Wake up device and select GyroZ clock (better performance) mpu6000_write_reg(MPUREG_PWR_MGMT_1, MPU_CLK_SEL_PLLGYROZ); up_udelay(1000); // Disable I2C bus (recommended on datasheet) mpu6000_write_reg(MPUREG_USER_CTRL, BIT_I2C_IF_DIS); up_udelay(1000); // SAMPLE RATE mpu6000_write_reg(MPUREG_SMPLRT_DIV,0x04); // Sample rate = 200Hz Fsample= 1Khz/(4+1) = 200Hz usleep(1000); // FS & DLPF FS=2000¼/s, DLPF = 98Hz (low pass filter) mpu6000_write_reg(MPUREG_CONFIG, BITS_DLPF_CFG_98HZ); usleep(1000); mpu6000_write_reg(MPUREG_GYRO_CONFIG,BITS_FS_2000DPS); // Gyro scale 2000¼/s usleep(1000); uint8_t _product_id = mpu6000_read_reg(MPUREG_PRODUCT_ID); printf("MPU-6000 product id: %d\n", (int)_product_id); if ((_product_id == MPU6000ES_REV_C4) || (_product_id == MPU6000ES_REV_C5) || (_product_id == MPU6000_REV_C4) || (_product_id == MPU6000_REV_C5)){ // Accel scale 8g (4096 LSB/g) // Rev C has different scaling than rev D mpu6000_write_reg(MPUREG_ACCEL_CONFIG,1<<3); } else { // Accel scale 8g (4096 LSB/g) mpu6000_write_reg(MPUREG_ACCEL_CONFIG,2<<3); } usleep(1000); // INT CFG => Interrupt on Data Ready mpu6000_write_reg(MPUREG_INT_ENABLE,BIT_RAW_RDY_EN); // INT: Raw data ready usleep(1000); mpu6000_write_reg(MPUREG_INT_PIN_CFG,BIT_INT_ANYRD_2CLEAR); // INT: Clear on any read usleep(1000); // Oscillator set // write_reg(MPUREG_PWR_MGMT_1,MPU_CLK_SEL_PLLGYROZ); usleep(1000); /* revert back to normal bus mode */ SPI_SETFREQUENCY(mpu6000_dev.spi, 10000000); SPI_SETBITS(mpu6000_dev.spi, 8); SPI_SETMODE(mpu6000_dev.spi, SPIDEV_MODE3); /* verify that the device is attached and functioning */ if ((_product_id == MPU6000ES_REV_C4) || (_product_id == MPU6000ES_REV_C5) || (_product_id == MPU6000_REV_C4) || (_product_id == MPU6000_REV_C5) || (_product_id == MPU6000_REV_D7) || (_product_id == MPU6000_REV_D8) || (_product_id == MPU6000_REV_D9) || (_product_id == MPU6000_REV_D10)){ /* make ourselves available */ register_driver("/dev/mpu6000", &mpu6000_fops, 0666, NULL); result = OK; } else { errno = EIO; } SPI_LOCK(mpu6000_dev.spi, false); SPI_LOCK(mpu6000_dev.spi, false); return result; }
static void pn532_unlock(FAR struct spi_dev_s *spi) { (void)SPI_LOCK(spi, false); }