static void ramtron_waitwritecomplete(struct ramtron_dev_s *priv)
{
uint8_t status;
/* Select this FLASH part */
SPI_SELECT(priv->dev, SPIDEV_FLASH, true);
/* Send "Read Status Register (RDSR)" command */
(void)SPI_SEND(priv->dev, RAMTRON_RDSR);
/* Loop as long as the memory is busy with a write cycle */
do
{
/* Send a dummy byte to generate the clock needed to shift out the status */
status = SPI_SEND(priv->dev, RAMTRON_DUMMY);
}
while ((status & RAMTRON_SR_WIP) != 0);
/* Deselect the FLASH */
SPI_SELECT(priv->dev, SPIDEV_FLASH, false);
fvdbg("Complete\n");
}
void adxl345_putreg8(FAR struct adxl345_dev_s *priv, uint8_t regaddr,
uint8_t regval)
{
#ifdef CONFIG_ADXL345_REGDEBUG
dbg("%02x<-%02x\n", regaddr, regval);
#endif
/* If SPI bus is shared then lock and configure it */
#ifndef CONFIG_SPI_OWNBUS
(void)SPI_LOCK(priv->spi, true);
adxl345_configspi(priv->spi);
#endif
/* Select the ADXL345 */
SPI_SELECT(priv->spi, SPIDEV_GSENSOR, true);
/* Send register address and set the value */
(void)SPI_SEND(priv->spi, regaddr);
(void)SPI_SEND(priv->spi, regval);
/* Deselect the ADXL345 */
SPI_SELECT(priv->spi, SPIDEV_GSENSOR, false);
/* Unlock bus */
#ifndef CONFIG_SPI_OWNBUS
(void)SPI_LOCK(priv->spi, false);
#endif
}
static inline int ramtron_readid(struct ramtron_dev_s *priv)
{
uint16_t manufacturer, memory, capacity, part;
int i;
fvdbg("priv: %p\n", priv);
/* Lock the SPI bus, configure the bus, and select this FLASH part. */
ramtron_lock(priv);
SPI_SELECT(priv->dev, SPIDEV_FLASH, true);
/* Send the "Read ID (RDID)" command and read the first three ID bytes */
(void)SPI_SEND(priv->dev, RAMTRON_RDID);
for (i = 0; i < 6; i++)
{
manufacturer = SPI_SEND(priv->dev, RAMTRON_DUMMY);
/*
* Fujitsu parts such as MB85RS1MT only have 1-byte for the manufacturer
* ID. The manufacturer code is "0x4".
*/
if (manufacturer == 0x4)
break;
}
memory = SPI_SEND(priv->dev, RAMTRON_DUMMY);
capacity = SPI_SEND(priv->dev, RAMTRON_DUMMY); // fram.id1
part = SPI_SEND(priv->dev, RAMTRON_DUMMY); // fram.id2
/* Deselect the FLASH and unlock the bus */
SPI_SELECT(priv->dev, SPIDEV_FLASH, false);
ramtron_unlock(priv->dev);
/* Select part from the part list */
for (priv->part = ramtron_parts;
priv->part->name != NULL && !(priv->part->id1 == capacity && priv->part->id2 == part);
priv->part++);
if (priv->part->name)
{
fvdbg("RAMTRON %s of size %d bytes (mf:%02x mem:%02x cap:%02x part:%02x)\n",
priv->part->name, priv->part->size, manufacturer, memory, capacity, part);
priv->sectorshift = RAMTRON_EMULATE_SECTOR_SHIFT;
priv->nsectors = priv->part->size / (1 << RAMTRON_EMULATE_SECTOR_SHIFT);
priv->pageshift = RAMTRON_EMULATE_PAGE_SHIFT;
priv->npages = priv->part->size / (1 << RAMTRON_EMULATE_PAGE_SHIFT);
priv->speed = priv->part->speed;
return OK;
}
fvdbg("RAMTRON device not found\n");
return -ENODEV;
}
static uint8_t pn532_status(struct pn532_dev_s *dev)
{
int rs;
pn532_lock(dev->spi);
pn532_select(dev);
rs = SPI_SEND(dev->spi, PN532_SPI_STATREAD);
rs = SPI_SEND(dev->spi, PN532_SPI_STATREAD);
pn532_deselect(dev);
pn532_unlock(dev->spi);
return rs;
}
int pn532_write_frame(struct pn532_dev_s *dev, struct pn532_frame *f)
{
int res = OK;
pn532_lock(dev->spi);
pn532_select(dev);
nxsig_usleep(2000);
SPI_SEND(dev->spi, PN532_SPI_DATAWRITE);
SPI_SNDBLOCK(dev->spi, f, FRAME_SIZE(f));
pn532_deselect(dev);
pn532_unlock(dev->spi);
tracetx("WriteFrame", (uint8_t *) f, FRAME_SIZE(f));
/* Wait ACK frame */
res = pn532_wait_rx_ready(dev, 30);
if (res == OK)
{
if (!pn532_read_ack(dev))
{
pn532err("ERROR: command FAILED\n");
res = -EIO;
}
}
return res;
}
static uint16_t max11802_sendcmd(FAR struct max11802_dev_s *priv,
uint8_t cmd, int *tags)
{
uint8_t buffer[2];
uint16_t result;
/* Select the MAX11802 */
SPI_SELECT(priv->spi, SPIDEV_TOUCHSCREEN, true);
/* Send the command */
(void)SPI_SEND(priv->spi, cmd);
/* Read the data */
SPI_RECVBLOCK(priv->spi, buffer, 2);
SPI_SELECT(priv->spi, SPIDEV_TOUCHSCREEN, false);
result = ((uint16_t)buffer[0] << 8) | (uint16_t)buffer[1];
*tags = result & 0xF;
result >>= 4; /* Get rid of tags */
iinfo("cmd:%02x response:%04x\n", cmd, result);
return result;
}
static void ssd1351_write(FAR struct ssd1351_dev_s *priv, uint8_t cmd,
FAR const uint8_t *data, size_t datlen)
{
FAR struct spi_dev_s *spi = priv->spi;
/* Sanity check */
DEBUGASSERT(priv != NULL);
DEBUGASSERT((data == NULL && datlen == 0) || (data != NULL && datlen > 0));
/* Select command transfer */
(void)SPI_CMDDATA(spi, SPIDEV_DISPLAY, true);
/* Send the command */
(void)SPI_SEND(spi, cmd);
/* Do we have any data to send? */
if (datlen > 0)
{
/* Yes, select data transfer */
(void)SPI_CMDDATA(spi, SPIDEV_DISPLAY, false);
/* Transfer all of the data */
(void)SPI_SNDBLOCK(spi, data, datlen);
}
}
static uint16_t ads7843e_sendcmd(FAR struct ads7843e_dev_s *priv, uint8_t cmd)
{
uint8_t buffer[2];
uint16_t result;
/* Select the ADS7843E */
SPI_SELECT(priv->spi, SPIDEV_TOUCHSCREEN, true);
/* Send the command */
(void)SPI_SEND(priv->spi, cmd);
ads7843e_waitbusy(priv);
/* Read the data */
SPI_RECVBLOCK(priv->spi, buffer, 2);
SPI_SELECT(priv->spi, SPIDEV_TOUCHSCREEN, false);
result = ((uint16_t)buffer[0] << 8) | (uint16_t)buffer[1];
result = result >> 4;
ivdbg("cmd:%02x response:%04x\n", cmd, result);
return result;
}
static uint16_t ads7843e_sendcmd(FAR struct ads7843e_dev_s *priv, uint8_t cmd)
{
uint8_t buffer[2];
uint16_t result;
/* Select the ADS7843E */
SPI_SELECT(priv->spi, SPIDEV_TOUCHSCREEN, true);
/* Send the command */
(void)SPI_SEND(priv->spi, cmd);
/* Wait a tiny amount to make sure that the aquisition time is complete */
up_udelay(3); /* 3 microseconds */
/* Read the 12-bit data (LS 4 bits will be padded with zero) */
SPI_RECVBLOCK(priv->spi, buffer, 2);
SPI_SELECT(priv->spi, SPIDEV_TOUCHSCREEN, false);
result = ((uint16_t)buffer[0] << 8) | (uint16_t)buffer[1];
result = result >> 4;
ivdbg("cmd:%02x response:%04x\n", cmd, result);
return result;
}
uint8_t CONTROLLER_BYTE(uint8_t _data) {
SET(C_PORT,CMD);
SET(C_PORT,CLK);
CLR(C_PORT,ATT);
DelaySmall;
return SPI_SEND(_data);
}
static uint8_t nrf24l01_access(FAR struct nrf24l01_dev_s *dev,
nrf24l01_access_mode_t mode, uint8_t cmd, FAR uint8_t *buf, int length)
{
uint8_t status;
/* Prepare SPI */
nrf24l01_select(dev);
/* Transfer */
status = SPI_SEND(dev->spi, cmd);
switch (mode)
{
case MODE_WRITE:
if (length > 0)
{
SPI_SNDBLOCK(dev->spi, buf, length);
}
break;
case MODE_READ:
SPI_RECVBLOCK(dev->spi, buf, length);
break;
}
nrf24l01_deselect(dev);
return status;
}
uint8_t adxl345_getreg8(FAR struct adxl345_dev_s *priv, uint8_t regaddr)
{
uint8_t regval;
/* If SPI bus is shared then lock and configure it */
#ifndef CONFIG_SPI_OWNBUS
(void)SPI_LOCK(priv->spi, true);
adxl345_configspi(priv->spi);
#endif
/* Select the ADXL345 */
SPI_SELECT(priv->spi, SPIDEV_GSENSOR, true);
/* Send register to read and get the next byte */
(void)SPI_SEND(priv->spi, regaddr);
SPI_RECVBLOCK(priv->spi, ®val, 1);
/* Deselect the ADXL345 */
SPI_SELECT(priv->spi, SPIDEV_GSENSOR, false);
/* Unlock bus */
#ifndef CONFIG_SPI_OWNBUS
(void)SPI_LOCK(priv->spi, false);
#endif
#ifdef CONFIG_ADXL345_REGDEBUG
dbg("%02x->%02x\n", regaddr, regval);
#endif
return regval;
}
static uint16_t pga11x_recv16(FAR struct spi_dev_s *spi)
{
uint8_t msb;
uint8_t lsb;
/* The logical interface is 16-bits wide. However, this driver uses a
* 8-bit configuration for greaer portability.
*
* Send a dummy byte and receive MS byte first. Then the LS byte.
*/
msb = SPI_SEND(spi, SPI_DUMMY);
lsb = SPI_SEND(spi, SPI_DUMMY);
spivdbg("Received %02x %02x\n", msb, lsb);
return ((uint16_t)msb << 8) | (uint16_t)lsb;
}
int cc1101_access(struct cc1101_dev_s * dev, uint8_t addr, uint8_t *buf, int length)
{
int stabyte;
/* Address cannot explicitly define READ command while length WRITE.
* Also access to these cells is only permitted as one byte, eventhough
* transfer is marked as BURST!
*/
if ((addr & CC1101_READ_SINGLE) && length != 1)
return ERROR;
/* Prepare SPI */
cc1101_access_begin(dev);
if (length>1 || length < -1)
SPI_SETFREQUENCY(dev->spi, CC1101_SPIFREQ_BURST);
else SPI_SETFREQUENCY(dev->spi, CC1101_SPIFREQ_SINGLE);
/* Transfer */
if (length <= 0) { /* 0 length are command strobes */
if (length < -1)
addr |= CC1101_WRITE_BURST;
stabyte = SPI_SEND(dev->spi, addr);
if (length) {
SPI_SNDBLOCK(dev->spi, buf, -length);
}
}
else {
addr |= CC1101_READ_SINGLE;
if (length > 1)
addr |= CC1101_READ_BURST;
stabyte = SPI_SEND(dev->spi, addr);
SPI_RECVBLOCK(dev->spi, buf, length);
}
cc1101_access_end(dev);
return stabyte;
}
static int ramtron_waitwritecomplete(struct ramtron_dev_s *priv)
{
uint8_t status;
/* Select this FLASH part */
SPI_SELECT(priv->dev, SPIDEV_FLASH, true);
/* Send "Read Status Register (RDSR)" command */
(void)SPI_SEND(priv->dev, RAMTRON_RDSR);
/* Loop as long as the memory is busy with a write cycle,
* but limit the cycles.
*
* RAMTRON FRAM is never busy per spec compared to flash,
* and so anything exceeding the default timeout number
* is highly suspicious.
*/
unsigned int tries = 100; // XXX should be CONFIG_MTD_RAMTRON_WRITEWAIT_COUNT
do
{
/* Send a dummy byte to generate the clock needed to shift out the status */
status = SPI_SEND(priv->dev, RAMTRON_DUMMY);
tries--;
}
while ((status & RAMTRON_SR_WIP) != 0 && tries > 0);
/* Deselect the FLASH */
SPI_SELECT(priv->dev, SPIDEV_FLASH, false);
fvdbg("Complete\n");
if (tries == 0) {
fdbg("timeout waiting for write completion\n");
return -EAGAIN;
}
return OK;
}
DRESULT disk_writep (
const BYTE *buff, /* Pointer to the bytes to be written (NULL:Initiate/Finalize sector write) */
DWORD sa /* Number of bytes to send, Sector number (LBA) or zero */
)
{
DRESULT res;
WORD bc;
UINT tmr;
static WORD wc;
res = RES_ERROR;
if (buff) { /* Send data bytes */
bc = (WORD)sa;
while (bc && wc) { /* Send data bytes to the card */
SPI_SEND(*buff++);
wc--; bc--;
}
res = RES_OK;
} else {
if (sa) { /* Initiate sector write process */
if (!(CardType & CT_BLOCK)) sa *= 512; /* Convert to byte address if needed */
if (send_cmd(CMD24, sa) == 0) { /* WRITE_SINGLE_BLOCK */
SPI_SEND(0xFF); SPI_SEND(0xFE); /* Data block header */
wc = 512; /* Set byte counter */
res = RES_OK;
}
} else { /* Finalize sector write process */
bc = wc + 2;
while (bc--) SPI_SEND(0x00); /* Fill left bytes and CRC with zeros */
if ((SPI_RECEIVE() & 0x1F) == 0x05) { /* Receive data resp and wait for end of write process in timeout of 500ms */
for (tmr = 10000; SPI_RECEIVE() != 0xFF && tmr; tmr--) DLY100U();//delayMicroseconds(100);//DELAY_100US(); /* Wait ready */
if (tmr) res = RES_OK;
}
DESELECT();
SPI_RECEIVE();
}
}
return res;
}
int pn532_read(struct pn532_dev_s *dev, uint8_t *buff, uint8_t n)
{
pn532_lock(dev->spi);
pn532_select(dev);
SPI_SEND(dev->spi, PN532_SPI_DATAREAD);
SPI_RECVBLOCK(dev->spi, buff, n);
pn532_deselect(dev);
pn532_unlock(dev->spi);
tracerx("read", buff, n);
return n;
}
static
BYTE send_cmd (
BYTE cmd, /* 1st byte (Start + Index) */
DWORD arg /* Argument (32 bits) */
)
{
BYTE n, res;
if (cmd & 0x80) { /* ACMD<n> is the command sequense of CMD55-CMD<n> */
cmd &= 0x7F;
res = send_cmd(CMD55, 0);
if (res > 1) return res;
}
/* Select the card */
DESELECT();
SPI_RECEIVE();
SELECT();
SPI_RECEIVE();
/* Send a command packet */
SPI_SEND((BYTE)cmd); /* Start + Command index */
SPI_SEND((BYTE)(arg >> 24)); /* Argument[31..24] */
SPI_SEND((BYTE)(arg >> 16)); /* Argument[23..16] */
SPI_SEND((BYTE)(arg >> 8)); /* Argument[15..8] */
SPI_SEND((BYTE)arg); /* Argument[7..0] */
n = 0x01; /* Dummy CRC + Stop */
if (cmd == CMD0) n = 0x95; /* Valid CRC for CMD0(0) */
if (cmd == CMD8) n = 0x87; /* Valid CRC for CMD8(0x1AA) */
SPI_SEND(n);
/* Receive a command response */
n = 10; /* Wait for a valid response in timeout of 10 attempts */
do {
res = SPI_RECEIVE();
} while ((res & 0x80) && --n);
return res; /* Return with the response value */
}
/** Strobes command and returns chip status byte
*
* By default commands are send as Write. To a command,
* CC1101_READ_SINGLE may be OR'ed to obtain the number of RX bytes
* pending in RX FIFO.
*/
inline uint8_t cc1101_strobe(struct cc1101_dev_s * dev, uint8_t command)
{
uint8_t status;
cc1101_access_begin(dev);
SPI_SETFREQUENCY(dev->spi, CC1101_SPIFREQ_SINGLE);
status = SPI_SEND(dev->spi, command);
cc1101_access_end(dev);
return status;
}
static void pga11x_send16(FAR struct spi_dev_s *spi, uint16_t word)
{
spivdbg("Send %04x\n", word);
/* The logical interface is 16-bits wide. However, this driver uses a
* 8-bit configuration for greaer portability.
*
* Send the MS byte first. Then the LS byte.
*/
SPI_SEND(spi, word >> 8);
SPI_SEND(spi, word & 0xff);
}
static void ramtron_writeenable(struct ramtron_dev_s *priv)
{
/* Select this FLASH part */
SPI_SELECT(priv->dev, SPIDEV_FLASH, true);
/* Send "Write Enable (WREN)" command */
(void)SPI_SEND(priv->dev, RAMTRON_WREN);
/* Deselect the FLASH */
SPI_SELECT(priv->dev, SPIDEV_FLASH, false);
fvdbg("Enabled\n");
}
void ad7714_on_spi_it( void ) {
uint8_t spi_read = SPDR;
if (msg == &ad7714_read) {
if (idx==1)
ad7714_sample = spi_read<<8;
else if (idx==2) {
ad7714_sample += spi_read;
ad7714_sample_read = TRUE;
}
}
idx++;
if (idx < msg->len) {
SPI_SEND(msg->data[idx]);
}
else {
SPI_UNSELECT_SLAVE1();
SPI_STOP();
}
}
static void pn532_writecommand(struct pn532_dev_s *dev, uint8_t cmd)
{
char cmd_buffer[16];
struct pn532_frame *f = (struct pn532_frame *) cmd_buffer;
pn532_frame_init(f, cmd);
pn532_frame_finish(f);
pn532_lock(dev->spi);
pn532_select(dev);
nxsig_usleep(10000);
SPI_SEND(dev->spi, PN532_SPI_DATAWRITE);
SPI_SNDBLOCK(dev->spi, f, FRAME_SIZE(f));
pn532_deselect(dev);
pn532_unlock(dev->spi);
tracetx("command sent", (uint8_t *) f, FRAME_SIZE(f));
}
int max11802_register(FAR struct spi_dev_s *spi,
FAR struct max11802_config_s *config, int minor)
{
FAR struct max11802_dev_s *priv;
char devname[DEV_NAMELEN];
#ifdef CONFIG_MAX11802_MULTIPLE
irqstate_t flags;
#endif
int ret;
iinfo("spi: %p minor: %d\n", spi, minor);
/* Debug-only sanity checks */
DEBUGASSERT(spi != NULL && config != NULL && minor >= 0 && minor < 100);
/* Create and initialize a MAX11802 device driver instance */
#ifndef CONFIG_MAX11802_MULTIPLE
priv = &g_max11802;
#else
priv = (FAR struct max11802_dev_s *)kmm_malloc(sizeof(struct max11802_dev_s));
if (!priv)
{
ierr("ERROR: kmm_malloc(%d) failed\n", sizeof(struct max11802_dev_s));
return -ENOMEM;
}
#endif
/* Initialize the MAX11802 device driver instance */
memset(priv, 0, sizeof(struct max11802_dev_s));
priv->spi = spi; /* Save the SPI device handle */
priv->config = config; /* Save the board configuration */
priv->wdog = wd_create(); /* Create a watchdog timer */
priv->threshx = INVALID_THRESHOLD; /* Initialize thresholding logic */
priv->threshy = INVALID_THRESHOLD; /* Initialize thresholding logic */
/* Initialize semaphores */
sem_init(&priv->devsem, 0, 1); /* Initialize device structure semaphore */
sem_init(&priv->waitsem, 0, 0); /* Initialize pen event wait semaphore */
/* The pen event semaphore is used for signaling and, hence, should not
* have priority inheritance enabled.
*/
sem_setprotocol(&priv->waitsem, SEM_PRIO_NONE);
/* Make sure that interrupts are disabled */
config->clear(config);
config->enable(config, false);
/* Attach the interrupt handler */
ret = config->attach(config, max11802_interrupt);
if (ret < 0)
{
ierr("ERROR: Failed to attach interrupt\n");
goto errout_with_priv;
}
iinfo("Mode: %d Bits: 8 Frequency: %d\n",
CONFIG_MAX11802_SPIMODE, CONFIG_MAX11802_FREQUENCY);
/* Lock the SPI bus so that we have exclusive access */
max11802_lock(spi);
/* Configure MAX11802 registers */
SPI_SELECT(priv->spi, SPIDEV_TOUCHSCREEN, true);
(void)SPI_SEND(priv->spi, MAX11802_CMD_MODE_WR);
(void)SPI_SEND(priv->spi, MAX11802_MODE);
SPI_SELECT(priv->spi, SPIDEV_TOUCHSCREEN, false);
SPI_SELECT(priv->spi, SPIDEV_TOUCHSCREEN, true);
(void)SPI_SEND(priv->spi, MAX11802_CMD_AVG_WR);
(void)SPI_SEND(priv->spi, MAX11802_AVG);
SPI_SELECT(priv->spi, SPIDEV_TOUCHSCREEN, false);
SPI_SELECT(priv->spi, SPIDEV_TOUCHSCREEN, true);
(void)SPI_SEND(priv->spi, MAX11802_CMD_TIMING_WR);
(void)SPI_SEND(priv->spi, MAX11802_TIMING);
SPI_SELECT(priv->spi, SPIDEV_TOUCHSCREEN, false);
SPI_SELECT(priv->spi, SPIDEV_TOUCHSCREEN, true);
(void)SPI_SEND(priv->spi, MAX11802_CMD_DELAY_WR);
(void)SPI_SEND(priv->spi, MAX11802_DELAY);
SPI_SELECT(priv->spi, SPIDEV_TOUCHSCREEN, false);
/* Test that the device access was successful. */
SPI_SELECT(priv->spi, SPIDEV_TOUCHSCREEN, true);
(void)SPI_SEND(priv->spi, MAX11802_CMD_MODE_RD);
ret = SPI_SEND(priv->spi, 0);
SPI_SELECT(priv->spi, SPIDEV_TOUCHSCREEN, false);
/* Unlock the bus */
max11802_unlock(spi);
if (ret != MAX11802_MODE)
{
ierr("ERROR: max11802 mode readback failed: %02x\n", ret);
goto errout_with_priv;
}
/* Register the device as an input device */
(void)snprintf(devname, DEV_NAMELEN, DEV_FORMAT, minor);
iinfo("Registering %s\n", devname);
ret = register_driver(devname, &max11802_fops, 0666, priv);
if (ret < 0)
{
ierr("ERROR: register_driver() failed: %d\n", ret);
goto errout_with_priv;
}
/* If multiple MAX11802 devices are supported, then we will need to add
* this new instance to a list of device instances so that it can be
* found by the interrupt handler based on the recieved IRQ number.
*/
#ifdef CONFIG_MAX11802_MULTIPLE
flags = enter_critical_section();
priv->flink = g_max11802list;
g_max11802list = priv;
leave_critical_section(flags);
#endif
/* Schedule work to perform the initial sampling and to set the data
* availability conditions.
*/
ret = work_queue(HPWORK, &priv->work, max11802_worker, priv, 0);
if (ret != 0)
{
ierr("ERROR: Failed to queue work: %d\n", ret);
goto errout_with_priv;
}
/* And return success (?) */
return OK;
errout_with_priv:
sem_destroy(&priv->devsem);
#ifdef CONFIG_MAX11802_MULTIPLE
kmm_free(priv);
#endif
return ret;
}
