/**
* \brief Write to the FRAM chip.
* \param address The index of the byte to start writing to.
* \param len The number of bytes to write.
* \param buf A buffer of values to write.
* \return 0 on success, -1 on error
*
* Writes len bytes to the FRAM chip starting at address.
*/
int
fm25v02_write(uint16_t address, uint16_t len, uint8_t *buf)
{
uint16_t i;
spi_set_mode(SSI_CR0_FRF_MOTOROLA, SSI_CR0_SPO, SSI_CR0_SPH, 8);
SPI_CS_CLR(FM25V02_CS_N_PORT_NUM, FM25V02_CS_N_PIN);
/* Send the WRITE ENABLE command to allow writing to the FRAM */
SPI_WRITE(FM25V02_WRITE_ENABLE_COMMAND);
SPI_CS_SET(FM25V02_CS_N_PORT_NUM, FM25V02_CS_N_PIN);
SPI_CS_CLR(FM25V02_CS_N_PORT_NUM, FM25V02_CS_N_PIN);
/* Send the WRITE command and the address to the FRAM */
SPI_WRITE(FM25V02_WRITE_COMMAND);
address &= 0x7fff;
SPI_WRITE((address&0xff00)>>8);
SPI_WRITE((address&0xff));
/* Send the data to write */
for(i=0; i<len; i++) {
SPI_WRITE(buf[i]);
}
SPI_CS_SET(FM25V02_CS_N_PORT_NUM, FM25V02_CS_N_PIN);
return 0;
}
/**
* \brief Write to the FRAM chip.
* \param address The index of the byte to start writing to.
* \param len The number of bytes to write.
* \param buf A buffer of values to write.
* \return 0 on success, -1 on error
*
* Writes len bytes to the FRAM chip starting at address.
*/
int
fm25lb_write(uint16_t address, uint16_t len, uint8_t *buf)
{
uint16_t i;
spi_set_mode(SSI_CR0_FRF_MOTOROLA, SSI_CR0_SPO, SSI_CR0_SPH, 8);
SPI_CS_CLR(FM25LB_CS_N_PORT_NUM, FM25LB_CS_N_PIN);
/* Send the WRITE ENABLE command to allow writing to the FRAM */
SPI_WRITE(FM25LB_WRITE_ENABLE_COMMAND);
SPI_CS_SET(FM25LB_CS_N_PORT_NUM, FM25LB_CS_N_PIN);
SPI_CS_CLR(FM25LB_CS_N_PORT_NUM, FM25LB_CS_N_PIN);
/* Send the WRITE command and the address to the FRAM */
SPI_WRITE(FM25LB_ADD_ADDRESS_BIT(address, FM25LB_WRITE_COMMAND));
SPI_WRITE(address & 0xFF);
/* Send the data to write */
for(i=0; i<len; i++) {
SPI_WRITE(buf[i]);
}
SPI_CS_SET(FM25LB_CS_N_PORT_NUM, FM25LB_CS_N_PIN);
return 0;
}
static int
ar71xx_spi_detach(device_t dev)
{
struct ar71xx_spi_softc *sc = device_get_softc(dev);
/*
* Ensure any other writes to the device are finished
* before we tear down the SPI device.
*/
SPI_BARRIER_WRITE(sc);
/*
* Restore the control register; ensure it has hit the
* hardware before continuing.
*/
SPI_WRITE(sc, AR71XX_SPI_CTRL, sc->sc_reg_ctrl);
SPI_BARRIER_WRITE(sc);
/*
* And now, put the flash back into mapped IO mode and
* ensure _that_ has completed before we finish up.
*/
SPI_WRITE(sc, AR71XX_SPI_FS, 0);
SPI_BARRIER_WRITE(sc);
if (sc->sc_mem_res)
bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
return (0);
}
/**
* \brief Read from the FRAM chip.
* \param address The index of the byte to start reading from.
* \param len The number of bytes to read.
* \param buf A buffer to put the return data in.
* \return 0 on success, -1 on error
*
* Reads len bytes from the FRAM chip starting at address.
*/
int
fm25v02_read(uint16_t address, uint16_t len, uint8_t *buf)
{
uint16_t i;
spi_set_mode(SSI_CR0_FRF_MOTOROLA, SSI_CR0_SPO, SSI_CR0_SPH, 8);
SPI_CS_CLR(FM25V02_CS_N_PORT_NUM, FM25V02_CS_N_PIN);
/* Send the READ command and the address to the FRAM */
SPI_WRITE(FM25V02_READ_COMMAND);
address &= 0x7fff;
SPI_WRITE((address&0xff00)>>8);
SPI_WRITE((address&0xff));
SPI_FLUSH();
for (i=0; i<len; i++) {
SPI_READ(buf[i]);
}
SPI_CS_SET(FM25V02_CS_N_PORT_NUM, FM25V02_CS_N_PIN);
return 0;
}
/**
* @brief Reads current value from a transceiver register
*
* This function reads the current value from a transceiver register.
*
* @param addr Specifies the address of the trx register from which
* the data shall be read
*
* @return Value of the register read
*/
uint8_t pal_trx_reg_read(uint8_t addr)
{
uint8_t register_value;
ENTER_CRITICAL_REGION();
/* Prepare the command byte */
addr |= READ_ACCESS_COMMAND;
/* Start SPI transaction by pulling SEL low */
SS_LOW();
/* Send the write command byte */
SPI_WRITE(addr);
/*
* Done to clear the RDRF bit in the SPI status register, which will be set
* as a result of reception of some data from the transceiver as a result
* of SPI write operation done above.
*/
SPI_READ(register_value);
/* Do dummy write for initiating SPI read */
SPI_WRITE(SPI_DUMMY_VALUE);
/* Read the byte received */
SPI_READ(register_value);
/* Stop the SPI transaction by setting SEL high */
SS_HIGH();
LEAVE_CRITICAL_REGION();
return register_value;
}
int
rv3049_set_time(rv3049_time_t* time)
{
uint8_t buf[8];
int i;
buf[0] = rv3049_binary_to_bcd(time->seconds);
buf[1] = rv3049_binary_to_bcd(time->minutes);
buf[2] = rv3049_binary_to_bcd(time->hours); // 24 hour mode
buf[3] = rv3049_binary_to_bcd(time->days);
buf[4] = time->weekday;
buf[5] = time->month;
buf[6] = rv3049_binary_to_bcd(time->year - 2000);
spix_set_mode(SPI_CONF_DEFAULT_INSTANCE, SSI_CR0_FRF_MOTOROLA, 0, SSI_CR0_SPH, 8);
SPI_CS_SET(RV3049_CS_PORT_NUM, RV3049_CS_PIN);
// Signal a write to the clock
SPI_WRITE(RV3049_SET_WRITE_BIT(RV3049_PAGE_ADDR_CLOCK));
// Write the clock values
for (i=0; i<RV3049_WRITE_LEN_TIME; i++) {
SPI_WRITE(buf[i]);
}
SPI_CS_CLR(RV3049_CS_PORT_NUM, RV3049_CS_PIN);
return 0;
}
/**
* \brief Read from the FRAM chip.
* \param address The index of the byte to start reading from.
* \param len The number of bytes to read.
* \param buf A buffer to put the return data in.
* \return 0 on success, -1 on error
*
* Reads len bytes from the FRAM chip starting at address.
*/
int
fm25lb_read(uint16_t address, uint16_t len, uint8_t *buf)
{
uint16_t i;
// uint16_t c;
// uint16_t cycles = (len / 6) + 1;
// uint16_t index = 0;
uint16_t current_address = address;
spi_set_mode(SSI_CR0_FRF_MOTOROLA, SSI_CR0_SPO, SSI_CR0_SPH, 8);
SPI_CS_CLR(FM25LB_CS_N_PORT_NUM, FM25LB_CS_N_PIN);
/* Send the READ command and the address to the FRAM */
SPI_WRITE(FM25LB_ADD_ADDRESS_BIT(current_address, FM25LB_READ_COMMAND));
SPI_WRITE(current_address & 0xFF);
SPI_FLUSH();
for (i=0; i<len; i++) {
SPI_READ(buf[i]);
}
SPI_CS_SET(FM25LB_CS_N_PORT_NUM, FM25LB_CS_N_PIN);
return 0;
}
static uint8_t
ar71xx_spi_txrx(struct ar71xx_spi_softc *sc, int cs, uint8_t data)
{
int bit;
/* CS0 */
uint32_t ioctrl = SPI_IO_CTRL_CSMASK;
/*
* low-level for selected CS
*/
ioctrl &= ~(SPI_IO_CTRL_CS0 << cs);
uint32_t iod, rds;
for (bit = 7; bit >=0; bit--) {
if (data & (1 << bit))
iod = ioctrl | SPI_IO_CTRL_DO;
else
iod = ioctrl & ~SPI_IO_CTRL_DO;
SPI_BARRIER_WRITE(sc);
SPI_WRITE(sc, AR71XX_SPI_IO_CTRL, iod);
SPI_BARRIER_WRITE(sc);
SPI_WRITE(sc, AR71XX_SPI_IO_CTRL, iod | SPI_IO_CTRL_CLK);
}
/*
* Provide falling edge for connected device by clear clock bit.
*/
SPI_BARRIER_WRITE(sc);
SPI_WRITE(sc, AR71XX_SPI_IO_CTRL, iod);
SPI_BARRIER_WRITE(sc);
rds = SPI_READ(sc, AR71XX_SPI_RDS);
return (rds & 0xff);
}
/**
* @brief Writes and reads data into/from SRAM of the transceiver
*
* This function writes data into the SRAM of the transceiver and
* simultaneously reads the bytes.
*
* @param addr Start address in the SRAM for the write operation
* @param idata Pointer to the data written/read into/from SRAM
* @param length Number of bytes written/read into/from SRAM
*/
void pal_trx_aes_wrrd(uint8_t addr, uint8_t *idata, uint8_t length)
{
uint8_t dummy_rx_data;
uint8_t *odata;
PAL_WAIT_500_NS();
ENTER_CRITICAL_REGION();
/* Start SPI transaction by pulling SEL low */
SS_LOW();
/* Send the command byte */
SPI_WRITE(TRX_CMD_SW);
/*
* Done to clear the RDRF bit in the SPI status register, which will be set
* as a result of reception of some data from the transceiver as a result
* of SPI write operation done above.
*/
SPI_READ(dummy_rx_data);
/* Write SRAM start address, clear the RDRF bit */
SPI_WRITE(addr);
SPI_READ(dummy_rx_data);
/* Now transfer data */
odata = idata;
/* Write data byte 0 - the obtained value in SPDR is meaningless */
SPI_WRITE(*idata++);
SPI_READ(dummy_rx_data);
/*
* Done to avoid compiler warning about variable being not used after
* setting.
*/
dummy_rx_data = dummy_rx_data;
/* Process data bytes 1...length-1: write and read */
do
{
SPI_WRITE(*idata++);
/* Upload the received byte in the user provided location */
SPI_READ(*odata++);
}
while (--length > 0);
/* To get the last data byte, write some dummy byte */
SPI_WRITE(SPI_DUMMY_VALUE);
SPI_READ(*odata);
/* Stop the SPI transaction by setting SEL high */
SS_HIGH();
LEAVE_CRITICAL_REGION();
}
void mmc_close_block(void){
SPI_READ(0xFF); // CRC bytes that are not needed
SPI_READ(0xFF);
MMCSS=1; // set MMCSS = 1 (off)
SPI_WRITE(0xFF); // give mmc the clocks it needs to finish off
SPI_WRITE(0xff);
}
/**
* @brief Reads frame buffer of the transceiver
*
* This function reads the frame buffer of the transceiver.
*
* @param[out] data Pointer to the location to store frame
* @param[in] length Number of bytes to be read from the frame buffer.
*/
void pal_trx_frame_read(uint8_t *data, uint8_t length)
{
uint8_t dummy_rx_data;
ENTER_CRITICAL_REGION();
/* Start SPI transaction by pulling SEL low */
SS_LOW();
/* Send the command byte */
SPI_WRITE(TRX_CMD_FR);
/*
* Done to clear the RDRF bit in the SPI status register, which will be set
* as a result of reception of some data from the transceiver as a result
* of SPI write operation done above.
*/
SPI_READ(dummy_rx_data);
/*
* Done to avoid compiler warning about variable being not used after
* setting.
*/
dummy_rx_data = dummy_rx_data;
#ifdef NODMA_SPI
do
{
/* Do dummy write for initiating SPI read */
SPI_WRITE(SPI_DUMMY_VALUE);
/* Upload the received byte in the user provided location */
SPI_READ(*data);
data++;
}
while (--length > 0);
#else
/* Disable both read and write. */
SPI_USED->SPI_PTCR = SPI_PTCR_RXTDIS | SPI_PTCR_TXTDIS;
memset(data, 0xFF, length);
SPI_USED->SPI_RPR = SPI_USED->SPI_TPR = (uint32_t)data;
SPI_USED->SPI_RCR = SPI_USED->SPI_TCR = length;
/* Enable read and write. */
SPI_USED->SPI_PTCR = SPI_PTCR_RXTEN | SPI_PTCR_TXTEN;
/* Wait for end of read */
while (SPI_USED->SPI_RCR);
#endif
SS_HIGH();
LEAVE_CRITICAL_REGION();
}
static void mist_memory_write(char *data, unsigned long words) {
EnableFpga();
SPI(MIST_WRITE_MEMORY);
while(words--) {
SPI_WRITE(*data++);
SPI_WRITE(*data++);
}
DisableFpga();
}
void mist_memory_set(char data, unsigned long words) {
EnableFpga();
SPI(MIST_WRITE_MEMORY);
while(words--) {
SPI_WRITE(data);
SPI_WRITE(data);
}
DisableFpga();
}
int fm25v02_writeStatus(uint8_t statusReg){
// Set WEL bit in status register
spi_set_mode(SSI_CR0_FRF_MOTOROLA, 0, 0, 8);
SPI_CS_CLR(FM25V02_CS_N_PORT_NUM, FM25V02_CS_N_PIN);
SPI_WRITE(FM25V02_WRITE_ENABLE_COMMAND);
SPI_CS_SET(FM25V02_CS_N_PORT_NUM, FM25V02_CS_N_PIN);
SPI_CS_CLR(FM25V02_CS_N_PORT_NUM, FM25V02_CS_N_PIN);
SPI_WRITE(FM25V02_WRITE_STATUS_COMMAND);
SPI_WRITE(statusReg);
SPI_CS_SET(FM25V02_CS_N_PORT_NUM, FM25V02_CS_N_PIN);
return 0;
}
static int
ar71xx_spi_detach(device_t dev)
{
struct ar71xx_spi_softc *sc = device_get_softc(dev);
SPI_WRITE(sc, AR71XX_SPI_CTRL, sc->sc_reg_ctrl);
SPI_WRITE(sc, AR71XX_SPI_FS, 0);
if (sc->sc_mem_res)
bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
return (0);
}
void defilement_led() {
int i;
for(i=0;i<NLED;i++) {
SPI_WRITE(vert);
RFLPC_DELAY(2000000);
}
}
static int
rt305x_spi_attach(device_t dev)
{
struct rt305x_spi_softc *sc = device_get_softc(dev);
int rid;
sc->sc_dev = dev;
rid = 0;
sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
RF_ACTIVE);
if (!sc->sc_mem_res) {
device_printf(dev, "Could not map memory\n");
return (ENXIO);
}
if (rt305x_spi_wait(sc)) {
bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
return (EBUSY);
}
SPI_WRITE(sc, RT305X_SPICFG, MSBFIRST | SPICLKPOL | TX_ON_CLK_FALL |
SPI_CLK_DIV8); /* XXX: make it configurable */
/*
* W25Q64CV max 104MHz, bus 120-192 MHz, so divide by 2.
* Update: divide by 4, DEV2 to fast for flash.
*/
device_add_child(dev, "spibus", 0);
return (bus_generic_attach(dev));
}
/*---------------------------------------------------------------------------*/
PROCESS_THREAD(ipv6_process, ev, data)
{
PROCESS_BEGIN();
printf("started!\n");
etimer_set(&periodic_timer, 1*CLOCK_SECOND);
while(1) {
PROCESS_YIELD();
if (etimer_expired(&periodic_timer)) {
if (!(spibyte & 0x01)) {
SPI_READ(spibuf[0]);
} else {
SPI_WRITE(spibuf[1]);
}
spibyte++;
etimer_restart(&periodic_timer);
}
}
PROCESS_END();
}
/**
* @brief Writes data into frame buffer of the transceiver
*
* This function writes data into the frame buffer of the transceiver
*
* @param[in] data Pointer to data to be written into frame buffer
* @param[in] length Number of bytes to be written into frame buffer
*/
void pal_trx_frame_write(uint8_t *data, uint8_t length)
{
uint8_t command_data = TRX_CMD_FW ;
ENTER_CRITICAL_REGION();
/* Start SPI transaction by pulling SEL low */
SS_LOW();
#ifdef NODMA_SPI
/* Send the command byte */
SPI_WRITE(command_data);
do
{
/* Upload the user data to transceiver data register */
SPI_WRITE(*data);
data++;
}
while (--length > 0);
#else
/* DMA transfer for SAM3S */
/* Disable both read and write. */
SPI_USED->SPI_PTCR = SPI_PTCR_TXTDIS;
/* Setup dma transfer including trx command byte */
SPI_USED->SPI_TPR = (uint32_t)&command_data;
SPI_USED->SPI_TCR = (uint16_t)1;
SPI_USED->SPI_TNPR = (uint32_t)data;
SPI_USED->SPI_TNCR = (uint16_t)length;
/* start transfer */
SPI_USED->SPI_PTCR = SPI_PTCR_TXTEN;
/* Wait while transfer isnt finished */
while (!(SPI_USED->SPI_SR & SPI_SR_TXEMPTY) ||
!(SPI_USED->SPI_SR & SPI_SR_TXBUFE));
SPI_USED->SPI_PTCR = SPI_PTCR_TXTDIS;
#endif
/* Wait for end of write; send counter should not matter. */
/* Stop the SPI transaction by setting SEL high. */
SS_HIGH();
LEAVE_CRITICAL_REGION();
}
static void
ar71xx_spi_chip_deactivate(struct ar71xx_spi_softc *sc, int cs)
{
/*
* Put all CSx to high
*/
SPI_WRITE(sc, AR71XX_SPI_IO_CTRL, SPI_IO_CTRL_CSMASK);
}
/**
* @brief Writes data into SRAM of the transceiver
*
* This function writes data into the SRAM of the transceiver
*
* @param addr Start address in the SRAM for the write operation
* @param data Pointer to the data to be written into SRAM
* @param length Number of bytes to be written into SRAM
*/
void pal_trx_sram_write(uint8_t addr, uint8_t *data, uint8_t length)
{
ENTER_CRITICAL_REGION();
/* Start SPI transaction by pulling SEL low */
SS_LOW();
/* Send the command byte */
SPI_WRITE(TRX_CMD_SW);
/* Send the address from which the write operation should start */
SPI_WRITE(addr);
#ifdef NODMA_SPI
do
{
/* Upload the user data to transceiver data register */
SPI_WRITE(*data);
data++;
}
while (--length > 0);
#else
/* DMA transfer for SAM3S */
/* Disable both read and write. */
SPI_USED->SPI_PTCR = SPI_PTCR_TXTDIS;
/* Setup dma transfer including trx command byte */
SPI_USED->SPI_TPR = (uint32_t)data;
SPI_USED->SPI_TCR = (uint16_t)length;
/* start transfer */
SPI_USED->SPI_PTCR = SPI_PTCR_TXTEN;
/* Wait while transfer isnt finished */
while (!(SPI_USED->SPI_SR & SPI_SR_TXEMPTY) ||
!(SPI_USED->SPI_SR & SPI_SR_TXBUFE));
SPI_USED->SPI_PTCR = SPI_PTCR_TXTDIS;
#endif
/* Stop the SPI transaction by setting SEL high */
SS_HIGH();
LEAVE_CRITICAL_REGION();
}
int mmc_get_status(){ // Get the status register of the MMC, for debugging
char ret=0;
char p;
xcs=1;
xdcs=1;
MMCSS=0; // set MMCSS = 0 (on)
SPI_WRITE(0x7a); // 0x58?
for(p=4;p>0;p--){
SPI_WRITE(0x00);
}
SPI_WRITE(0xFF); // checksum is no longer required but we always send 0xFF
if( mmc_response(0x00) == 0 &&
mmc_response(0xff) == 0) ret=1;
MMCSS=1; // set MMCSS = 1 (off)
SPI_WRITE(0xFF);
SPI_WRITE(0xFF);
return ret;
}
uint8_t fm25v02_readStatus(){
uint8_t statusReg;
spi_set_mode(SSI_CR0_FRF_MOTOROLA, 0, 0, 8);
SPI_CS_CLR(FM25V02_CS_N_PORT_NUM, FM25V02_CS_N_PIN);
SPI_WRITE(FM25V02_READ_STATUS_COMMAND);
SPI_FLUSH();
SPI_READ(statusReg);
SPI_CS_SET(FM25V02_CS_N_PORT_NUM, FM25V02_CS_N_PIN);
return statusReg;
}
static int
ar71xx_spi_attach(device_t dev)
{
struct ar71xx_spi_softc *sc = device_get_softc(dev);
int rid;
sc->sc_dev = dev;
rid = 0;
sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
RF_ACTIVE);
if (!sc->sc_mem_res) {
device_printf(dev, "Could not map memory\n");
return (ENXIO);
}
SPI_WRITE(sc, AR71XX_SPI_FS, 1);
/* Flush out read before reading the control register */
SPI_BARRIER_WRITE(sc);
sc->sc_reg_ctrl = SPI_READ(sc, AR71XX_SPI_CTRL);
/*
* XXX TODO: document what the SPI control register does.
*/
SPI_WRITE(sc, AR71XX_SPI_CTRL, 0x43);
/*
* Ensure the config register write has gone out before configuring
* the chip select mask.
*/
SPI_BARRIER_WRITE(sc);
SPI_WRITE(sc, AR71XX_SPI_IO_CTRL, SPI_IO_CTRL_CSMASK);
/*
* .. and ensure the write has gone out before continuing.
*/
SPI_BARRIER_WRITE(sc);
device_add_child(dev, "spibus", -1);
return (bus_generic_attach(dev));
}
/* ----------------------------------------------------------------------------
* Function : void EEPROM_Write_Init(uint32_t spi_interface,
* uint16_t address)
* ----------------------------------------------------------------------------
* Description : Ready the EEPROM for writing at a specified address. Chip
* select is left low.
* Inputs : - spi_interface - Index of SPI interface; use 0, 1
* - address - EEPROM address to write to
* Outputs : None
* Assumptions : EEPROM is write enabled
* ------------------------------------------------------------------------- */
void EEPROM_Write_Init(uint32_t spi_interface, uint16_t address)
{
/* Check if SPI interface exists. If interface is invalid, return. */
if(spi_interface > (EEPROM_SPI_NUM_INTERFACE - 1))
{
return;
}
/* Send write opcode */
SPI_WRITE(spi_interface, EEPROM_OPCODE_WRITE);
SPI_TRANSFERCONFIG(spi_interface, EEPROM_SPI_WRITE_BYTE);
while(SPI_IS_BUSY(spi_interface));
/* Send address to write to */
SPI_WRITE(spi_interface, address);
SPI_TRANSFERCONFIG(spi_interface, EEPROM_SPI_WRITE_SHORT);
while(SPI_IS_BUSY(spi_interface));
/* NOTE: Chip select is left low. */
}
void fm25v02_eraseAll(){
uint16_t i;
spi_set_mode(SSI_CR0_FRF_MOTOROLA, 0, 0, 8);
SPI_CS_CLR(FM25V02_CS_N_PORT_NUM, FM25V02_CS_N_PIN);
SPI_WRITE(FM25V02_WRITE_ENABLE_COMMAND);
SPI_CS_SET(FM25V02_CS_N_PORT_NUM, FM25V02_CS_N_PIN);
SPI_CS_CLR(FM25V02_CS_N_PORT_NUM, FM25V02_CS_N_PIN);
SPI_WRITE(FM25V02_WRITE_COMMAND);
// Address
SPI_WRITE(0x00);
SPI_WRITE(0x00);
/* Send the data to write */
for(i=0; i<0x7fff; i++) {
SPI_WRITE(0x00);
}
SPI_CS_SET(FM25V02_CS_N_PORT_NUM, FM25V02_CS_N_PIN);
}
static void
ar71xx_spi_chip_activate(struct ar71xx_spi_softc *sc, int cs)
{
uint32_t ioctrl = SPI_IO_CTRL_CSMASK;
/*
* Put respective CSx to low
*/
ioctrl &= ~(SPI_IO_CTRL_CS0 << cs);
SPI_WRITE(sc, AR71XX_SPI_IO_CTRL, ioctrl);
}
/**
* @brief Writes data into a transceiver register
*
* This function writes a value into transceiver register.
*
* @param addr Address of the trx register
* @param data Data to be written to trx register
*
*/
void pal_trx_reg_write(uint8_t addr, uint8_t data)
{
ENTER_CRITICAL_REGION();
/* Prepare the command byte */
addr |= WRITE_ACCESS_COMMAND;
/* Start SPI transaction by pulling SEL low */
SS_LOW();
/* Send the Read command byte */
SPI_WRITE(addr);
/* Write the byte in the transceiver data register */
SPI_WRITE(data);
/* Stop the SPI transaction by setting SEL high */
SS_HIGH();
LEAVE_CRITICAL_REGION();
}
/** \brief This function reads data from one of the radio transceiver's registers.
*
* \param address Register address to read from. See datasheet for register
* map.
*
* \see Look at the at86rf230_registermap.h file for register address definitions.
*
* \returns The actual value of the read register.
*/
inline uint8_t
spi_register_read(uint8_t address)
{
uint8_t register_value;
//SPI_READ_REG(address, register_value);
SPI_ENABLE();
SPI_WRITE(address);
register_value = (uint8_t)SPI_TRANSFER(0);
SPI_DISABLE();
return register_value;
}
/*---------------------------------------------------------------------------*/
static void
write_enable(void)
{
int s;
s = splhigh();
SPI_FLASH_ENABLE();
SPI_WRITE(SPI_FLASH_INS_WREN);
SPI_FLASH_DISABLE();
splx(s);
}
