void SpiFlash_ChipErase(void)
{
// /CS: active
SPI_SET_SS0_LOW(SPI_FLASH_PORT);
// send Command: 0x06, Write enable
SPI_WRITE_TX(SPI_FLASH_PORT, 0x06);
// wait tx finish
while(SPI_IS_BUSY(SPI_FLASH_PORT));
// /CS: de-active
SPI_SET_SS0_HIGH(SPI_FLASH_PORT);
//////////////////////////////////////////
// /CS: active
SPI_SET_SS0_LOW(SPI_FLASH_PORT);
// send Command: 0xC7, Chip Erase
SPI_WRITE_TX(SPI_FLASH_PORT, 0xC7);
// wait tx finish
while(SPI_IS_BUSY(SPI_FLASH_PORT));
// /CS: de-active
SPI_SET_SS0_HIGH(SPI_FLASH_PORT);
SPI_ClearRxFIFO(SPI0);
}
void SpiFlash_WriteStatusReg(uint8_t u8Value)
{
// /CS: active
SPI_SET_SS0_LOW(SPI_FLASH_PORT);
// send Command: 0x06, Write enable
SPI_WRITE_TX(SPI_FLASH_PORT, 0x06);
// wait tx finish
while(SPI_IS_BUSY(SPI_FLASH_PORT));
// /CS: de-active
SPI_SET_SS0_HIGH(SPI_FLASH_PORT);
///////////////////////////////////////
// /CS: active
SPI_SET_SS0_LOW(SPI_FLASH_PORT);
// send Command: 0x01, Write status register
SPI_WRITE_TX(SPI_FLASH_PORT, 0x01);
// write status
SPI_WRITE_TX(SPI_FLASH_PORT, u8Value);
// wait tx finish
while(SPI_IS_BUSY(SPI_FLASH_PORT));
// /CS: de-active
SPI_SET_SS0_HIGH(SPI_FLASH_PORT);
}
int32_t nReadCommandHandler(uint16_t* pCOM_Buff)
{
if (COMM_GET_DATA(pCOM_Buff[0]) < COMM_READ_MAX)
{
SPI_WRITE_TX(SPI, tMotor.unValue[COMM_GET_DATA(pCOM_Buff[0])]);
SPI_WRITE_TX(SPI, CRC16((uint8_t*)(&(tMotor.unValue[COMM_GET_DATA(pCOM_Buff[0])])), 1));
return 0;
}
else
{
return -1;
}
}
void SPI0_IRQHandler(void)
{
/* Check RX EMPTY flag */
while(SPI_GET_RX_FIFO_EMPTY_FLAG(SPI0) == 0)
{
/* Read RX FIFO */
g_au32DestinationData[g_u32RxDataCount++] = SPI_READ_RX(SPI0);
}
/* Check TX FULL flag and TX data count */
while((SPI_GET_TX_FIFO_FULL_FLAG(SPI0) == 0) && (g_u32TxDataCount < TEST_COUNT))
{
/* Write to TX FIFO */
SPI_WRITE_TX(SPI0, g_au32SourceData[g_u32TxDataCount++]);
}
if(g_u32TxDataCount >= TEST_COUNT)
SPI_DisableInt(SPI0, SPI_FIFO_TX_INT_MASK); /* Disable TX FIFO threshold interrupt */
/* Check the RX FIFO time-out interrupt flag */
if(SPI_GetIntFlag(SPI0, SPI_FIFO_TIMEOUT_INT_MASK))
{
/* If RX FIFO is not empty, read RX FIFO. */
while((SPI0->STATUS & SPI_STATUS_RX_EMPTY_Msk) == 0)
g_au32DestinationData[g_u32RxDataCount++] = SPI_READ_RX(SPI0);
}
}
uint8_t LCD_ReadReg(uint8_t u8Comm)
{
SPI_ClearRxFIFO(SPI_LCD_PORT);
ILI9341_DC = 0;
SPI_WRITE_TX(SPI_LCD_PORT, u8Comm);
SPI_WRITE_TX(SPI_LCD_PORT, 0x00);
// wait tx finish
while(SPI_IS_BUSY(SPI_LCD_PORT));
SPI_READ_RX(SPI_LCD_PORT);
return (SPI_READ_RX(SPI_LCD_PORT));
}
void LCD_WriteData(uint8_t u8Data)
{
ILI9341_DC = 1;
SPI_WRITE_TX(SPI_LCD_PORT, u8Data);
// wait tx finish
while(SPI_IS_BUSY(SPI_LCD_PORT));
}
void LCD_WriteCommand(uint8_t u8Comm)
{
ILI9341_DC = 0;
SPI_WRITE_TX(SPI_LCD_PORT, u8Comm);
// wait tx finish
while(SPI_IS_BUSY(SPI_LCD_PORT));
}
void SpiFlash_NormalPageProgram(uint32_t StartAddress, uint8_t *u8DataBuffer)
{
uint32_t i = 0;
// /CS: active
SPI_SET_SS0_LOW(SPI_FLASH_PORT);
// send Command: 0x06, Write enable
SPI_WRITE_TX(SPI_FLASH_PORT, 0x06);
// wait tx finish
while(SPI_IS_BUSY(SPI_FLASH_PORT));
// /CS: de-active
SPI_SET_SS0_HIGH(SPI_FLASH_PORT);
// /CS: active
SPI_SET_SS0_LOW(SPI_FLASH_PORT);
// send Command: 0x02, Page program
SPI_WRITE_TX(SPI_FLASH_PORT, 0x02);
// send 24-bit start address
SPI_WRITE_TX(SPI_FLASH_PORT, (StartAddress>>16) & 0xFF);
SPI_WRITE_TX(SPI_FLASH_PORT, (StartAddress>>8) & 0xFF);
SPI_WRITE_TX(SPI_FLASH_PORT, StartAddress & 0xFF);
// write data
while(1) {
if(!SPI_GET_TX_FIFO_FULL_FLAG(SPI_FLASH_PORT)) {
SPI_WRITE_TX(SPI_FLASH_PORT, u8DataBuffer[i++]);
if(i >= 255) break;
}
}
// wait tx finish
while(SPI_IS_BUSY(SPI_FLASH_PORT));
// /CS: de-active
SPI_SET_SS0_HIGH(SPI_FLASH_PORT);
SPI_ClearRxFIFO(SPI_FLASH_PORT);
}
void SpiFlash_DualFastRead(uint32_t StartAddress, uint8_t *u8DataBuffer)
{
uint32_t i;
// /CS: active
SPI_SET_SS0_LOW(SPI_FLASH_PORT);
// Command: 0x3B, Fast Read dual data
SPI_WRITE_TX(SPI_FLASH_PORT, 0x3B);
// send 24-bit start address
SPI_WRITE_TX(SPI_FLASH_PORT, (StartAddress>>16) & 0xFF);
SPI_WRITE_TX(SPI_FLASH_PORT, (StartAddress>>8) & 0xFF);
SPI_WRITE_TX(SPI_FLASH_PORT, StartAddress & 0xFF);
// dummy byte
SPI_WRITE_TX(SPI_FLASH_PORT, 0x00);
while(SPI_IS_BUSY(SPI_FLASH_PORT));
// clear RX buffer
SPI_ClearRxFIFO(SPI_FLASH_PORT);
// enable SPI dual IO mode and set direction to input
SPI_ENABLE_DUAL_MODE(SPI_FLASH_PORT);
SPI_ENABLE_DUAL_INPUT_MODE(SPI_FLASH_PORT);
// read data
for(i=0; i<256; i++) {
SPI_WRITE_TX(SPI_FLASH_PORT, 0x00);
while(SPI_IS_BUSY(SPI_FLASH_PORT));
u8DataBuffer[i] = SPI_READ_RX(SPI_FLASH_PORT);
}
// wait tx finish
while(SPI_IS_BUSY(SPI_FLASH_PORT));
// /CS: de-active
SPI_SET_SS0_HIGH(SPI_FLASH_PORT);
SPI_DISABLE_DUAL_MODE(SPI_FLASH_PORT);
}
void Display_SSD_Write(uint8_t isData, const uint8_t *buf, uint32_t len) {
int i;
// Set D/C#
DISPLAY_SSD_DC = isData ? 1 : 0;
for(i = 0; i < len; i++) {
// Send byte, wait until it is transmitted
SPI_WRITE_TX(SPI0, buf[i]);
while(SPI_IS_BUSY(SPI0));
}
}
uint16_t SpiFlash_ReadMidDid(void)
{
uint8_t u8RxData[6], u8IDCnt = 0;
// /CS: active
SPI_SET_SS0_LOW(SPI_FLASH_PORT);
// send Command: 0x90, Read Manufacturer/Device ID
SPI_WRITE_TX(SPI_FLASH_PORT, 0x90);
// send 24-bit '0', dummy
SPI_WRITE_TX(SPI_FLASH_PORT, 0x00);
SPI_WRITE_TX(SPI_FLASH_PORT, 0x00);
SPI_WRITE_TX(SPI_FLASH_PORT, 0x00);
// receive 16-bit
SPI_WRITE_TX(SPI_FLASH_PORT, 0x00);
SPI_WRITE_TX(SPI_FLASH_PORT, 0x00);
// wait tx finish
while(SPI_IS_BUSY(SPI_FLASH_PORT));
// /CS: de-active
SPI_SET_SS0_HIGH(SPI_FLASH_PORT);
while(!SPI_GET_RX_FIFO_EMPTY_FLAG(SPI_FLASH_PORT))
u8RxData[u8IDCnt ++] = SPI_READ_RX(SPI_FLASH_PORT);
return ( (u8RxData[4]<<8) | u8RxData[5] );
}
uint8_t SpiFlash_ReadStatusReg(void)
{
// /CS: active
SPI_SET_SS0_LOW(SPI_FLASH_PORT);
// send Command: 0x05, Read status register
SPI_WRITE_TX(SPI_FLASH_PORT, 0x05);
// read status
SPI_WRITE_TX(SPI_FLASH_PORT, 0x00);
// wait tx finish
while(SPI_IS_BUSY(SPI_FLASH_PORT));
// /CS: de-active
SPI_SET_SS0_HIGH(SPI_FLASH_PORT);
// skip first rx data
SPI_READ_RX(SPI_FLASH_PORT);
return (SPI_READ_RX(SPI_FLASH_PORT) & 0xff);
}
/* ------------- */
int main(void)
{
volatile uint32_t u32TxDataCount, u32RxDataCount;
/* Unlock protected registers */
SYS_UnlockReg();
/* Init System, IP clock and multi-function I/O. */
SYS_Init();
/* Lock protected registers */
SYS_LockReg();
/* Init UART0 for printf */
UART0_Init();
/* Init SPI */
SPI_Init();
printf("\n\n");
printf("+-----------------------------------------------------+\n");
printf("| SPI Slave Mode Sample Code |\n");
printf("+-----------------------------------------------------+\n");
printf("\n");
printf("Configure SPI0 as a slave.\n");
printf("Bit length of a transaction: 32\n");
printf("The I/O connection for SPI0:\n");
printf(" SPI0_SS (PB.4)\n SPI0_CLK (PB.2)\n");
printf(" SPI0_MISO0 (PB.3)\n SPI0_MOSI0 (PB.5)\n\n");
printf("SPI controller will transfer %d data to a off-chip master device.\n", TEST_COUNT);
printf("In the meanwhile the SPI controller will receive %d data from the off-chip master device.\n", TEST_COUNT);
printf("After the transfer is done, the %d received data will be printed out.\n", TEST_COUNT);
for(u32TxDataCount = 0; u32TxDataCount < TEST_COUNT; u32TxDataCount++)
{
/* Write the initial value to source buffer */
g_au32SourceData[u32TxDataCount] = 0x00AA0000 + u32TxDataCount;
/* Clear destination buffer */
g_au32DestinationData[u32TxDataCount] = 0;
}
u32TxDataCount = 0;
u32RxDataCount = 0;
printf("Press any key if the master device configuration is ready.");
getchar();
printf("\n");
/* Access TX and RX FIFO */
while(u32RxDataCount < TEST_COUNT)
{
/* Check TX FULL flag and TX data count */
if((SPI_GET_TX_FIFO_FULL_FLAG(SPI0) == 0) && (u32TxDataCount < TEST_COUNT))
SPI_WRITE_TX(SPI0, g_au32SourceData[u32TxDataCount++]); /* Write to TX FIFO */
/* Check RX EMPTY flag */
if(SPI_GET_RX_FIFO_EMPTY_FLAG(SPI0) == 0)
g_au32DestinationData[u32RxDataCount++] = SPI_READ_RX(SPI0); /* Read RX FIFO */
}
/* Print the received data */
printf("Received data:\n");
for(u32RxDataCount = 0; u32RxDataCount < TEST_COUNT; u32RxDataCount++)
{
printf("%d:\t0x%X\n", u32RxDataCount, g_au32DestinationData[u32RxDataCount]);
}
printf("The data transfer was done.\n");
printf("\n\nExit SPI driver sample code.\n");
/* Disable SPI0 peripheral clock */
CLK->APBCLK0 &= (~CLK_APBCLK0_SPI0CKEN_Msk);
while(1);
}
int main(void)
{
uint32_t u32DataCount, u32TestCount, u32Err;
/* Init System, IP clock and multi-function I/O */
SYS_Init();
/* Init UART to 115200-8n1 for print message */
UART_Open(UART0, 115200);
/* Configure SPI0 as a master, MSB first, 32-bit transaction, SPI Mode-0 timing, clock is 2MHz */
SPI_Open(SPI0, SPI_MASTER, SPI_MODE_0, 32, 2000000);
/* Enable the automatic hardware slave select function. Select the SPI0_SS0 pin and configure as low-active. */
SPI_EnableAutoSS(SPI0, SPI_SS0, SPI_SS_ACTIVE_LOW);
/* Configure SPI1 as a slave, MSB first, 32-bit transaction, SPI Mode-0 timing, clock is 4Mhz */
SPI_Open(SPI1, SPI_SLAVE, SPI_MODE_0, 32, 4000000);
/* Configure SPI1 as a low level active device. */
SPI_SET_SS0_LOW(SPI1);
printf("\n\n");
printf("+----------------------------------------------------------------------+\n");
printf("| SPI Driver Sample Code |\n");
printf("+----------------------------------------------------------------------+\n");
printf("\n");
printf("Configure SPI0 as a master and SPI1 as a slave.\n");
printf("Data width of a transaction: 32\n");
printf("SPI clock rate: %d Hz\n", SPI_GetBusClock(SPI0));
printf("The I/O connection for SPI0/SPI1 loopback:\n");
printf(" SPI0_SS (PE.4) <--> SPI1_SS(PC.12)\n SPI0_CLK(PE.5) <--> SPI1_CLK(PD.1)\n");
printf(" SPI0_MISO(PE.2) <--> SPI1_MISO(PD.0)\n SPI0_MOSI(PE.3) <--> SPI1_MOSI(PC.15)\n\n");
printf("Please connect SPI0 with SPI1, and press any key to start transmission ...");
getchar();
printf("\n");
printf("\nSPI0/1 Loopback test ");
/* Enable the SPI1 unit transfer interrupt. */
SPI_EnableInt(SPI1, SPI_UNITIEN_MASK);
NVIC_EnableIRQ(SPI1_IRQn);
SPI_TRIGGER(SPI1);
u32Err = 0;
for(u32TestCount=0; u32TestCount<10000; u32TestCount++) {
/* set the source data and clear the destination buffer */
for(u32DataCount=0; u32DataCount<TEST_COUNT; u32DataCount++) {
g_au32SourceData[u32DataCount] = u32DataCount;
g_au32DestinationData[u32DataCount] = 0;
}
u32DataCount=0;
SPI1_INT_Flag = 0;
if((u32TestCount&0x1FF) == 0) {
putchar('.');
}
SPI_TRIGGER(SPI0);
/* write the first data of source buffer to Tx register of SPI0. And start transmission. */
SPI_WRITE_TX(SPI0, g_au32SourceData[0]);
while(1) {
if(SPI1_INT_Flag==1) {
SPI1_INT_Flag = 0;
if(u32DataCount<(TEST_COUNT-1)) {
/* Read the previous retrieved data and trigger next transfer. */
g_au32DestinationData[u32DataCount] = SPI_READ_RX(SPI1);
u32DataCount++;
/* Write data to SPI0 Tx buffer and trigger the transfer */
SPI_WRITE_TX(SPI0, g_au32SourceData[u32DataCount]);
} else {
/* Just read the previous retrieved data but trigger next transfer, because this is the last transfer. */
g_au32DestinationData[u32DataCount] = SPI_READ_RX(SPI1);
break;
}
}
}
/* Check the received data */
for(u32DataCount=0; u32DataCount<TEST_COUNT; u32DataCount++) {
if(g_au32DestinationData[u32DataCount]!=g_au32SourceData[u32DataCount])
u32Err = 1;
}
if(u32Err)
break;
}
/* Disable the SPI1 unit transfer interrupt. */
SPI_DisableInt(SPI1, SPI_UNITIEN_MASK);
NVIC_DisableIRQ(SPI1_IRQn);
if(u32Err)
printf(" [FAIL]\n\n");
else
printf(" [PASS]\n\n");
printf("\n\nExit SPI driver sample code.\n");
while(1);
}
