/*
** @ close device
**/
int VS1003_close() {
VS_HW_RESET();
SPI_close(GPIOR_VS1003_CMDCH);
SPI_close(GPIOR_VS1003_DATCH);
VS_PLAT_DEINIT();
return 0;
}
/*******************************************************************************
* @fn bspSpiClose
*
* @brief Close the RTOS SPI driver
*
* @return none
*/
void bspSpiClose(void)
{
nUsers--;
if (nUsers > 0)
{
// Don't close the driver if still in use
return;
}
if (spiHandle != NULL)
{
// Close the RTOS driver
SPI_close(spiHandle);
spiHandle = NULL;
}
if (hSpiPin == NULL)
{
// Configure SPI lines as IO and set them according to BoardSpiInitTable
hSpiPin = PIN_open(&pinState, BoardSpiInitTable);
}
nUsers = 0;
}
static int spi_svc_close(const USB_Setup_TypeDef *setup)
{
int res = USB_STATUS_OK;
SPI_close();
return res;
}
static void
SPI_dealloc(SPI *self)
{
PyObject *ref = SPI_close(self);
Py_XDECREF(ref);
self->ob_type->tp_free((PyObject *)self);
}
int SPI_FLASH_close_force(spi_flash_dev *sfd) {
SPI_close(sfd->dev.bus);
SPI_DEV_close(&sfd->dev);
sfd->state = SPI_FLASH_STATE_CLOSED;
spi_flash_finalize(sfd, SPI_OK);
TASK_stop_timer(&sfd->timer);
TASK_free(sfd->task);
return SPI_OK;
}
/*
* ======== spi_Close ========
* SimpleLink Host Driver API to close a SPI communication interface.
*/
int spi_Close(Fd_t fd)
{
WiFiCC3100_Object *object = wifiHandle->object;
SPI_close(object->spiHandle);
object->spiState = WiFiCC3100_SPI_UNINITIALIZED;
Log_print1(Diags_USER1, "WiFi SPI (%p) closed\n", (Fd_t) object->spiHandle);
return (0);
}
static PyObject *SPIDev_close(SPIDev *self, PyObject *args, PyObject *kwds) {
int i;
for (i=0; i<SPIDev_MAX_CS_PER_BUS; i++) {
if (self->spidev_fd[i] > 0) {
SPI_close(self->spidev_fd[i]);
self->spidev_fd[i] = -1;
}
}
Py_INCREF(Py_None);
return Py_None;
}
/**************************************************************************//**
* @brief Sets/resets the ChipSelect of the SPI
*
* @param[in] value if true CS will be set, and reseted otherwise
*****************************************************************************/
void SPI_SetChipSelect(bool value)
{
if (value)
{
SPI_setup();
/* Enable chip select */
ClrOutput(SDF_CS);
}
else
{
SPI_close();
/* Disable chip select */
SetOutput(SDF_CS);
}
}
// -----------------------------------------------------------------------------
//! \brief This routine closes Transport Layer port
//!
//! \return void
// -----------------------------------------------------------------------------
void NPITLSPI_closeTransport(void)
{
SPI_close(spiHandle);
}
void SPI_begin(u8 module)
{
// Reset the module
SPI_close(module);
// Configure the module
switch(module)
{
case SPISW:
break;
#if !defined(__32MX440F256H__)
case SPI1:
// IO's
#if defined(PINGUINO32MX220) || defined(PINGUINO32MX250) || defined(PINGUINO32MX270)
TRISBCLR = 1<<14; // SCK1 is on RB14 ( D1 )
//TRISBCLR = 1<<7; // SS1 is on RB7 ( D5 )
TRISBSET = 1<<5; // SDI1 is on RB5 ( D6 )
TRISACLR = 1<<4; // SDO1 is on RA4 ( D7 )
#endif
// 4. Clear the ENHBUF bit (SPIxCON<16>) if using Standard Buffer mode.
// This bit can only be written when the ON bit = 0
// SPIENHBUF = 0; // not available on all devices
// 5. If SPI interrupts are not going to be used, skip this step and
// continue to step 6. Otherwise the following additional steps are performed:
// a) Clear the SPIx interrupt flags/events in the respective IFS0/1 register.
/*
IntClearFlag(INTFAULT);
IntClearFlag(INTTXDONE);
IntClearFlag(INTRXDONE);
// b) Set the SPIx interrupt enable bits in the respective IEC0/1 register.
IntEnable(INTFAULT);
IntEnable(INTTXDONE);
IntEnable(INTRXDONE);
// c) Write the SPIx interrupt priority and subpriority bits in the respective IPC5/7 register.
IntSetVectorPriority(INTVECTOR, 3, 1);
*/
// 6. Write the Baud Rate register, SPIxBRG.
SPI1BRG = SPI[SPI1].divider; // Default SPI_PBCLOCK_DIV64
// 7. Clear the SPIROV bit (SPIxSTAT<6>).
SPI1STATbits.SPIROV = 0; // clear the Overflow
// 8. Write the desired settings to the SPIxCON register.
/**
* Mode CKP CKE
* SPI_MODE0 0 0
* SPI_MODE1 0 1
* SPI_MODE2 1 0
* SPI_MODE3 1 1
*/
switch (SPI[SPI1].mode)
{
case SPI_MODE0: // SPI bus mode 0,0
SPI1CONbits.CKP = 0;
SPI1CONbits.CKE = 0; // data transmitted on falling edge
break;
case SPI_MODE1: // default SPI bus mode 0,1
SPI1CONbits.CKP = 0;
SPI1CONbits.CKE = 1; // data transmitted on falling edge
break;
case SPI_MODE2: // SPI bus mode 1,0
SPI1CONbits.CKP = 1; // clock idle state high
SPI1CONbits.CKE = 0; // data transmitted on rising edge
break;
case SPI_MODE3: // SPI bus mode 1,1
SPI1CONbits.CKP = 1; // clock idle state high
SPI1CONbits.CKE = 1; // data transmitted on falling edge
break;
}
SPI1CONbits.SMP = SPI[SPI1].phase; // Input data sampled at end of middle of data output time
switch (SPI[SPI1].role)
{
case SPI_MASTER8:
SPI1CONbits.MODE16 = 0;
SPI1CONbits.MODE32 = 0;
SPI1CONbits.MSTEN = 1; // Master
break;
case SPI_MASTER16:
SPI1CONbits.MODE16 = 1;
SPI1CONbits.MODE32 = 0;
SPI1CONbits.MSTEN = 1; // Master
break;
case SPI_MASTER32:
SPI1CONbits.MODE16 = 0;
SPI1CONbits.MODE32 = 1;
SPI1CONbits.MSTEN = 1; // Master
break;
case SPI_SLAVE:
SPI1CONbits.MSTEN = 0; // Slave
break;
}
// The SSx pin is not driven by the SPI Master.
// User have to drive the bit himself and pulse it before the SPI
// transmission takes place.
// He can therefore use any other I/O pin for that purpose,
// but we provide one ;-)
/*
if (SPI[SPI1].role != SPI_SLAVE)
{
#if defined(PINGUINO32MX250) || defined(PINGUINO32MX270) || defined(PINGUINO32MX220)
TRISBCLR = 1<<7; // RB7 is defined as SS1 pin (cf. io.c)
#endif
}
*/
// 9. Enable SPI operation by setting the ON bit (SPIxCON<15>).
SPI1CONSET = 0x8000; // Set bit 15
break;
#endif
case SPI2:
// IO's
#if defined(PINGUINO32MX220) || defined(PINGUINO32MX250) || defined(PINGUINO32MX270)
TRISBCLR = 1<<15; // SCK2 is on RB15 ( D0 )
TRISBSET = 1<<13; // SDI2 is on RB13 ( D2 )
//TRISBCLR = 1<<9; // SS2 is on RB9 ( D3 )
TRISBCLR = 1<<8; // SDO2 is on RB8 ( D4 )
#endif
// 6. Write the Baud Rate register, SPIxBRG.
SPI2BRG = SPI[SPI2].divider; // Default SPI_PBCLOCK_DIV64
// 7. Clear the SPIROV bit (SPIxSTAT<6>).
SPI2STATbits.SPIROV = 0; // clear the Overflow
// 8. Write the desired settings to the SPIxCON register.
switch (SPI[SPI2].mode)
{
case SPI_MODE0: // SPI bus mode 0,0
SPI2CONbits.CKP = 0;
SPI2CONbits.CKE = 0; // data transmitted on falling edge
break;
case SPI_MODE1: // default SPI bus mode 0,1
SPI2CONbits.CKP = 0;
SPI2CONbits.CKE = 1; // data transmitted on falling edge
break;
case SPI_MODE2: // SPI bus mode 1,0
SPI2CONbits.CKP = 1; // clock idle state high
SPI2CONbits.CKE = 0; // data transmitted on rising edge
break;
case SPI_MODE3: // SPI bus mode 1,1
SPI2CONbits.CKP = 1; // clock idle state high
SPI2CONbits.CKE = 1; // data transmitted on falling edge
break;
}
SPI2CONbits.SMP = SPI[SPI2].phase; // Input data sampled at end of middle of data output time
switch (SPI[SPI2].role)
{
case SPI_MASTER8:
SPI2CONbits.MODE16 = 0;
SPI2CONbits.MODE32 = 0;
SPI2CONbits.MSTEN = 1; // Master
break;
case SPI_MASTER16:
SPI2CONbits.MODE16 = 1;
SPI2CONbits.MODE32 = 0;
SPI2CONbits.MSTEN = 1; // Master
break;
case SPI_MASTER32:
SPI2CONbits.MODE16 = 0;
SPI2CONbits.MODE32 = 1;
SPI2CONbits.MSTEN = 1; // Master
break;
case SPI_SLAVE:
SPI2CONbits.MSTEN = 0; // Slave
break;
}
// 9. Enable SPI operation by setting the ON bit (SPIxCON<15>).
SPI2CONSET = 0x8000; // Set bit 15
break;
#if defined(__32MX795F512L__) || \
defined(__32MX795F512H__)
case SPI3:
// 6. Write the Baud Rate register, SPIxBRG.
SPI3BRG = SPI[SPI3].divider; // Default SPI_PBCLOCK_DIV64
// 7. Clear the SPIROV bit (SPIxSTAT<6>).
SPI3STATbits.SPIROV = 0; // clear the Overflow
// 8. Write the desired settings to the SPIxCON register.
switch (SPI[SPI3].mode)
{
case SPI_MODE0: // SPI bus mode 0,0
SPI3CONbits.CKP = 0;
SPI3CONbits.CKE = 0; // data transmitted on falling edge
break;
case SPI_MODE1: // default SPI bus mode 0,1
SPI3CONbits.CKP = 0;
SPI3CONbits.CKE = 1; // data transmitted on falling edge
break;
case SPI_MODE2: // SPI bus mode 1,0
SPI3CONbits.CKP = 1; // clock idle state high
SPI3CONbits.CKE = 0; // data transmitted on rising edge
break;
case SPI_MODE3: // SPI bus mode 1,1
SPI3CONbits.CKP = 1; // clock idle state high
SPI3CONbits.CKE = 1; // data transmitted on falling edge
break;
}
SPI1CONbits.SMP = SPI[SPI3].phase; // Input data sampled at end of middle of data output time
switch (SPI[SPI3].role)
{
case SPI_MASTER8:
SPI3CONbits.MODE16 = 0;
SPI3CONbits.MODE32 = 0;
SPI3CONbits.MSTEN = 1; // Master
break;
case SPI_MASTER16:
SPI3CONbits.MODE16 = 1;
SPI3CONbits.MODE32 = 0;
SPI3CONbits.MSTEN = 1; // Master
break;
case SPI_MASTER32:
SPI3CONbits.MODE16 = 0;
SPI3CONbits.MODE32 = 1;
SPI3CONbits.MSTEN = 1; // Master
break;
case SPI_SLAVE:
SPI3CONbits.MSTEN = 0; // Slave
break;
}
// 9. Enable SPI operation by setting the ON bit (SPIxCON<15>).
SPI3CONSET = 0x8000; // Set bit 15
break;
case SPI4:
// 6. Write the Baud Rate register, SPIxBRG.
SPI4BRG = SPI[SPI4].divider; // Default SPI_PBCLOCK_DIV64
// 7. Clear the SPIROV bit (SPIxSTAT<6>).
SPI4STATbits.SPIROV = 0; // clear the Overflow
// 8. Write the desired settings to the SPIxCON register.
switch (SPI[SPI4].mode)
{
case SPI_MODE0: // SPI bus mode 0,0
SPI4CONbits.CKP = 0;
SPI4CONbits.CKE = 0; // data transmitted on falling edge
break;
case SPI_MODE1: // default SPI bus mode 0,1
SPI4CONbits.CKP = 0;
SPI4CONbits.CKE = 1; // data transmitted on falling edge
break;
case SPI_MODE2: // SPI bus mode 1,0
SPI4CONbits.CKP = 1; // clock idle state high
SPI4CONbits.CKE = 0; // data transmitted on rising edge
break;
case SPI_MODE3: // SPI bus mode 1,1
SPI4CONbits.CKP = 1; // clock idle state high
SPI4CONbits.CKE = 1; // data transmitted on falling edge
break;
}
SPI4CONbits.SMP = SPI[SPI4].phase; // Input data sampled at end of middle of data output time
switch (SPI[SPI4].role)
{
case SPI_MASTER8:
SPI4CONbits.MODE16 = 0;
SPI4CONbits.MODE32 = 0;
SPI4CONbits.MSTEN = 1; // Master
break;
case SPI_MASTER16:
SPI4CONbits.MODE16 = 1;
SPI4CONbits.MODE32 = 0;
SPI4CONbits.MSTEN = 1; // Master
break;
case SPI_MASTER32:
SPI4CONbits.MODE16 = 0;
SPI4CONbits.MODE32 = 1;
SPI4CONbits.MSTEN = 1; // Master
break;
case SPI_SLAVE:
SPI4CONbits.MSTEN = 0; // Slave
break;
}
// 9. Enable SPI operation by setting the ON bit (SPIxCON<15>).
SPI4CONSET = 0x8000; // Set bit 15
break;
#endif
}
}
