void LoadStateUnknown(SPUFreeze_t * pF)
{
int i;
for(i=0;i<MAXCHAN;i++)
{
s_chan[i].bStop=0;
s_chan[i].pLoop=spuMemC;
s_chan[i].pStart=spuMemC;
s_chan[i].pLoop=spuMemC;
}
dwNewChannel=0;
dwChannelOn=0;
pSpuIrq=0;
for(i=0;i<0xc0;i++)
{
SPU_writeRegister(0x1f801c00+i*2,regArea[i]);
}
}
void psxHwWrite16(u32 add, u16 value) {
switch (add) {
case 0x1f801040:
sioWrite8((unsigned char)value);
sioWrite8((unsigned char)(value>>8));
#ifdef PAD_LOG
PAD_LOG ("sio write16 %x, %x\n", add&0xf, value);
#endif
return;
case 0x1f801044:
sioWriteStat16(value);
#ifdef PAD_LOG
PAD_LOG ("sio write16 %x, %x\n", add&0xf, value);
#endif
return;
case 0x1f801048:
sioWriteMode16(value);
#ifdef PAD_LOG
PAD_LOG ("sio write16 %x, %x\n", add&0xf, value);
#endif
return;
case 0x1f80104a: // control register
sioWriteCtrl16(value);
#ifdef PAD_LOG
PAD_LOG ("sio write16 %x, %x\n", add&0xf, value);
#endif
return;
case 0x1f80104e: // baudrate register
sioWriteBaud16(value);
#ifdef PAD_LOG
PAD_LOG ("sio write16 %x, %x\n", add&0xf, value);
#endif
return;
#ifdef ENABLE_SIO1API
case 0x1f801050:
SIO1_writeData16(value);
return;
case 0x1f801054:
SIO1_writeStat16(value);
return;
case 0x1f80105a:
SIO1_writeCtrl16(value);
return;
case 0x1f80105e:
SIO1_writeBaud16(value);
return;
#endif
case 0x1f801070:
#ifdef PSXHW_LOG
PSXHW_LOG("IREG 16bit write %x\n", value);
#endif
if (Config.Sio) psxHu16ref(0x1070) |= SWAPu16(0x80);
if (Config.SpuIrq) psxHu16ref(0x1070) |= SWAPu16(0x200);
psxHu16ref(0x1070) &= SWAPu16((psxHu16(0x1074) & value));
return;
case 0x1f801074:
#ifdef PSXHW_LOG
PSXHW_LOG("IMASK 16bit write %x\n", value);
#endif
psxHu16ref(0x1074) = SWAPu16(value);
if (psxHu16ref(0x1070) & value)
new_dyna_set_event(PSXINT_NEWDRC_CHECK, 1);
return;
case 0x1f801100:
#ifdef PSXHW_LOG
PSXHW_LOG("COUNTER 0 COUNT 16bit write %x\n", value);
#endif
psxRcntWcount(0, value); return;
case 0x1f801104:
#ifdef PSXHW_LOG
PSXHW_LOG("COUNTER 0 MODE 16bit write %x\n", value);
#endif
psxRcntWmode(0, value); return;
case 0x1f801108:
#ifdef PSXHW_LOG
PSXHW_LOG("COUNTER 0 TARGET 16bit write %x\n", value);
#endif
psxRcntWtarget(0, value); return;
case 0x1f801110:
#ifdef PSXHW_LOG
PSXHW_LOG("COUNTER 1 COUNT 16bit write %x\n", value);
#endif
psxRcntWcount(1, value); return;
case 0x1f801114:
#ifdef PSXHW_LOG
PSXHW_LOG("COUNTER 1 MODE 16bit write %x\n", value);
#endif
psxRcntWmode(1, value); return;
case 0x1f801118:
#ifdef PSXHW_LOG
PSXHW_LOG("COUNTER 1 TARGET 16bit write %x\n", value);
#endif
psxRcntWtarget(1, value); return;
case 0x1f801120:
#ifdef PSXHW_LOG
PSXHW_LOG("COUNTER 2 COUNT 16bit write %x\n", value);
#endif
psxRcntWcount(2, value); return;
case 0x1f801124:
#ifdef PSXHW_LOG
PSXHW_LOG("COUNTER 2 MODE 16bit write %x\n", value);
#endif
psxRcntWmode(2, value); return;
case 0x1f801128:
#ifdef PSXHW_LOG
PSXHW_LOG("COUNTER 2 TARGET 16bit write %x\n", value);
#endif
psxRcntWtarget(2, value); return;
default:
if (add>=0x1f801c00 && add<0x1f801e00) {
SPU_writeRegister(add, value);
return;
}
psxHu16ref(add) = SWAPu16(value);
#ifdef PSXHW_LOG
PSXHW_LOG("*Unknown 16bit write at address %x value %x\n", add, value);
#endif
return;
}
psxHu16ref(add) = SWAPu16(value);
#ifdef PSXHW_LOG
PSXHW_LOG("*Known 16bit write at address %x value %x\n", add, value);
#endif
}
void psxHwWrite32(u32 add, u32 value) {
switch (add) {
case 0x1f801040:
sioWrite8((unsigned char)value);
sioWrite8((unsigned char)((value&0xff) >> 8));
sioWrite8((unsigned char)((value&0xff) >> 16));
sioWrite8((unsigned char)((value&0xff) >> 24));
#ifdef PAD_LOG
PAD_LOG("sio write32 %x\n", value);
#endif
return;
#ifdef ENABLE_SIO1API
case 0x1f801050:
SIO1_writeData32(value);
return;
#endif
#ifdef PSXHW_LOG
case 0x1f801060:
PSXHW_LOG("RAM size write %x\n", value);
psxHu32ref(add) = SWAPu32(value);
return; // Ram size
#endif
case 0x1f801070:
#ifdef PSXHW_LOG
PSXHW_LOG("IREG 32bit write %x\n", value);
#endif
if (Config.Sio) psxHu32ref(0x1070) |= SWAPu32(0x80);
if (Config.SpuIrq) psxHu32ref(0x1070) |= SWAPu32(0x200);
psxHu32ref(0x1070) &= SWAPu32((psxHu32(0x1074) & value));
return;
case 0x1f801074:
#ifdef PSXHW_LOG
PSXHW_LOG("IMASK 32bit write %x\n", value);
#endif
psxHu32ref(0x1074) = SWAPu32(value);
if (psxHu32ref(0x1070) & value)
new_dyna_set_event(PSXINT_NEWDRC_CHECK, 1);
return;
#ifdef PSXHW_LOG
case 0x1f801080:
PSXHW_LOG("DMA0 MADR 32bit write %x\n", value);
HW_DMA0_MADR = SWAPu32(value); return; // DMA0 madr
case 0x1f801084:
PSXHW_LOG("DMA0 BCR 32bit write %x\n", value);
HW_DMA0_BCR = SWAPu32(value); return; // DMA0 bcr
#endif
case 0x1f801088:
#ifdef PSXHW_LOG
PSXHW_LOG("DMA0 CHCR 32bit write %x\n", value);
#endif
DmaExec(0); // DMA0 chcr (MDEC in DMA)
return;
#ifdef PSXHW_LOG
case 0x1f801090:
PSXHW_LOG("DMA1 MADR 32bit write %x\n", value);
HW_DMA1_MADR = SWAPu32(value); return; // DMA1 madr
case 0x1f801094:
PSXHW_LOG("DMA1 BCR 32bit write %x\n", value);
HW_DMA1_BCR = SWAPu32(value); return; // DMA1 bcr
#endif
case 0x1f801098:
#ifdef PSXHW_LOG
PSXHW_LOG("DMA1 CHCR 32bit write %x\n", value);
#endif
DmaExec(1); // DMA1 chcr (MDEC out DMA)
return;
#ifdef PSXHW_LOG
case 0x1f8010a0:
PSXHW_LOG("DMA2 MADR 32bit write %x\n", value);
HW_DMA2_MADR = SWAPu32(value); return; // DMA2 madr
case 0x1f8010a4:
PSXHW_LOG("DMA2 BCR 32bit write %x\n", value);
HW_DMA2_BCR = SWAPu32(value); return; // DMA2 bcr
#endif
case 0x1f8010a8:
#ifdef PSXHW_LOG
PSXHW_LOG("DMA2 CHCR 32bit write %x\n", value);
#endif
DmaExec(2); // DMA2 chcr (GPU DMA)
return;
#ifdef PSXHW_LOG
case 0x1f8010b0:
PSXHW_LOG("DMA3 MADR 32bit write %x\n", value);
HW_DMA3_MADR = SWAPu32(value); return; // DMA3 madr
case 0x1f8010b4:
PSXHW_LOG("DMA3 BCR 32bit write %x\n", value);
HW_DMA3_BCR = SWAPu32(value); return; // DMA3 bcr
#endif
case 0x1f8010b8:
#ifdef PSXHW_LOG
PSXHW_LOG("DMA3 CHCR 32bit write %x\n", value);
#endif
DmaExec(3); // DMA3 chcr (CDROM DMA)
return;
#ifdef PSXHW_LOG
case 0x1f8010c0:
PSXHW_LOG("DMA4 MADR 32bit write %x\n", value);
HW_DMA4_MADR = SWAPu32(value); return; // DMA4 madr
case 0x1f8010c4:
PSXHW_LOG("DMA4 BCR 32bit write %x\n", value);
HW_DMA4_BCR = SWAPu32(value); return; // DMA4 bcr
#endif
case 0x1f8010c8:
#ifdef PSXHW_LOG
PSXHW_LOG("DMA4 CHCR 32bit write %x\n", value);
#endif
DmaExec(4); // DMA4 chcr (SPU DMA)
return;
#if 0
case 0x1f8010d0: break; //DMA5write_madr();
case 0x1f8010d4: break; //DMA5write_bcr();
case 0x1f8010d8: break; //DMA5write_chcr(); // Not needed
#endif
#ifdef PSXHW_LOG
case 0x1f8010e0:
PSXHW_LOG("DMA6 MADR 32bit write %x\n", value);
HW_DMA6_MADR = SWAPu32(value); return; // DMA6 bcr
case 0x1f8010e4:
PSXHW_LOG("DMA6 BCR 32bit write %x\n", value);
HW_DMA6_BCR = SWAPu32(value); return; // DMA6 bcr
#endif
case 0x1f8010e8:
#ifdef PSXHW_LOG
PSXHW_LOG("DMA6 CHCR 32bit write %x\n", value);
#endif
DmaExec(6); // DMA6 chcr (OT clear)
return;
#ifdef PSXHW_LOG
case 0x1f8010f0:
PSXHW_LOG("DMA PCR 32bit write %x\n", value);
HW_DMA_PCR = SWAPu32(value);
return;
#endif
case 0x1f8010f4:
#ifdef PSXHW_LOG
PSXHW_LOG("DMA ICR 32bit write %x\n", value);
#endif
{
u32 tmp = value & 0x00ff803f;
tmp |= (SWAPu32(HW_DMA_ICR) & ~value) & 0x7f000000;
if ((tmp & HW_DMA_ICR_GLOBAL_ENABLE && tmp & 0x7f000000)
|| tmp & HW_DMA_ICR_BUS_ERROR) {
if (!(SWAPu32(HW_DMA_ICR) & HW_DMA_ICR_IRQ_SENT))
psxHu32ref(0x1070) |= SWAP32(8);
tmp |= HW_DMA_ICR_IRQ_SENT;
}
HW_DMA_ICR = SWAPu32(tmp);
return;
}
case 0x1f801810:
#ifdef PSXHW_LOG
PSXHW_LOG("GPU DATA 32bit write %x\n", value);
#endif
GPU_writeData(value); return;
case 0x1f801814:
#ifdef PSXHW_LOG
PSXHW_LOG("GPU STATUS 32bit write %x\n", value);
#endif
GPU_writeStatus(value);
gpuSyncPluginSR();
return;
case 0x1f801820:
mdecWrite0(value); break;
case 0x1f801824:
mdecWrite1(value); break;
case 0x1f801100:
#ifdef PSXHW_LOG
PSXHW_LOG("COUNTER 0 COUNT 32bit write %x\n", value);
#endif
psxRcntWcount(0, value & 0xffff); return;
case 0x1f801104:
#ifdef PSXHW_LOG
PSXHW_LOG("COUNTER 0 MODE 32bit write %x\n", value);
#endif
psxRcntWmode(0, value); return;
case 0x1f801108:
#ifdef PSXHW_LOG
PSXHW_LOG("COUNTER 0 TARGET 32bit write %x\n", value);
#endif
psxRcntWtarget(0, value & 0xffff); return; // HW_DMA_ICR&= SWAP32((~value)&0xff000000);
case 0x1f801110:
#ifdef PSXHW_LOG
PSXHW_LOG("COUNTER 1 COUNT 32bit write %x\n", value);
#endif
psxRcntWcount(1, value & 0xffff); return;
case 0x1f801114:
#ifdef PSXHW_LOG
PSXHW_LOG("COUNTER 1 MODE 32bit write %x\n", value);
#endif
psxRcntWmode(1, value); return;
case 0x1f801118:
#ifdef PSXHW_LOG
PSXHW_LOG("COUNTER 1 TARGET 32bit write %x\n", value);
#endif
psxRcntWtarget(1, value & 0xffff); return;
case 0x1f801120:
#ifdef PSXHW_LOG
PSXHW_LOG("COUNTER 2 COUNT 32bit write %x\n", value);
#endif
psxRcntWcount(2, value & 0xffff); return;
case 0x1f801124:
#ifdef PSXHW_LOG
PSXHW_LOG("COUNTER 2 MODE 32bit write %x\n", value);
#endif
psxRcntWmode(2, value); return;
case 0x1f801128:
#ifdef PSXHW_LOG
PSXHW_LOG("COUNTER 2 TARGET 32bit write %x\n", value);
#endif
psxRcntWtarget(2, value & 0xffff); return;
default:
// Dukes of Hazard 2 - car engine noise
if (add>=0x1f801c00 && add<0x1f801e00) {
SPU_writeRegister(add, value&0xffff);
SPU_writeRegister(add + 2, value>>16);
return;
}
psxHu32ref(add) = SWAPu32(value);
#ifdef PSXHW_LOG
PSXHW_LOG("*Unknown 32bit write at address %x value %x\n", add, value);
#endif
return;
}
void psxHwWrite32(u32 add, u32 value) {
switch (add) {
case 0x1f801040:
sioWrite8((unsigned char)value);
sioWrite8((unsigned char)((value&0xff) >> 8));
sioWrite8((unsigned char)((value&0xff) >> 16));
sioWrite8((unsigned char)((value&0xff) >> 24));
#ifdef PAD_LOG
PAD_LOG("sio write32 %x\n", value);
#endif
return;
#ifdef ENABLE_SIO1API
case 0x1f801050:
SIO1_writeData32(value);
#ifdef SIO1_LOG
SIO1_LOG("sio1 write32 %x\n", value);
#endif
return;
#endif
#ifdef PSXHW_LOG
case 0x1f801060:
PSXHW_LOG("RAM size write %x\n", value);
psxHu32ref(add) = SWAPu32(value);
return; // Ram size
#endif
case 0x1f801070:
#ifdef PSXHW_LOG
PSXHW_LOG("IREG 32bit write %x\n", value);
#endif
if (Config.SioIrq) psxHu32ref(0x1070) |= SWAPu32(0x80);
if (Config.SpuIrq) psxHu32ref(0x1070) |= SWAPu32(0x200);
psxHu32ref(0x1070) &= SWAPu32(value);
return;
case 0x1f801074:
#ifdef PSXHW_LOG
PSXHW_LOG("IMASK 32bit write %x\n", value);
#endif
psxHu32ref(0x1074) = SWAPu32(value);
return;
#ifdef PSXHW_LOG
case 0x1f801080:
PSXHW_LOG("DMA0 MADR 32bit write %x\n", value);
HW_DMA0_MADR = SWAPu32(value);
return; // DMA0 madr
case 0x1f801084:
PSXHW_LOG("DMA0 BCR 32bit write %x\n", value);
HW_DMA0_BCR = SWAPu32(value);
return; // DMA0 bcr
#endif
case 0x1f801088:
#ifdef PSXHW_LOG
PSXHW_LOG("DMA0 CHCR 32bit write %x\n", value);
#endif
DmaExec(0); // DMA0 chcr (MDEC in DMA)
return;
#ifdef PSXHW_LOG
case 0x1f801090:
PSXHW_LOG("DMA1 MADR 32bit write %x\n", value);
HW_DMA1_MADR = SWAPu32(value);
return; // DMA1 madr
case 0x1f801094:
PSXHW_LOG("DMA1 BCR 32bit write %x\n", value);
HW_DMA1_BCR = SWAPu32(value);
return; // DMA1 bcr
#endif
case 0x1f801098:
#ifdef PSXHW_LOG
PSXHW_LOG("DMA1 CHCR 32bit write %x\n", value);
#endif
DmaExec(1); // DMA1 chcr (MDEC out DMA)
return;
#ifdef PSXHW_LOG
case 0x1f8010a0:
PSXHW_LOG("DMA2 MADR 32bit write %x\n", value);
HW_DMA2_MADR = SWAPu32(value);
return; // DMA2 madr
case 0x1f8010a4:
PSXHW_LOG("DMA2 BCR 32bit write %x\n", value);
HW_DMA2_BCR = SWAPu32(value);
return; // DMA2 bcr
#endif
case 0x1f8010a8:
#ifdef PSXHW_LOG
PSXHW_LOG("DMA2 CHCR 32bit write %x\n", value);
#endif
/* A hack that makes Vampire Hunter D title screen visible,
/* but makes Tomb Raider II water effect to stay opaque
/* Root cause for this problem is that when DMA2 is issued
/* it is incompletele and still beign built by the game.
/* Maybe it is ready when some signal comes in or within given delay?
*/
if (dmaGpuListHackEn && value == 0x00000401 && HW_DMA2_BCR == 0x0) {
psxDma2(SWAPu32(HW_DMA2_MADR), SWAPu32(HW_DMA2_BCR), SWAPu32(value));
return;
}
DmaExec(2); // DMA2 chcr (GPU DMA)
if (HW_DMA2_CHCR == 0x1000401)
dmaGpuListHackEn=TRUE;
return;
#ifdef PSXHW_LOG
case 0x1f8010b0:
PSXHW_LOG("DMA3 MADR 32bit write %x\n", value);
HW_DMA3_MADR = SWAPu32(value);
return; // DMA3 madr
case 0x1f8010b4:
PSXHW_LOG("DMA3 BCR 32bit write %x\n", value);
HW_DMA3_BCR = SWAPu32(value);
return; // DMA3 bcr
#endif
case 0x1f8010b8:
#ifdef PSXHW_LOG
PSXHW_LOG("DMA3 CHCR 32bit write %x\n", value);
#endif
DmaExec(3); // DMA3 chcr (CDROM DMA)
return;
#ifdef PSXHW_LOG
case 0x1f8010c0:
PSXHW_LOG("DMA4 MADR 32bit write %x\n", value);
HW_DMA4_MADR = SWAPu32(value);
return; // DMA4 madr
case 0x1f8010c4:
PSXHW_LOG("DMA4 BCR 32bit write %x\n", value);
HW_DMA4_BCR = SWAPu32(value);
return; // DMA4 bcr
#endif
case 0x1f8010c8:
#ifdef PSXHW_LOG
PSXHW_LOG("DMA4 CHCR 32bit write %x\n", value);
#endif
DmaExec(4); // DMA4 chcr (SPU DMA)
return;
#if 0
case 0x1f8010d0:
break; //DMA5write_madr();
case 0x1f8010d4:
break; //DMA5write_bcr();
case 0x1f8010d8:
break; //DMA5write_chcr(); // Not needed
#endif
#ifdef PSXHW_LOG
case 0x1f8010e0:
PSXHW_LOG("DMA6 MADR 32bit write %x\n", value);
HW_DMA6_MADR = SWAPu32(value);
return; // DMA6 bcr
case 0x1f8010e4:
PSXHW_LOG("DMA6 BCR 32bit write %x\n", value);
HW_DMA6_BCR = SWAPu32(value);
return; // DMA6 bcr
#endif
case 0x1f8010e8:
#ifdef PSXHW_LOG
PSXHW_LOG("DMA6 CHCR 32bit write %x\n", value);
#endif
DmaExec(6); // DMA6 chcr (OT clear)
return;
#ifdef PSXHW_LOG
case 0x1f8010f0:
PSXHW_LOG("DMA PCR 32bit write %x\n", value);
HW_DMA_PCR = SWAPu32(value);
return;
#endif
case 0x1f8010f4:
#ifdef PSXHW_LOG
PSXHW_LOG("DMA ICR 32bit write %x\n", value);
#endif
{
u32 tmp = (~value) & SWAPu32(HW_DMA_ICR);
HW_DMA_ICR = SWAPu32(((tmp ^ value) & 0xffffff) ^ tmp);
return;
}
case 0x1f801014:
#ifdef PSXHW_LOG
PSXHW_LOG("SPU delay [0x1014] write32: %8.8lx\n", value);
#endif
psxHu32ref(add) = SWAPu32(value);
return;
case 0x1f801810:
#ifdef PSXHW_LOG
PSXHW_LOG("GPU DATA 32bit write %x\n", value);
#endif
GPU_writeData(value);
return;
case 0x1f801814:
#ifdef PSXHW_LOG
PSXHW_LOG("GPU STATUS 32bit write %x\n", value);
#endif
if (value & 0x8000000)
dmaGpuListHackEn=FALSE;
GPU_writeStatus(value);
return;
case 0x1f801820:
mdecWrite0(value);
break;
case 0x1f801824:
mdecWrite1(value);
break;
case 0x1f801100:
#ifdef PSXHW_LOG
PSXHW_LOG("COUNTER 0 COUNT 32bit write %x\n", value);
#endif
psxRcntWcount(0, value & 0xffff);
return;
case 0x1f801104:
#ifdef PSXHW_LOG
PSXHW_LOG("COUNTER 0 MODE 32bit write %x\n", value);
#endif
psxRcntWmode(0, value);
return;
case 0x1f801108:
#ifdef PSXHW_LOG
PSXHW_LOG("COUNTER 0 TARGET 32bit write %x\n", value);
#endif
psxRcntWtarget(0, value & 0xffff);
return; // HW_DMA_ICR&= SWAP32((~value)&0xff000000);
case 0x1f801110:
#ifdef PSXHW_LOG
PSXHW_LOG("COUNTER 1 COUNT 32bit write %x\n", value);
#endif
psxRcntWcount(1, value & 0xffff);
return;
case 0x1f801114:
#ifdef PSXHW_LOG
PSXHW_LOG("COUNTER 1 MODE 32bit write %x\n", value);
#endif
psxRcntWmode(1, value);
return;
case 0x1f801118:
#ifdef PSXHW_LOG
PSXHW_LOG("COUNTER 1 TARGET 32bit write %x\n", value);
#endif
psxRcntWtarget(1, value & 0xffff);
return;
case 0x1f801120:
#ifdef PSXHW_LOG
PSXHW_LOG("COUNTER 2 COUNT 32bit write %x\n", value);
#endif
psxRcntWcount(2, value & 0xffff);
return;
case 0x1f801124:
#ifdef PSXHW_LOG
PSXHW_LOG("COUNTER 2 MODE 32bit write %x\n", value);
#endif
psxRcntWmode(2, value);
return;
case 0x1f801128:
#ifdef PSXHW_LOG
PSXHW_LOG("COUNTER 2 TARGET 32bit write %x\n", value);
#endif
psxRcntWtarget(2, value & 0xffff);
return;
default:
// Dukes of Hazard 2 - car engine noise
if (add>=0x1f801c00 && add<0x1f801e00) {
SPU_writeRegister(add, value&0xffff);
add += 2;
value >>= 16;
if (add>=0x1f801c00 && add<0x1f801e00)
SPU_writeRegister(add, value&0xffff);
return;
}
psxHu32ref(add) = SWAPu32(value);
#ifdef PSXHW_LOG
PSXHW_LOG("*Unknown 32bit write at address %x value %x\n", add, value);
#endif
return;
}