/**************************************************************************** * Set all registers to given values ****************************************************************************/ static void m6805_set_context(void *src) { if( src ) { m6805 = *(m6805_Regs*)src; S = SP_ADJUST( S ); } }
static void m6805_set_info(UINT32 state, cpuinfo *info) { switch (state) { /* --- the following bits of info are set as 64-bit signed integers --- */ case CPUINFO_INT_INPUT_STATE + M6805_IRQ_LINE: set_irq_line(M6805_IRQ_LINE, info->i); break; case CPUINFO_INT_REGISTER + M6805_A: A = info->i; break; case CPUINFO_INT_PC: case CPUINFO_INT_REGISTER + M6805_PC: PC = info->i; change_pc(PC); break; case CPUINFO_INT_SP: case CPUINFO_INT_REGISTER + M6805_S: S = SP_ADJUST(info->i); break; case CPUINFO_INT_REGISTER + M6805_X: X = info->i; break; case CPUINFO_INT_REGISTER + M6805_CC: CC = info->i; break; } }
static CPU_SET_INFO( m6805 ) { m6805_Regs *cpustate = get_safe_token(device); switch (state) { /* --- the following bits of info are set as 64-bit signed integers --- */ case CPUINFO_INT_INPUT_STATE + M6805_IRQ_LINE: set_irq_line(cpustate, M6805_IRQ_LINE, info->i); break; case CPUINFO_INT_REGISTER + M6805_A: A = info->i; break; case CPUINFO_INT_PC: case CPUINFO_INT_REGISTER + M6805_PC: PC = info->i; break; case CPUINFO_INT_SP: case CPUINFO_INT_REGISTER + M6805_S: S = SP_ADJUST(info->i); break; case CPUINFO_INT_REGISTER + M6805_X: X = info->i; break; case CPUINFO_INT_REGISTER + M6805_CC: CC = info->i; break; } }
static void m6805_set_info(UINT32 state, union cpuinfo *info) { switch (state) { /* --- the following bits of info are set as 64-bit signed integers --- */ case CPUINFO_INT_INPUT_STATE + M6805_IRQ_LINE: set_irq_line(M6805_IRQ_LINE, info->i); break; case CPUINFO_INT_REGISTER + M6805_A: A = info->i; break; case CPUINFO_INT_PC: case CPUINFO_INT_REGISTER + M6805_PC: PC = info->i; change_pc(PC); break; case CPUINFO_INT_SP: case CPUINFO_INT_REGISTER + M6805_S: S = SP_ADJUST(info->i); break; case CPUINFO_INT_REGISTER + M6805_X: X = info->i; break; case CPUINFO_INT_REGISTER + M6805_CC: CC = info->i; break; /* --- the following bits of info are set as pointers to data or functions --- */ case CPUINFO_PTR_IRQ_CALLBACK: m6805.irq_callback = info->irqcallback; break; } }
/* execute instructions on this CPU until icount expires */ void m6805_base_device::execute_run() { S = SP_ADJUST( S ); /* Taken from CPU_SET_CONTEXT when pointer'afying */ do { if (m_pending_interrupts != 0) { interrupt(); } debugger_instruction_hook(this, PC); u8 const ireg = rdop(PC++); (this->*m_params.m_ops[ireg])(); m_icount -= m_params.m_cycles[ireg]; burn_cycles(m_params.m_cycles[ireg]); } while (m_icount > 0); }
/* execute instructions on this CPU until icount expires */ void m6805_base_device::execute_run() { UINT8 ireg; S = SP_ADJUST( S ); /* Taken from CPU_SET_CONTEXT when pointer'afying */ do { if (m_pending_interrupts != 0) { interrupt(); } debugger_instruction_hook(this, PC); ireg=M_RDOP(PC++); switch( ireg ) { case 0x00: brset(0x01); break; case 0x01: brclr(0x01); break; case 0x02: brset(0x02); break; case 0x03: brclr(0x02); break; case 0x04: brset(0x04); break; case 0x05: brclr(0x04); break; case 0x06: brset(0x08); break; case 0x07: brclr(0x08); break; case 0x08: brset(0x10); break; case 0x09: brclr(0x10); break; case 0x0A: brset(0x20); break; case 0x0B: brclr(0x20); break; case 0x0C: brset(0x40); break; case 0x0D: brclr(0x40); break; case 0x0E: brset(0x80); break; case 0x0F: brclr(0x80); break; case 0x10: bset(0x01); break; case 0x11: bclr(0x01); break; case 0x12: bset(0x02); break; case 0x13: bclr(0x02); break; case 0x14: bset(0x04); break; case 0x15: bclr(0x04); break; case 0x16: bset(0x08); break; case 0x17: bclr(0x08); break; case 0x18: bset(0x10); break; case 0x19: bclr(0x10); break; case 0x1a: bset(0x20); break; case 0x1b: bclr(0x20); break; case 0x1c: bset(0x40); break; case 0x1d: bclr(0x40); break; case 0x1e: bset(0x80); break; case 0x1f: bclr(0x80); break; case 0x20: bra(); break; case 0x21: brn(); break; case 0x22: bhi(); break; case 0x23: bls(); break; case 0x24: bcc(); break; case 0x25: bcs(); break; case 0x26: bne(); break; case 0x27: beq(); break; case 0x28: bhcc(); break; case 0x29: bhcs(); break; case 0x2a: bpl(); break; case 0x2b: bmi(); break; case 0x2c: bmc(); break; case 0x2d: bms(); break; case 0x2e: bil(); break; case 0x2f: bih(); break; case 0x30: neg_di(); break; case 0x31: illegal(); break; case 0x32: illegal(); break; case 0x33: com_di(); break; case 0x34: lsr_di(); break; case 0x35: illegal(); break; case 0x36: ror_di(); break; case 0x37: asr_di(); break; case 0x38: lsl_di(); break; case 0x39: rol_di(); break; case 0x3a: dec_di(); break; case 0x3b: illegal(); break; case 0x3c: inc_di(); break; case 0x3d: tst_di(); break; case 0x3e: illegal(); break; case 0x3f: clr_di(); break; case 0x40: nega(); break; case 0x41: illegal(); break; case 0x42: illegal(); break; case 0x43: coma(); break; case 0x44: lsra(); break; case 0x45: illegal(); break; case 0x46: rora(); break; case 0x47: asra(); break; case 0x48: lsla(); break; case 0x49: rola(); break; case 0x4a: deca(); break; case 0x4b: illegal(); break; case 0x4c: inca(); break; case 0x4d: tsta(); break; case 0x4e: illegal(); break; case 0x4f: clra(); break; case 0x50: negx(); break; case 0x51: illegal(); break; case 0x52: illegal(); break; case 0x53: comx(); break; case 0x54: lsrx(); break; case 0x55: illegal(); break; case 0x56: rorx(); break; case 0x57: asrx(); break; case 0x58: aslx(); break; case 0x59: rolx(); break; case 0x5a: decx(); break; case 0x5b: illegal(); break; case 0x5c: incx(); break; case 0x5d: tstx(); break; case 0x5e: illegal(); break; case 0x5f: clrx(); break; case 0x60: neg_ix1(); break; case 0x61: illegal(); break; case 0x62: illegal(); break; case 0x63: com_ix1(); break; case 0x64: lsr_ix1(); break; case 0x65: illegal(); break; case 0x66: ror_ix1(); break; case 0x67: asr_ix1(); break; case 0x68: lsl_ix1(); break; case 0x69: rol_ix1(); break; case 0x6a: dec_ix1(); break; case 0x6b: illegal(); break; case 0x6c: inc_ix1(); break; case 0x6d: tst_ix1(); break; case 0x6e: illegal(); break; case 0x6f: clr_ix1(); break; case 0x70: neg_ix(); break; case 0x71: illegal(); break; case 0x72: illegal(); break; case 0x73: com_ix(); break; case 0x74: lsr_ix(); break; case 0x75: illegal(); break; case 0x76: ror_ix(); break; case 0x77: asr_ix(); break; case 0x78: lsl_ix(); break; case 0x79: rol_ix(); break; case 0x7a: dec_ix(); break; case 0x7b: illegal(); break; case 0x7c: inc_ix(); break; case 0x7d: tst_ix(); break; case 0x7e: illegal(); break; case 0x7f: clr_ix(); break; case 0x80: rti(); break; case 0x81: rts(); break; case 0x82: illegal(); break; case 0x83: swi(); break; case 0x84: illegal(); break; case 0x85: illegal(); break; case 0x86: illegal(); break; case 0x87: illegal(); break; case 0x88: illegal(); break; case 0x89: illegal(); break; case 0x8a: illegal(); break; case 0x8b: illegal(); break; case 0x8c: illegal(); break; case 0x8d: illegal(); break; case 0x8e: illegal(); break; case 0x8f: illegal(); break; case 0x90: illegal(); break; case 0x91: illegal(); break; case 0x92: illegal(); break; case 0x93: illegal(); break; case 0x94: illegal(); break; case 0x95: illegal(); break; case 0x96: illegal(); break; case 0x97: tax(); break; case 0x98: CLC; break; case 0x99: SEC; break; #if IRQ_LEVEL_DETECT case 0x9a: CLI; if (m_irq_state != CLEAR_LINE) m_pending_interrupts |= 1 << M6805_IRQ_LINE; break; #else case 0x9a: CLI; break; #endif case 0x9b: SEI; break; case 0x9c: rsp(); break; case 0x9d: nop(); break; case 0x9e: illegal(); break; case 0x9f: txa(); break; case 0xa0: suba_im(); break; case 0xa1: cmpa_im(); break; case 0xa2: sbca_im(); break; case 0xa3: cpx_im(); break; case 0xa4: anda_im(); break; case 0xa5: bita_im(); break; case 0xa6: lda_im(); break; case 0xa7: illegal(); break; case 0xa8: eora_im(); break; case 0xa9: adca_im(); break; case 0xaa: ora_im(); break; case 0xab: adda_im(); break; case 0xac: illegal(); break; case 0xad: bsr(); break; case 0xae: ldx_im(); break; case 0xaf: illegal(); break; case 0xb0: suba_di(); break; case 0xb1: cmpa_di(); break; case 0xb2: sbca_di(); break; case 0xb3: cpx_di(); break; case 0xb4: anda_di(); break; case 0xb5: bita_di(); break; case 0xb6: lda_di(); break; case 0xb7: sta_di(); break; case 0xb8: eora_di(); break; case 0xb9: adca_di(); break; case 0xba: ora_di(); break; case 0xbb: adda_di(); break; case 0xbc: jmp_di(); break; case 0xbd: jsr_di(); break; case 0xbe: ldx_di(); break; case 0xbf: stx_di(); break; case 0xc0: suba_ex(); break; case 0xc1: cmpa_ex(); break; case 0xc2: sbca_ex(); break; case 0xc3: cpx_ex(); break; case 0xc4: anda_ex(); break; case 0xc5: bita_ex(); break; case 0xc6: lda_ex(); break; case 0xc7: sta_ex(); break; case 0xc8: eora_ex(); break; case 0xc9: adca_ex(); break; case 0xca: ora_ex(); break; case 0xcb: adda_ex(); break; case 0xcc: jmp_ex(); break; case 0xcd: jsr_ex(); break; case 0xce: ldx_ex(); break; case 0xcf: stx_ex(); break; case 0xd0: suba_ix2(); break; case 0xd1: cmpa_ix2(); break; case 0xd2: sbca_ix2(); break; case 0xd3: cpx_ix2(); break; case 0xd4: anda_ix2(); break; case 0xd5: bita_ix2(); break; case 0xd6: lda_ix2(); break; case 0xd7: sta_ix2(); break; case 0xd8: eora_ix2(); break; case 0xd9: adca_ix2(); break; case 0xda: ora_ix2(); break; case 0xdb: adda_ix2(); break; case 0xdc: jmp_ix2(); break; case 0xdd: jsr_ix2(); break; case 0xde: ldx_ix2(); break; case 0xdf: stx_ix2(); break; case 0xe0: suba_ix1(); break; case 0xe1: cmpa_ix1(); break; case 0xe2: sbca_ix1(); break; case 0xe3: cpx_ix1(); break; case 0xe4: anda_ix1(); break; case 0xe5: bita_ix1(); break; case 0xe6: lda_ix1(); break; case 0xe7: sta_ix1(); break; case 0xe8: eora_ix1(); break; case 0xe9: adca_ix1(); break; case 0xea: ora_ix1(); break; case 0xeb: adda_ix1(); break; case 0xec: jmp_ix1(); break; case 0xed: jsr_ix1(); break; case 0xee: ldx_ix1(); break; case 0xef: stx_ix1(); break; case 0xf0: suba_ix(); break; case 0xf1: cmpa_ix(); break; case 0xf2: sbca_ix(); break; case 0xf3: cpx_ix(); break; case 0xf4: anda_ix(); break; case 0xf5: bita_ix(); break; case 0xf6: lda_ix(); break; case 0xf7: sta_ix(); break; case 0xf8: eora_ix(); break; case 0xf9: adca_ix(); break; case 0xfa: ora_ix(); break; case 0xfb: adda_ix(); break; case 0xfc: jmp_ix(); break; case 0xfd: jsr_ix(); break; case 0xfe: ldx_ix(); break; case 0xff: stx_ix(); break; } m_icount -= m_cycles1[ireg]; } while( m_icount > 0 ); }
void m6805_get_info(UINT32 state, union cpuinfo *info) { switch (state) { /* --- the following bits of info are returned as 64-bit signed integers --- */ case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(m6805); break; case CPUINFO_INT_INPUT_LINES: info->i = 1; break; case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0; break; case CPUINFO_INT_ENDIANNESS: info->i = CPU_IS_BE; break; case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1; break; case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 1; break; case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 3; break; case CPUINFO_INT_MIN_CYCLES: info->i = 2; break; case CPUINFO_INT_MAX_CYCLES: info->i = 10; break; case CPUINFO_INT_DATABUS_WIDTH + ADDRESS_SPACE_PROGRAM: info->i = 8; break; case CPUINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_PROGRAM: info->i = 12; break; case CPUINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_PROGRAM: info->i = 0; break; case CPUINFO_INT_DATABUS_WIDTH + ADDRESS_SPACE_DATA: info->i = 0; break; case CPUINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_DATA: info->i = 0; break; case CPUINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_DATA: info->i = 0; break; case CPUINFO_INT_DATABUS_WIDTH + ADDRESS_SPACE_IO: info->i = 0; break; case CPUINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_IO: info->i = 0; break; case CPUINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_IO: info->i = 0; break; case CPUINFO_INT_INPUT_STATE + M6805_IRQ_LINE: info->i = m6805.irq_state[M6805_IRQ_LINE]; break; case CPUINFO_INT_PREVIOUSPC: /* not implemented */ break; case CPUINFO_INT_REGISTER + M6805_A: info->i = A; break; case CPUINFO_INT_PC: info->i = PC; break; case CPUINFO_INT_REGISTER + M6805_PC: info->i = PC; break; case CPUINFO_INT_SP: case CPUINFO_INT_REGISTER + M6805_S: info->i = SP_ADJUST(S); break; case CPUINFO_INT_REGISTER + M6805_X: info->i = X; break; case CPUINFO_INT_REGISTER + M6805_CC: info->i = CC; break; /* --- the following bits of info are returned as pointers to data or functions --- */ case CPUINFO_PTR_SET_INFO: info->setinfo = m6805_set_info; break; case CPUINFO_PTR_GET_CONTEXT: info->getcontext = m6805_get_context; break; case CPUINFO_PTR_SET_CONTEXT: info->setcontext = m6805_set_context; break; case CPUINFO_PTR_INIT: info->init = m6805_init; break; case CPUINFO_PTR_RESET: info->reset = m6805_reset; break; case CPUINFO_PTR_EXIT: info->exit = m6805_exit; break; case CPUINFO_PTR_EXECUTE: info->execute = m6805_execute; break; case CPUINFO_PTR_BURN: info->burn = NULL; break; case CPUINFO_PTR_DISASSEMBLE: info->disassemble = m6805_dasm; break; case CPUINFO_PTR_IRQ_CALLBACK: info->irqcallback = m6805.irq_callback; break; case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &m6805_ICount; break; case CPUINFO_PTR_REGISTER_LAYOUT: info->p = m6805_reg_layout; break; case CPUINFO_PTR_WINDOW_LAYOUT: info->p = m6805_win_layout; break; /* --- the following bits of info are returned as NULL-terminated strings --- */ case CPUINFO_STR_NAME: strcpy(info->s = cpuintrf_temp_str(), "M6805"); break; case CPUINFO_STR_CORE_FAMILY: strcpy(info->s = cpuintrf_temp_str(), "Motorola 6805"); break; case CPUINFO_STR_CORE_VERSION: strcpy(info->s = cpuintrf_temp_str(), "1.0"); break; case CPUINFO_STR_CORE_FILE: strcpy(info->s = cpuintrf_temp_str(), __FILE__); break; case CPUINFO_STR_CORE_CREDITS: strcpy(info->s = cpuintrf_temp_str(), "The MAME team."); break; case CPUINFO_STR_FLAGS: sprintf(info->s = cpuintrf_temp_str(), "%c%c%c%c%c%c%c%c", m6805.cc & 0x80 ? '?':'.', m6805.cc & 0x40 ? '?':'.', m6805.cc & 0x20 ? '?':'.', m6805.cc & 0x10 ? 'H':'.', m6805.cc & 0x08 ? 'I':'.', m6805.cc & 0x04 ? 'N':'.', m6805.cc & 0x02 ? 'Z':'.', m6805.cc & 0x01 ? 'C':'.'); break; case CPUINFO_STR_REGISTER + M6805_A: sprintf(info->s = cpuintrf_temp_str(), "A:%02X", m6805.a); break; case CPUINFO_STR_REGISTER + M6805_PC: sprintf(info->s = cpuintrf_temp_str(), "PC:%04X", m6805.pc.w.l); break; case CPUINFO_STR_REGISTER + M6805_S: sprintf(info->s = cpuintrf_temp_str(), "S:%02X", m6805.s.w.l); break; case CPUINFO_STR_REGISTER + M6805_X: sprintf(info->s = cpuintrf_temp_str(), "X:%02X", m6805.x); break; case CPUINFO_STR_REGISTER + M6805_CC: sprintf(info->s = cpuintrf_temp_str(), "CC:%02X", m6805.cc); break; } }