ERROR_CODE SetupForFlash()
{
#if ( defined(__ADSP21375__) || defined(__ADSP21369__) || defined(__ADSP21469__) || defined(__ADSP21479__) || defined(__ADSP21489__))
SRU(SPI_CLK_O,DPI_PB03_I);
SRU(HIGH,DPI_PBEN03_I);
// for the flag pins to act as chip select
SRU(FLAG4_O, DPI_PB05_I);
SRU(HIGH, DPI_PBEN05_I);
//First set flag 4 as an output
sysreg_bit_set( sysreg_FLAGS, FLG4O ); //asm("bit set flags FLG4O;");
sysreg_bit_set( sysreg_FLAGS, FLG4 ); //asm("bit set flags FLG4;"); //Logic high
#elif (__ADSP21364__) || (__ADSP21262__)
//First set flag 0 as an output
sysreg_bit_set( sysreg_FLAGS, FLG0O ); //asm("bit set flags FLG0O;");
sysreg_bit_set( sysreg_FLAGS, FLG0 ); //asm("bit set flags FLG0;"); //Logic high
#endif
*pSPIDMAC = 0;
*pSPIBAUD = 0;
*pSPIFLG = 0xF80;
*pSPICTL = 0x400;
return NO_ERR;
}
void exibicaoPrincipal(void) { // maindisplay
glMatrixMode (GL_PROJECTION);
glLoadIdentity ();
gluOrtho2D(-20 * zoom, 20 * zoom, -20 * zoom, 20 * zoom);
glMatrixMode (GL_MODELVIEW);
glLoadIdentity ();
glClear (GL_COLOR_BUFFER_BIT | GL_DEPTH_BUFFER_BIT);
SRU();
//desenha circulo
glColor3f(0.0f,0.0,1.0);//Azul
glPointSize(2.0f);
double coeficiente = (double)360/ 72;
for(int i = 0; i < 72; i++)
{
glBegin(GL_POINTS);
glVertex2f(RetornaX(i*coeficiente, (double)10), RetornaY(i*coeficiente, (double)10));
glEnd();
}
glutSwapBuffers();
}
void dspcontroller_spi_init() {
// init SPI MASTER TX
*(volatile int *)DSPC_SHARC_SPICTL = 0;
*(volatile int *)DSPC_SHARC_SPIFLG = 0;
// set SPI BAUD
*(volatile int *)DSPC_SHARC_SPIBAUD = 20;
// set up DAG registers
*(volatile int *)DSPC_SHARC_SPICTL = DSPC_SHARC_TIMOD|
DSPC_SHARC_MSBF|
DSPC_SHARC_SPIMS|
DSPC_SHARC_SPIEN|
DSPC_SHARC_GM;
// init DAI pin for SS
// *(volatile int *)(0x247D) = 0;
SRU(HIGH,PBEN15_I);
SRU(HIGH,DAI_PB15_I);
}
void exibicaoPrincipal(void) { // maindisplay
glMatrixMode (GL_PROJECTION);
glLoadIdentity ();
gluOrtho2D(-20, 20, -20, 20);
glMatrixMode (GL_MODELVIEW);
glLoadIdentity ();
glClear (GL_COLOR_BUFFER_BIT | GL_DEPTH_BUFFER_BIT);
SRU();
//desenha circulo
glColor3f(0.0f,0.0,1.0);//Azul
glPointSize(2.0f);
desenhaCirculo(5.0f, 5.0f, 5.0f);
desenhaCirculo(5.0f, -5.0f, 5.0f);
desenhaCirculo(5.0f, 0.0f, -5.0f);
//traça o triangulo entre os centros dos circulos
//a - b
desenhaReta(-5, 5, 5, 5);
desenhaReta(5, 5, 0, -5);
desenhaReta(0, -5, -5, 5);
glutSwapBuffers();
}
void DDS_init_io(void) {
//DAI => We can't use flags. Value has to be set low or high.
// Oscillator starts active
SRU(HIGH,PIN_OSC_EN);
SRU(LOW,PIN_SCALE_b0);
SRU(LOW,PIN_SCALE_b1);
SRU(LOW,PIN_RESET);
SRU(LOW,PIN_DATA);
SRU(LOW,PIN_FQ_UD);
SRU(LOW,PIN_W_CLK3);
SRU(LOW,PIN_W_CLK2);
SRU(LOW,PIN_W_CLK1);
SRU(LOW,DAI_PB02_I);
//Enabling the Buffer using the following sequence: High -> Output, Low -> Input
SRU(HIGH,PBEN_OSC_EN); //default format to enable the buffer using DAI
SRU(HIGH,PBEN_SCALE_b0);
SRU(HIGH,PBEN_SCALE_b1); //default format to enable the buffer using DAI
SRU(HIGH,PBEN_RESET);
SRU(HIGH,PBEN_DATA); //default format to enable the buffer using DAI
SRU(HIGH,PBEN_FQ_UD);
SRU(HIGH,PBEN_W_CLK3); //default format to enable the buffer using DAI
SRU(HIGH,PBEN_W_CLK2);
SRU(HIGH,PBEN_W_CLK1); //default format to enable the buffer using DAI
SRU(LOW,PBEN02_I);
}
void InitDAI(){
//-----------------------------------------------------------------------------
//
// MCLK: The output of the 12.288 MHz xtal is either directly connected to the
// codec, but also connected to DAI_P06, or just to DAI_P17. This is
// determined by switches 7.1 and 7.2 For this example we route the
// MCLK into DAI_P17 and supply the clock to the ADC via DAI_P06
// by routing the signal through the SRU.
// Tie the pin buffer input LOW.
SRU(LOW,DAI_PB17_I);
// Tie the pin buffer enable input LOW
SRU(LOW,PBEN17_I);
//-----------------------------------------------------------------------------
//
// Connect the ADC: The codec drives a BCLK output to DAI pin 7, a LRCLK
// (a.k.a. frame sync) to DAI pin 8 and data to DAI pin 5.
//
// Connect the ADC to SPORT0, using data input A
//
// All three lines are always inputs to the SHARC so tie the pin
// buffer inputs and pin buffer enable inputs all low.
//------------------------------------------------------------------------
// Connect the ADC to SPORT0, using data input A
// Clock in on pin 7
SRU(DAI_PB07_O,SPORT0_CLK_I);
// Frame sync in on pin 8
SRU(DAI_PB08_O,SPORT0_FS_I);
// Data in on pin 5
SRU(DAI_PB05_O,SPORT0_DA_I);
//------------------------------------------------------------------------
// Tie the pin buffer inputs LOW for DAI pins 5, 6 7 and 8. Even though
// these pins are inputs to the SHARC, tying unused pin buffer inputs
// LOW is "good coding style" to eliminate the possibility of
// termination artifacts internal to the IC. Note that signal
// integrity is degraded only with a few specific SRU combinations.
// In practice, this occurs VERY rarely, and these connections are
// typically unnecessary.
SRU(LOW,DAI_PB05_I);
SRU(LOW,DAI_PB07_I);
SRU(LOW,DAI_PB08_I);
//------------------------------------------------------------------------
// Tie the pin buffer enable inputs LOW for DAI pins 5, 6, 7 and 8 so
// that they are always input pins.
SRU(LOW,PBEN05_I);
SRU(LOW,PBEN07_I);
SRU(LOW,PBEN08_I);
//-----------------------------------------------------------------------------
//
// Connect the DACs: The codec accepts a BCLK input from DAI pin 13 and
// a LRCLK (a.k.a. frame sync) from DAI pin 14 and has four
// serial data outputs to DAI pins 12, 11, 10 and 9
//
// Connect DAC1 to SPORT1, using data output A
// Connect DAC2 to SPORT1, using data output B
// Connect DAC3 to SPORT2, using data output A
// Connect DAC4 to SPORT2, using data output B
//
// Connect the clock and frame sync inputs to SPORT1 and SPORT2
// should come from the ADC on DAI pins 7 and 8, respectively
//
// Connect the ADC BCLK and LRCLK back out to the DAC on DAI
// pins 13 and 14, respectively.
//
// All six DAC connections are always outputs from the SHARC
// so tie the pin buffer enable inputs all high.
//
//------------------------------------------------------------------------
// Connect the pin buffers to the SPORT data lines and ADC BCLK & LRCLK
SRU(SPORT2_DB_O,DAI_PB09_I);
SRU(SPORT2_DA_O,DAI_PB10_I);
SRU(SPORT1_DB_O,DAI_PB11_I);
SRU(SPORT1_DA_O,DAI_PB12_I);
//------------------------------------------------------------------------
// Connect the clock and frame sync input from the ADC directly
// to the output pins driving the DACs.
SRU(DAI_PB07_O,DAI_PB13_I);
SRU(DAI_PB08_O,DAI_PB14_I);
SRU(DAI_PB17_O,DAI_PB06_I);
//------------------------------------------------------------------------
// Connect the SPORT clocks and frame syncs to the clock and
// frame sync from the SPDIF receiver
SRU(DAI_PB07_O,SPORT1_CLK_I);
SRU(DAI_PB07_O,SPORT2_CLK_I);
SRU(DAI_PB08_O,SPORT1_FS_I);
SRU(DAI_PB08_O,SPORT2_FS_I);
//------------------------------------------------------------------------
// Tie the pin buffer enable inputs HIGH to make DAI pins 9-14 outputs.
SRU(HIGH,PBEN06_I);
SRU(HIGH,PBEN09_I);
SRU(HIGH,PBEN10_I);
SRU(HIGH,PBEN11_I);
SRU(HIGH,PBEN12_I);
SRU(HIGH,PBEN13_I);
SRU(HIGH,PBEN14_I);
}
/************************************************************
Function: InitDDS_IO (void)
Argument:
Description: Initializes DDS and Current Scale IO pins
Action: Sets all of the DDS pins as outputs.
Oscillator starts High and the rest starts
Low.
************************************************************/
void InitDDS_IO(void){
// Starting value of the Output Pins.
// DDS Oscillator Enable (default: HIGH)
//DDS_OSC_EN_ON;
// DDS Oscillator generated internally by PCG
SRU (PCG_FSA_O, DAI_PB08_I);
// Driver Current Scale (default: minimum scale 00)
DDS_SCALE_b1_L; // b1
DDS_SCALE_b0_L; // b0
// DDS Reset
DDS_RESET_L;
// DDS Data
DDS_DATA_H;
// DDS Frequency Update
DDS_FQ_UD_L;
// DDS #1 Write Clock
DDS_W_CLK1_L;
// DDS #2 Write Clock
DDS_W_CLK2_L;
// DDS #3 Write Clock
DDS_W_CLK3_L;
// DAI 02 Frame synce Register
SRU(LOW,DAI_PB07_I);
//Enabling pins as Outputs. High -> Output, Low -> Input
// DDS Oscillator Enable
SRU(HIGH,PBEN08_I);
// Driver Current Scale
SRU(HIGH,PBEN19_I);
SRU(HIGH,PBEN01_I);
// DDS Reset
SRU(HIGH,PBEN10_I);
// DDS Data
SRU(HIGH,PBEN20_I);
// DDS Frequency Update
SRU(HIGH,PBEN02_I);
// DDS #1 Write Clock
SRU(HIGH,PBEN06_I);
// DDS #2 Write Clock
SRU(HIGH,PBEN05_I);
// DDS #3 Write Clock
SRU(HIGH,PBEN09_I);
// DAI 02 Frame sync Register
SRU(HIGH,PBEN07_I);
// #!#!#!#! PARA ALTERAR!
}
