static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
{
MCOperand *Op = MCInst_getOperand(MI, OpNo);
if (MCOperand_isReg(Op)) {
printRegName(O, MCOperand_getReg(Op));
if (MI->csh->detail) {
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_REG;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].reg = MCOperand_getReg(Op);
MI->flat_insn->detail->x86.op_count++;
}
} else if (MCOperand_isImm(Op)) {
// Print X86 immediates as signed values.
int64_t imm = MCOperand_getImm(Op);
if (imm >= 0) {
if (imm > HEX_THRESHOLD)
SStream_concat(O, "%s$0x%"PRIx64"%s", markup("<imm:"), imm, markup(">"));
else
SStream_concat(O, "%s$%"PRIu64"%s", markup("<imm:"), imm, markup(">"));
} else {
if (imm < -HEX_THRESHOLD)
SStream_concat(O, "%s$-0x%"PRIx64"%s", markup("<imm:"), -imm, markup(">"));
else
SStream_concat(O, "%s$-%"PRIu64"%s", markup("<imm:"), -imm, markup(">"));
}
if (MI->csh->detail) {
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_IMM;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].imm = imm;
MI->flat_insn->detail->x86.op_count++;
}
}
}
/// printPCRelImm - This is used to print an immediate value that ends up
/// being encoded as a pc-relative value (e.g. for jumps and calls). These
/// print slightly differently than normal immediates. For example, a $ is not
/// emitted.
static void printPCRelImm(MCInst *MI, unsigned OpNo, SStream *O)
{
MCOperand *Op = MCInst_getOperand(MI, OpNo);
if (MCOperand_isImm(Op)) {
int64_t imm = MCOperand_getImm(Op) + MI->flat_insn->size + MI->address;
if (imm < 0) {
if (imm < -HEX_THRESHOLD)
SStream_concat(O, "-0x%"PRIx64, -imm);
else
SStream_concat(O, "-%"PRIu64, -imm);
} else {
// handle 16bit segment bound
if (MI->csh->mode == CS_MODE_16 && imm > 0x100000)
imm -= 0x10000;
if (imm > HEX_THRESHOLD)
SStream_concat(O, "0x%"PRIx64, imm);
else
SStream_concat(O, "%"PRIu64, imm);
}
if (MI->csh->detail) {
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_IMM;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].imm = imm;
MI->flat_insn->detail->x86.op_count++;
}
}
}
void printUInt64Bang(SStream *O, uint64_t val)
{
if (val > HEX_THRESHOLD)
SStream_concat(O, "#0x%"PRIx64, val);
else
SStream_concat(O, "#%"PRIu64, val);
}
static void printBDLAddrOperand(MCInst *MI, int OpNum, SStream *O)
{
unsigned Base = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
uint64_t Disp = (uint64_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1));
uint64_t Length = (uint64_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum + 2));
if (Disp > HEX_THRESHOLD)
SStream_concat(O, "0x%"PRIx64, Disp);
else
SStream_concat(O, "%"PRIu64, Disp);
if (Length > HEX_THRESHOLD)
SStream_concat(O, "(0x%"PRIx64, Length);
else
SStream_concat(O, "(%"PRIu64, Length);
if (Base)
SStream_concat(O, ", %%%s", getRegisterName(Base));
SStream_concat0(O, ")");
if (MI->csh->detail) {
MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_MEM;
MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.base = (uint8_t)SystemZ_map_register(Base);
MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.length = Length;
MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.disp = (int64_t)Disp;
MI->flat_insn->detail->sysz.op_count++;
}
}
void printUInt32(SStream *O, uint32_t val)
{
if (val > HEX_THRESHOLD)
SStream_concat(O, "0x%x", val);
else
SStream_concat(O, "%u", val);
}
// print number in decimal mode
void printInt32BangDec(SStream *O, int32_t val)
{
if (val >= 0)
SStream_concat(O, "#%u", val);
else
SStream_concat(O, "#-%u", -val);
}
static void printPCRelOperand(MCInst *MI, int OpNum, SStream *O)
{
MCOperand *MO = MCInst_getOperand(MI, OpNum);
int32_t imm;
if (MCOperand_isImm(MO)) {
imm = (int32_t)MCOperand_getImm(MO);
if (imm >= 0) {
if (imm > HEX_THRESHOLD)
SStream_concat(O, "0x%x", imm);
else
SStream_concat(O, "%u", imm);
} else {
if (imm < -HEX_THRESHOLD)
SStream_concat(O, "-0x%x", -imm);
else
SStream_concat(O, "-%u", -imm);
}
if (MI->csh->detail) {
MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM;
MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = (int64_t)imm;
MI->flat_insn->detail->sysz.op_count++;
}
}
}
/// printPCRelImm - This is used to print an immediate value that ends up
/// being encoded as a pc-relative value.
static void printPCRelImm(MCInst *MI, unsigned OpNo, SStream *O)
{
MCOperand *Op = MCInst_getOperand(MI, OpNo);
if (MCOperand_isImm(Op)) {
int64_t imm = MCOperand_getImm(Op) + MI->flat_insn->size + MI->address;
if (imm < 0) {
SStream_concat(O, "0x%"PRIx64, imm);
} else {
// handle 16bit segment bound
if (MI->csh->mode == CS_MODE_16 && imm > 0x100000)
imm -= 0x10000;
if (imm > HEX_THRESHOLD)
SStream_concat(O, "0x%"PRIx64, imm);
else
SStream_concat(O, "%"PRIu64, imm);
}
if (MI->csh->detail) {
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_IMM;
// if op_count > 0, then this operand's size is taken from the destination op
if (MI->flat_insn->detail->x86.op_count > 0)
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->flat_insn->detail->x86.operands[0].size;
else
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->imm_size;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].imm = imm;
MI->flat_insn->detail->x86.op_count++;
}
if (MI->op1_size == 0)
MI->op1_size = MI->imm_size;
}
}
static void printLogicalImm64(MCInst *MI, unsigned OpNum, SStream *O)
{
int64_t Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
Val = AArch64_AM_decodeLogicalImmediate(Val, 64);
switch(MI->flat_insn->id) {
default:
printInt64Bang(O, Val);
break;
case ARM64_INS_ORR:
case ARM64_INS_AND:
case ARM64_INS_EOR:
case ARM64_INS_TST:
// do not print number in negative form
if (Val >= 0 && Val <= HEX_THRESHOLD)
SStream_concat(O, "#%u", (int)Val);
else
SStream_concat(O, "#0x%"PRIx64, Val);
break;
}
if (MI->csh->detail) {
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = (int)Val;
MI->flat_insn->detail->arm64.op_count++;
}
}
static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
{
MCOperand *Op = MCInst_getOperand(MI, OpNo);
if (MCOperand_isReg(Op)) {
printRegName(O, MCOperand_getReg(Op));
if (MI->detail) {
MI->pub_insn.x86.operands[MI->pub_insn.x86.op_count].type = X86_OP_REG;
MI->pub_insn.x86.operands[MI->pub_insn.x86.op_count].reg = MCOperand_getReg(Op);
MI->pub_insn.x86.op_count++;
}
} else if (MCOperand_isImm(Op)) {
int64_t imm = MCOperand_getImm(Op);
if (imm >= 0) {
if (imm > HEX_THRESHOLD)
SStream_concat(O, "0x%"PRIx64, imm);
else
SStream_concat(O, "%"PRIu64, imm);
} else {
if (imm <= -HEX_THRESHOLD)
SStream_concat(O, "-0x%"PRIx64, -imm);
else
SStream_concat(O, "-%"PRIu64, -imm);
}
if (MI->detail) {
MI->pub_insn.x86.operands[MI->pub_insn.x86.op_count].type = X86_OP_IMM;
MI->pub_insn.x86.operands[MI->pub_insn.x86.op_count].imm = imm;
MI->pub_insn.x86.op_count++;
}
}
}
static void printDstIdx(MCInst *MI, unsigned Op, SStream *O)
{
if (MI->csh->detail) {
#ifndef CAPSTONE_DIET
uint8_t access[6];
#endif
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->x86opsize;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_REG_INVALID;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.base = X86_REG_INVALID;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.index = X86_REG_INVALID;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.scale = 1;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = 0;
#ifndef CAPSTONE_DIET
get_op_access(MI->csh, MCInst_getOpcode(MI), access, &MI->flat_insn->detail->x86.eflags);
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].access = access[MI->flat_insn->detail->x86.op_count];
#endif
}
// DI accesses are always ES-based on non-64bit mode
if (MI->csh->mode != CS_MODE_64) {
SStream_concat(O, "es:[");
if (MI->csh->detail) {
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_REG_ES;
}
} else
SStream_concat(O, "[");
set_mem_access(MI, true);
printOperand(MI, Op, O);
SStream_concat0(O, "]");
set_mem_access(MI, false);
}
static void printS16ImmOperand_Mem(MCInst *MI, unsigned OpNo, SStream *O)
{
if (MCOperand_isImm(MCInst_getOperand(MI, OpNo))) {
short Imm = (short)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
// Do not print zero offset
if (Imm == 0)
return;
if (Imm >= 0) {
if (Imm > HEX_THRESHOLD)
SStream_concat(O, "0x%x", Imm);
else
SStream_concat(O, "%u", Imm);
} else {
if (Imm < -HEX_THRESHOLD)
SStream_concat(O, "-0x%x", -Imm);
else
SStream_concat(O, "-%u", -Imm);
}
if (MI->csh->detail) {
if (MI->csh->doing_mem) {
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].mem.disp = Imm;
} else {
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Imm;
MI->flat_insn->detail->ppc.op_count++;
}
}
} else
printOperand(MI, OpNo, O);
}
static void printU8Imm(MCInst *MI, unsigned Op, SStream *O)
{
uint8_t val = MCOperand_getImm(MCInst_getOperand(MI, Op)) & 0xff;
if (val > HEX_THRESHOLD)
SStream_concat(O, "0x%x", val);
else
SStream_concat(O, "%u", val);
if (MI->csh->detail) {
#ifndef CAPSTONE_DIET
uint8_t access[6];
#endif
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_IMM;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].imm = val;
#ifndef CAPSTONE_DIET
get_op_access(MI->csh, MCInst_getOpcode(MI), access, &MI->flat_insn->detail->x86.eflags);
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].access = access[MI->flat_insn->detail->x86.op_count];
#endif
MI->flat_insn->detail->x86.op_count++;
}
}
static void printDstIdx(MCInst *MI, unsigned Op, SStream *O)
{
if (MI->csh->detail) {
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->x86opsize;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_REG_INVALID;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.base = X86_REG_INVALID;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.index = X86_REG_INVALID;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.scale = 1;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = 0;
}
// DI accesses are always ES-based on non-64bit mode
if (MI->csh->mode != CS_MODE_64) {
SStream_concat(O, "es:[");
if (MI->csh->detail) {
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_REG_ES;
}
} else
SStream_concat(O, "[");
set_mem_access(MI, true);
printOperand(MI, Op, O);
SStream_concat0(O, "]");
set_mem_access(MI, false);
}
static void printDstIdx(MCInst *MI, unsigned Op, SStream *O)
{
SStream_concat(O, "%s%s", markup("<mem:"), "%es:(");
printOperand(MI, Op, O);
SStream_concat(O, ")%s", markup(">"));
}
static void printMemOffset(MCInst *MI, unsigned Op, SStream *O)
{
MCOperand *DispSpec = MCInst_getOperand(MI, Op);
MCOperand *SegReg = MCInst_getOperand(MI, Op + 1);
int reg;
if (MI->csh->detail) {
#ifndef CAPSTONE_DIET
uint8_t access[6];
#endif
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->x86opsize;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_REG_INVALID;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.base = X86_REG_INVALID;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.index = X86_REG_INVALID;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.scale = 1;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = 0;
#ifndef CAPSTONE_DIET
get_op_access(MI->csh, MCInst_getOpcode(MI), access, &MI->flat_insn->detail->x86.eflags);
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].access = access[MI->flat_insn->detail->x86.op_count];
#endif
}
// If this has a segment register, print it.
reg = MCOperand_getReg(SegReg);
if (reg) {
_printOperand(MI, Op + 1, O);
SStream_concat0(O, ":");
if (MI->csh->detail) {
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = reg;
}
}
SStream_concat0(O, "[");
if (MCOperand_isImm(DispSpec)) {
int64_t imm = MCOperand_getImm(DispSpec);
if (MI->csh->detail)
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = imm;
if (imm < 0) {
SStream_concat(O, "0x%"PRIx64, arch_masks[MI->csh->mode] & imm);
} else {
if (imm > HEX_THRESHOLD)
SStream_concat(O, "0x%"PRIx64, imm);
else
SStream_concat(O, "%"PRIu64, imm);
}
}
SStream_concat0(O, "]");
if (MI->csh->detail)
MI->flat_insn->detail->x86.op_count++;
if (MI->op1_size == 0)
MI->op1_size = MI->x86opsize;
}
static void printTLSCall(MCInst *MI, unsigned OpNo, SStream *O)
{
set_mem_access(MI, true);
printBranchOperand(MI, OpNo, O);
SStream_concat(O, "(");
printOperand(MI, OpNo + 1, O);
SStream_concat(O, ")");
set_mem_access(MI, false);
}
static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
{
MCOperand *Op = MCInst_getOperand(MI, OpNo);
if (MCOperand_isReg(Op)) {
unsigned reg = MCOperand_getReg(Op);
#ifndef CAPSTONE_DIET
char *RegName = getRegisterName(reg);
#endif
// map to public register
reg = PPC_map_register(reg);
#ifndef CAPSTONE_DIET
// The linux and AIX assembler does not take register prefixes.
if (MI->csh->syntax == CS_OPT_SYNTAX_NOREGNAME)
RegName = stripRegisterPrefix(RegName);
SStream_concat0(O, RegName);
#endif
if (MI->csh->detail) {
if (MI->csh->doing_mem) {
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].mem.base = reg;
} else {
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_REG;
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].reg = reg;
MI->flat_insn->detail->ppc.op_count++;
}
}
return;
}
if (MCOperand_isImm(Op)) {
int64_t imm = MCOperand_getImm(Op);
if (imm >= 0) {
if (imm > HEX_THRESHOLD)
SStream_concat(O, "0x%" PRIx64, imm);
else
SStream_concat(O, "%" PRIu64 , imm);
} else {
if (imm < -HEX_THRESHOLD)
SStream_concat(O, "-0x%" PRIx64 , -imm);
else
SStream_concat(O, "-%" PRIu64 , -imm);
}
if (MI->csh->detail) {
if (MI->csh->doing_mem) {
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].mem.disp = imm;
} else {
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = imm;
MI->flat_insn->detail->ppc.op_count++;
}
}
}
}
static void printMemExtend(MCInst *MI, unsigned OpNum, SStream *O, char SrcRegKind, unsigned Width)
{
unsigned SignExtend = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
unsigned DoShift = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1));
// sxtw, sxtx, uxtw or lsl (== uxtx)
bool IsLSL = !SignExtend && SrcRegKind == 'x';
if (IsLSL) {
SStream_concat0(O, "lsl");
if (MI->csh->detail) {
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].shift.type = ARM64_SFT_LSL;
}
} else {
SStream_concat(O, "%cxt%c", (SignExtend ? 's' : 'u'), SrcRegKind);
if (MI->csh->detail) {
if (!SignExtend) {
switch(SrcRegKind) {
default: break;
case 'b':
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].ext = ARM64_EXT_UXTB;
break;
case 'h':
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].ext = ARM64_EXT_UXTH;
break;
case 'w':
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].ext = ARM64_EXT_UXTW;
break;
}
} else {
switch(SrcRegKind) {
default: break;
case 'b':
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].ext = ARM64_EXT_SXTB;
break;
case 'h':
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].ext = ARM64_EXT_SXTH;
break;
case 'w':
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].ext = ARM64_EXT_SXTW;
break;
case 'x':
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].ext = ARM64_EXT_SXTX;
break;
}
}
}
}
if (DoShift || IsLSL) {
SStream_concat(O, " #%u", Log2_32(Width / 8));
if (MI->csh->detail) {
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].shift.type = ARM64_SFT_LSL;
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].shift.value = Log2_32(Width / 8);
}
}
}
static void printMemOperand(MCInst *MI, int opNum, SStream *O)
{
// Load/Store memory operands -- imm($reg)
// If PIC target the target is loaded as the
// pattern lw $25,%call16($28)
set_mem_access(MI, true);
printOperand(MI, opNum + 1, O);
SStream_concat(O, "(");
printOperand(MI, opNum, O);
SStream_concat(O, ")");
set_mem_access(MI, false);
}
static void printMemOffs32(MCInst *MI, unsigned OpNo, SStream *O)
{
SStream_concat(O, "dword ptr ");
// If this has a segment register, print it.
// this is a hack. will fix it later
if (MI->x86_segment) {
SStream_concat(O, "%s:", X86_reg_name(1, MI->x86_segment));
}
printMemOffset(MI, OpNo, O);
}
static void printMemRegReg(MCInst *MI, unsigned OpNo, SStream *O)
{
// When used as the base register, r0 reads constant zero rather than
// the value contained in the register. For this reason, the darwin
// assembler requires that we print r0 as 0 (no r) when used as the base.
if (MCOperand_getReg(MCInst_getOperand(MI, OpNo)) == PPC_R0)
SStream_concat(O, "0");
else
printOperand(MI, OpNo, O);
SStream_concat(O, ", ");
printOperand(MI, OpNo + 1, O);
}
void printInt32(SStream *O, int32_t val)
{
if (val >= 0) {
if (val > HEX_THRESHOLD)
SStream_concat(O, "0x%x", val);
else
SStream_concat(O, "%u", val);
} else {
if (val <- HEX_THRESHOLD)
SStream_concat(O, "-0x%x", -val);
else
SStream_concat(O, "-%u", -val);
}
}
// print number
void printInt64(SStream *O, int64_t val)
{
if (val >= 0) {
if (val > HEX_THRESHOLD)
SStream_concat(O, "0x%"PRIx64, val);
else
SStream_concat(O, "%"PRIu64, val);
} else {
if (val <- HEX_THRESHOLD)
SStream_concat(O, "-0x%"PRIx64, -val);
else
SStream_concat(O, "-%"PRIu64, -val);
}
}
static void printU6ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
{
unsigned int Value = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
//assert(Value <= 63 && "Invalid u6imm argument!");
if (Value > HEX_THRESHOLD)
SStream_concat(O, "0x%x", Value);
else
SStream_concat(O, "%u", Value);
if (MI->csh->detail) {
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Value;
MI->flat_insn->detail->ppc.op_count++;
}
}
static void printU8Imm(MCInst *MI, unsigned Op, SStream *O)
{
uint8_t val = MCOperand_getImm(MCInst_getOperand(MI, Op)) & 0xff;
if (val > HEX_THRESHOLD)
SStream_concat(O, "$0x%x", val);
else
SStream_concat(O, "$%u", val);
if (MI->csh->detail) {
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_IMM;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].imm = val;
MI->flat_insn->detail->x86.op_count++;
}
}
static void printMemRegImm(MCInst *MI, unsigned OpNo, SStream *O)
{
set_mem_access(MI, true);
printS16ImmOperand_Mem(MI, OpNo, O);
SStream_concat(O, "(");
if (MCOperand_getReg(MCInst_getOperand(MI, OpNo + 1)) == PPC_R0)
SStream_concat(O, "0");
else
printOperand(MI, OpNo + 1, O);
SStream_concat(O, ")");
set_mem_access(MI, false);
}
static void printU32ImmOperand(MCInst *MI, int OpNum, SStream *O)
{
uint32_t Value = (uint32_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
// assert(isUInt<32>(Value) && "Invalid u32imm argument");
if (Value > HEX_THRESHOLD)
SStream_concat(O, "0x%x", Value);
else
SStream_concat(O, "%u", Value);
if (MI->csh->detail) {
MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM;
MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = (int64_t)Value;
MI->flat_insn->detail->sysz.op_count++;
}
}
static void printInstructionName(cs_struct *handle, SStream *OS,
unsigned int insn)
{
#ifndef CAPSTONE_DIET
SStream_concat(OS, handle->insn_name((csh)handle, insn));
#endif
}
static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
{
MCOperand *Op = MCInst_getOperand(MI, OpNo);
if (MCOperand_isReg(Op)) {
unsigned int reg = MCOperand_getReg(Op);
printRegName(O, reg);
reg = Mips_map_register(reg);
if (MI->csh->detail) {
if (MI->csh->doing_mem) {
MI->flat_insn.mips.operands[MI->flat_insn.mips.op_count].mem.base = reg;
} else {
MI->flat_insn.mips.operands[MI->flat_insn.mips.op_count].type = MIPS_OP_REG;
MI->flat_insn.mips.operands[MI->flat_insn.mips.op_count].reg = reg;
MI->flat_insn.mips.op_count++;
}
}
}
if (MCOperand_isImm(Op)) {
int64_t imm = MCOperand_getImm(Op);
if (MI->csh->doing_mem) {
if (imm) { // only print Imm offset if it is not 0
if (imm >= 0) {
if (imm > HEX_THRESHOLD)
SStream_concat(O, "0x%"PRIx64, imm);
else
SStream_concat(O, "%"PRIu64, imm);
} else {
if (imm <= -HEX_THRESHOLD)
SStream_concat(O, "-0x%"PRIx64, -imm);
else
SStream_concat(O, "-%"PRIu64, -imm);
}
}
if (MI->csh->detail)
MI->flat_insn.mips.operands[MI->flat_insn.mips.op_count].mem.disp = imm;
} else {
if (imm >= 0) {
if (imm > HEX_THRESHOLD)
SStream_concat(O, "0x%"PRIx64, imm);
else
SStream_concat(O, "%"PRIu64, imm);
} else {
if (imm <= -HEX_THRESHOLD)
SStream_concat(O, "-0x%"PRIx64, -imm);
else
SStream_concat(O, "-%"PRIu64, -imm);
}
if (MI->csh->detail) {
MI->flat_insn.mips.operands[MI->flat_insn.mips.op_count].type = MIPS_OP_IMM;
MI->flat_insn.mips.operands[MI->flat_insn.mips.op_count].imm = imm;
MI->flat_insn.mips.op_count++;
}
}
}
}
