/*static*/ void GpioPlateformImplementation::internalPinSetupOutput( const int pin )
{
const int pinNum = SUNXI_GPD( pin );
const unsigned int val = 1; // 0 = input , 1 = output
unsigned int cfg;
unsigned int bank = GPIO_BANK( pinNum );
unsigned int index = GPIO_CFG_INDEX( pinNum );
unsigned int offset = GPIO_CFG_OFFSET( pinNum );
if( s_sunxi_pio_base == 0)
return ;
struct sunxi_gpio *pio = &((struct sunxi_gpio_reg *) s_sunxi_pio_base )->gpio_bank[bank];
cfg = *(&pio->cfg[0] + index);
cfg &= ~(0xf << offset);
cfg |= val << offset;
*(&pio->cfg[0] + index) = cfg;
return ;
}
GpioState GpioPlateformImplementation::internalRead()
{
const int pinNum = SUNXI_GPD( _pin );
unsigned int dat;
unsigned int bank = GPIO_BANK( pinNum );
unsigned int num = GPIO_NUM( pinNum );
if(s_sunxi_pio_base == 0)
return undefined;
struct sunxi_gpio *pio =&((struct sunxi_gpio_reg *) s_sunxi_pio_base )->gpio_bank[bank];
dat = *(&pio->dat);
dat >>= num;
return ( GpioState ) (dat & 0x1);
}
/*static*/ void GpioPlateformImplementation::internalSetOutput( const int pin , const GpioState state )
{
const int pinNum = SUNXI_GPD( pin );
unsigned int bank = GPIO_BANK( pinNum );
unsigned int num = GPIO_NUM( pinNum );
if( s_sunxi_pio_base == 0)
{
return ;
}
struct sunxi_gpio *pio =&((struct sunxi_gpio_reg *) s_sunxi_pio_base )->gpio_bank[bank];
if( state == high )
*(&pio->dat) |= 1 << num;
else
*(&pio->dat) &= ~(1 << num);
}
static void sunxi_lcdc_tcon0_mode_set(const struct ctfb_res_modes *mode,
bool for_ext_vga_dac)
{
struct sunxi_lcdc_reg * const lcdc =
(struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
struct sunxi_ccm_reg * const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
int clk_div, clk_double, pin;
struct display_timing timing;
#if defined CONFIG_MACH_SUN8I && defined CONFIG_VIDEO_LCD_IF_LVDS
for (pin = SUNXI_GPD(18); pin <= SUNXI_GPD(27); pin++) {
#else
for (pin = SUNXI_GPD(0); pin <= SUNXI_GPD(27); pin++) {
#endif
#ifdef CONFIG_VIDEO_LCD_IF_PARALLEL
sunxi_gpio_set_cfgpin(pin, SUNXI_GPD_LCD0);
#endif
#ifdef CONFIG_VIDEO_LCD_IF_LVDS
sunxi_gpio_set_cfgpin(pin, SUNXI_GPD_LVDS0);
#endif
#ifdef CONFIG_VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
sunxi_gpio_set_drv(pin, 3);
#endif
}
lcdc_pll_set(ccm, 0, mode->pixclock_khz, &clk_div, &clk_double,
sunxi_is_composite());
sunxi_ctfb_mode_to_display_timing(mode, &timing);
lcdc_tcon0_mode_set(lcdc, &timing, clk_div, for_ext_vga_dac,
sunxi_display.depth, CONFIG_VIDEO_LCD_DCLK_PHASE);
}
#if defined CONFIG_VIDEO_HDMI || defined CONFIG_VIDEO_VGA || defined CONFIG_VIDEO_COMPOSITE
static void sunxi_lcdc_tcon1_mode_set(const struct ctfb_res_modes *mode,
int *clk_div, int *clk_double,
bool use_portd_hvsync)
{
struct sunxi_lcdc_reg * const lcdc =
(struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
struct sunxi_ccm_reg * const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
struct display_timing timing;
sunxi_ctfb_mode_to_display_timing(mode, &timing);
lcdc_tcon1_mode_set(lcdc, &timing, use_portd_hvsync,
sunxi_is_composite());
if (use_portd_hvsync) {
sunxi_gpio_set_cfgpin(SUNXI_GPD(26), SUNXI_GPD_LCD0);
sunxi_gpio_set_cfgpin(SUNXI_GPD(27), SUNXI_GPD_LCD0);
}
lcdc_pll_set(ccm, 1, mode->pixclock_khz, clk_div, clk_double,
sunxi_is_composite());
}
#endif /* CONFIG_VIDEO_HDMI || defined CONFIG_VIDEO_VGA || CONFIG_VIDEO_COMPOSITE */
#ifdef CONFIG_VIDEO_HDMI
static void sunxi_hdmi_setup_info_frames(const struct ctfb_res_modes *mode)
{
struct sunxi_hdmi_reg * const hdmi =
(struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
u8 checksum = 0;
u8 avi_info_frame[17] = {
0x82, 0x02, 0x0d, 0x00, 0x12, 0x00, 0x88, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00
};
u8 vendor_info_frame[19] = {
0x81, 0x01, 0x06, 0x29, 0x03, 0x0c, 0x00, 0x40,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00
};
int i;
if (mode->pixclock_khz <= 27000)
avi_info_frame[5] = 0x40; /* SD-modes, ITU601 colorspace */
else
avi_info_frame[5] = 0x80; /* HD-modes, ITU709 colorspace */
if (mode->xres * 100 / mode->yres < 156)
avi_info_frame[5] |= 0x18; /* 4 : 3 */
else
avi_info_frame[5] |= 0x28; /* 16 : 9 */
for (i = 0; i < ARRAY_SIZE(avi_info_frame); i++)
checksum += avi_info_frame[i];
avi_info_frame[3] = 0x100 - checksum;
for (i = 0; i < ARRAY_SIZE(avi_info_frame); i++)
writeb(avi_info_frame[i], &hdmi->avi_info_frame[i]);
writel(SUNXI_HDMI_QCP_PACKET0, &hdmi->qcp_packet0);
writel(SUNXI_HDMI_QCP_PACKET1, &hdmi->qcp_packet1);
for (i = 0; i < ARRAY_SIZE(vendor_info_frame); i++)
writeb(vendor_info_frame[i], &hdmi->vendor_info_frame[i]);
writel(SUNXI_HDMI_PKT_CTRL0, &hdmi->pkt_ctrl0);
writel(SUNXI_HDMI_PKT_CTRL1, &hdmi->pkt_ctrl1);
setbits_le32(&hdmi->video_ctrl, SUNXI_HDMI_VIDEO_CTRL_HDMI);
}
static void sunxi_hdmi_mode_set(const struct ctfb_res_modes *mode,
int clk_div, int clk_double)
{
struct sunxi_hdmi_reg * const hdmi =
(struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
int x, y;
/* Write clear interrupt status bits */
writel(SUNXI_HDMI_IRQ_STATUS_BITS, &hdmi->irq);
if (sunxi_display.monitor == sunxi_monitor_hdmi)
sunxi_hdmi_setup_info_frames(mode);
/* Set input sync enable */
writel(SUNXI_HDMI_UNKNOWN_INPUT_SYNC, &hdmi->unknown);
/* Init various registers, select pll3 as clock source */
writel(SUNXI_HDMI_VIDEO_POL_TX_CLK, &hdmi->video_polarity);
writel(SUNXI_HDMI_PAD_CTRL0_RUN, &hdmi->pad_ctrl0);
writel(SUNXI_HDMI_PAD_CTRL1, &hdmi->pad_ctrl1);
writel(SUNXI_HDMI_PLL_CTRL, &hdmi->pll_ctrl);
writel(SUNXI_HDMI_PLL_DBG0_PLL3, &hdmi->pll_dbg0);
/* Setup clk div and doubler */
clrsetbits_le32(&hdmi->pll_ctrl, SUNXI_HDMI_PLL_CTRL_DIV_MASK,
SUNXI_HDMI_PLL_CTRL_DIV(clk_div));
if (!clk_double)
setbits_le32(&hdmi->pad_ctrl1, SUNXI_HDMI_PAD_CTRL1_HALVE);
/* Setup timing registers */
writel(SUNXI_HDMI_Y(mode->yres) | SUNXI_HDMI_X(mode->xres),
&hdmi->video_size);
x = mode->hsync_len + mode->left_margin;
y = mode->vsync_len + mode->upper_margin;
writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_bp);
x = mode->right_margin;
y = mode->lower_margin;
writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_fp);
x = mode->hsync_len;
y = mode->vsync_len;
writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_spw);
if (mode->sync & FB_SYNC_HOR_HIGH_ACT)
setbits_le32(&hdmi->video_polarity, SUNXI_HDMI_VIDEO_POL_HOR);
if (mode->sync & FB_SYNC_VERT_HIGH_ACT)
setbits_le32(&hdmi->video_polarity, SUNXI_HDMI_VIDEO_POL_VER);
}
static void sunxi_hdmi_enable(void)
{
struct sunxi_hdmi_reg * const hdmi =
(struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
udelay(100);
setbits_le32(&hdmi->video_ctrl, SUNXI_HDMI_VIDEO_CTRL_ENABLE);
}
#endif /* CONFIG_VIDEO_HDMI */
#if defined CONFIG_VIDEO_VGA || defined CONFIG_VIDEO_COMPOSITE
static void sunxi_tvencoder_mode_set(void)
{
struct sunxi_ccm_reg * const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
struct sunxi_tve_reg * const tve =
(struct sunxi_tve_reg *)SUNXI_TVE0_BASE;
/* Reset off */
setbits_le32(&ccm->lcd0_ch0_clk_cfg, CCM_LCD_CH0_CTRL_TVE_RST);
/* Clock on */
setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_TVE0);
switch (sunxi_display.monitor) {
case sunxi_monitor_vga:
tvencoder_mode_set(tve, tve_mode_vga);
break;
case sunxi_monitor_composite_pal_nc:
tvencoder_mode_set(tve, tve_mode_composite_pal_nc);
break;
case sunxi_monitor_composite_pal:
tvencoder_mode_set(tve, tve_mode_composite_pal);
break;
case sunxi_monitor_composite_pal_m:
tvencoder_mode_set(tve, tve_mode_composite_pal_m);
break;
case sunxi_monitor_composite_ntsc:
tvencoder_mode_set(tve, tve_mode_composite_ntsc);
break;
case sunxi_monitor_none:
case sunxi_monitor_dvi:
case sunxi_monitor_hdmi:
case sunxi_monitor_lcd:
break;
}
}
#endif /* CONFIG_VIDEO_VGA || defined CONFIG_VIDEO_COMPOSITE */
static void sunxi_drc_init(void)
{
#ifdef CONFIG_SUNXI_GEN_SUN6I
struct sunxi_ccm_reg * const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
/* On sun6i the drc must be clocked even when in pass-through mode */
#ifdef CONFIG_MACH_SUN8I_A33
setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_SAT);
#endif
setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DRC0);
clock_set_de_mod_clock(&ccm->iep_drc0_clk_cfg, 300000000);
#endif
}
#ifdef CONFIG_VIDEO_VGA_VIA_LCD
static void sunxi_vga_external_dac_enable(void)
{
int pin;
pin = sunxi_name_to_gpio(CONFIG_VIDEO_VGA_EXTERNAL_DAC_EN);
if (pin >= 0) {
gpio_request(pin, "vga_enable");
gpio_direction_output(pin, 1);
}
}
SUNXI_GPA(0), SUNXI_GPA(1), SUNXI_GPA(2), SUNXI_GPA(3), SUNXI_GPA(4), SUNXI_GPA(5), SUNXI_GPA(6), SUNXI_GPA(7), SUNXI_GPA(8), SUNXI_GPA(9), SUNXI_GPA(10), SUNXI_GPA(11), SUNXI_GPA(12), SUNXI_GPA(13), SUNXI_GPA(14), SUNXI_GPA(15), SUNXI_GPA(16), SUNXI_GPA(17), -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, SUNXI_GPB(0), SUNXI_GPB(1), SUNXI_GPB(2), SUNXI_GPB(3), SUNXI_GPB(4), SUNXI_GPB(5), SUNXI_GPB(6), SUNXI_GPB(7), SUNXI_GPB(8), SUNXI_GPB(9), SUNXI_GPB(10), SUNXI_GPB(11), SUNXI_GPB(12), SUNXI_GPB(13), SUNXI_GPB(14), SUNXI_GPB(15), SUNXI_GPB(16), SUNXI_GPB(17), SUNXI_GPB(18), SUNXI_GPB(19), SUNXI_GPB(20), SUNXI_GPB(21), SUNXI_GPB(22), SUNXI_GPB(23), -1, -1, -1, -1, -1, -1, -1, -1, SUNXI_GPC(0), SUNXI_GPC(1), SUNXI_GPC(2), SUNXI_GPC(3), SUNXI_GPC(4), SUNXI_GPC(5), SUNXI_GPC(6), SUNXI_GPC(7), SUNXI_GPC(8), SUNXI_GPC(9), SUNXI_GPC(10), SUNXI_GPC(11), SUNXI_GPC(12), SUNXI_GPC(13), SUNXI_GPC(14), SUNXI_GPC(15), SUNXI_GPC(16), SUNXI_GPC(17), SUNXI_GPC(18), SUNXI_GPC(19), SUNXI_GPC(20), SUNXI_GPC(21), SUNXI_GPC(22), SUNXI_GPC(23), SUNXI_GPC(24), -1, -1, -1, -1, -1, -1, -1, SUNXI_GPD(0), SUNXI_GPD(1), SUNXI_GPD(2), SUNXI_GPD(3), SUNXI_GPD(4), SUNXI_GPD(5), SUNXI_GPD(6), SUNXI_GPD(7), SUNXI_GPD(8), SUNXI_GPD(9), SUNXI_GPD(10), SUNXI_GPD(11), SUNXI_GPD(12), SUNXI_GPD(13), SUNXI_GPD(14), SUNXI_GPD(15), SUNXI_GPD(16), SUNXI_GPD(17), SUNXI_GPD(18), SUNXI_GPD(19), SUNXI_GPD(20), SUNXI_GPD(21), SUNXI_GPD(22), SUNXI_GPD(23), SUNXI_GPD(24), SUNXI_GPD(25), SUNXI_GPD(26), SUNXI_GPD(27), -1, -1, -1, -1, SUNXI_GPE(0), SUNXI_GPE(1), SUNXI_GPE(2), SUNXI_GPE(3), SUNXI_GPE(4), SUNXI_GPE(5), SUNXI_GPE(6), SUNXI_GPE(7), SUNXI_GPE(8), SUNXI_GPE(9), SUNXI_GPE(10), SUNXI_GPE(11), -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, SUNXI_GPF(0), SUNXI_GPF(1), SUNXI_GPF(2), SUNXI_GPF(3), SUNXI_GPF(4), SUNXI_GPF(5), -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, SUNXI_GPG(0), SUNXI_GPG(1), SUNXI_GPG(2), SUNXI_GPG(3), SUNXI_GPG(4), SUNXI_GPG(5), SUNXI_GPG(6), SUNXI_GPG(7), SUNXI_GPG(8), SUNXI_GPG(9), SUNXI_GPG(10), SUNXI_GPG(11), -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, SUNXI_GPH(0), SUNXI_GPH(1), SUNXI_GPH(2), SUNXI_GPH(3), SUNXI_GPH(4), SUNXI_GPH(5),
static void sunxi_lcdc_tcon1_mode_set(const struct ctfb_res_modes *mode,
int *clk_div, int *clk_double,
bool use_portd_hvsync)
{
struct sunxi_lcdc_reg * const lcdc =
(struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
int bp, clk_delay, total, val, yres;
/* Use tcon1 */
clrsetbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_IO_MAP_MASK,
SUNXI_LCDC_CTRL_IO_MAP_TCON1);
clk_delay = sunxi_lcdc_get_clk_delay(mode, 1);
writel(SUNXI_LCDC_TCON1_CTRL_ENABLE |
((mode->vmode == FB_VMODE_INTERLACED) ?
SUNXI_LCDC_TCON1_CTRL_INTERLACE_ENABLE : 0) |
SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(clk_delay), &lcdc->tcon1_ctrl);
yres = mode->yres;
if (mode->vmode == FB_VMODE_INTERLACED)
yres /= 2;
writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(yres),
&lcdc->tcon1_timing_source);
writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(yres),
&lcdc->tcon1_timing_scale);
writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(yres),
&lcdc->tcon1_timing_out);
bp = mode->hsync_len + mode->left_margin;
total = mode->xres + mode->right_margin + bp;
writel(SUNXI_LCDC_TCON1_TIMING_H_TOTAL(total) |
SUNXI_LCDC_TCON1_TIMING_H_BP(bp), &lcdc->tcon1_timing_h);
bp = mode->vsync_len + mode->upper_margin;
total = mode->yres + mode->lower_margin + bp;
if (mode->vmode == FB_VMODE_NONINTERLACED)
total *= 2;
writel(SUNXI_LCDC_TCON1_TIMING_V_TOTAL(total) |
SUNXI_LCDC_TCON1_TIMING_V_BP(bp), &lcdc->tcon1_timing_v);
writel(SUNXI_LCDC_X(mode->hsync_len) | SUNXI_LCDC_Y(mode->vsync_len),
&lcdc->tcon1_timing_sync);
if (use_portd_hvsync) {
sunxi_gpio_set_cfgpin(SUNXI_GPD(26), SUNXI_GPD_LCD0);
sunxi_gpio_set_cfgpin(SUNXI_GPD(27), SUNXI_GPD_LCD0);
val = 0;
if (mode->sync & FB_SYNC_HOR_HIGH_ACT)
val |= SUNXI_LCDC_TCON_HSYNC_MASK;
if (mode->sync & FB_SYNC_VERT_HIGH_ACT)
val |= SUNXI_LCDC_TCON_VSYNC_MASK;
writel(val, &lcdc->tcon1_io_polarity);
clrbits_le32(&lcdc->tcon1_io_tristate,
SUNXI_LCDC_TCON_VSYNC_MASK |
SUNXI_LCDC_TCON_HSYNC_MASK);
}
#ifdef CONFIG_MACH_SUN5I
if (sunxi_is_composite())
clrsetbits_le32(&lcdc->mux_ctrl, SUNXI_LCDC_MUX_CTRL_SRC0_MASK,
SUNXI_LCDC_MUX_CTRL_SRC0(1));
#endif
sunxi_lcdc_pll_set(1, mode->pixclock_khz, clk_div, clk_double);
}
static void sunxi_lcdc_tcon0_mode_set(const struct ctfb_res_modes *mode,
bool for_ext_vga_dac)
{
struct sunxi_lcdc_reg * const lcdc =
(struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
int bp, clk_delay, clk_div, clk_double, pin, total, val;
for (pin = SUNXI_GPD(0); pin <= SUNXI_GPD(27); pin++) {
#ifdef CONFIG_VIDEO_LCD_IF_PARALLEL
sunxi_gpio_set_cfgpin(pin, SUNXI_GPD_LCD0);
#endif
#ifdef CONFIG_VIDEO_LCD_IF_LVDS
sunxi_gpio_set_cfgpin(pin, SUNXI_GPD_LVDS0);
#endif
#ifdef CONFIG_VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
sunxi_gpio_set_drv(pin, 3);
#endif
}
sunxi_lcdc_pll_set(0, mode->pixclock_khz, &clk_div, &clk_double);
/* Use tcon0 */
clrsetbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_IO_MAP_MASK,
SUNXI_LCDC_CTRL_IO_MAP_TCON0);
clk_delay = sunxi_lcdc_get_clk_delay(mode, 0);
writel(SUNXI_LCDC_TCON0_CTRL_ENABLE |
SUNXI_LCDC_TCON0_CTRL_CLK_DELAY(clk_delay), &lcdc->tcon0_ctrl);
writel(SUNXI_LCDC_TCON0_DCLK_ENABLE |
SUNXI_LCDC_TCON0_DCLK_DIV(clk_div), &lcdc->tcon0_dclk);
writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres),
&lcdc->tcon0_timing_active);
bp = mode->hsync_len + mode->left_margin;
total = mode->xres + mode->right_margin + bp;
writel(SUNXI_LCDC_TCON0_TIMING_H_TOTAL(total) |
SUNXI_LCDC_TCON0_TIMING_H_BP(bp), &lcdc->tcon0_timing_h);
bp = mode->vsync_len + mode->upper_margin;
total = mode->yres + mode->lower_margin + bp;
writel(SUNXI_LCDC_TCON0_TIMING_V_TOTAL(total) |
SUNXI_LCDC_TCON0_TIMING_V_BP(bp), &lcdc->tcon0_timing_v);
#ifdef CONFIG_VIDEO_LCD_IF_PARALLEL
writel(SUNXI_LCDC_X(mode->hsync_len) | SUNXI_LCDC_Y(mode->vsync_len),
&lcdc->tcon0_timing_sync);
writel(0, &lcdc->tcon0_hv_intf);
writel(0, &lcdc->tcon0_cpu_intf);
#endif
#ifdef CONFIG_VIDEO_LCD_IF_LVDS
val = (sunxi_display.depth == 18) ? 1 : 0;
writel(SUNXI_LCDC_TCON0_LVDS_INTF_BITWIDTH(val) |
SUNXI_LCDC_TCON0_LVDS_CLK_SEL_TCON0, &lcdc->tcon0_lvds_intf);
#endif
if (sunxi_display.depth == 18 || sunxi_display.depth == 16) {
writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[0]);
writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[1]);
writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[2]);
writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[3]);
writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[4]);
writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[5]);
writel(SUNXI_LCDC_TCON0_FRM_TAB0, &lcdc->tcon0_frm_table[0]);
writel(SUNXI_LCDC_TCON0_FRM_TAB1, &lcdc->tcon0_frm_table[1]);
writel(SUNXI_LCDC_TCON0_FRM_TAB2, &lcdc->tcon0_frm_table[2]);
writel(SUNXI_LCDC_TCON0_FRM_TAB3, &lcdc->tcon0_frm_table[3]);
writel(((sunxi_display.depth == 18) ?
SUNXI_LCDC_TCON0_FRM_CTRL_RGB666 :
SUNXI_LCDC_TCON0_FRM_CTRL_RGB565),
&lcdc->tcon0_frm_ctrl);
}
val = SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE(CONFIG_VIDEO_LCD_DCLK_PHASE);
if (!(mode->sync & FB_SYNC_HOR_HIGH_ACT))
val |= SUNXI_LCDC_TCON_HSYNC_MASK;
if (!(mode->sync & FB_SYNC_VERT_HIGH_ACT))
val |= SUNXI_LCDC_TCON_VSYNC_MASK;
#ifdef CONFIG_VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
if (for_ext_vga_dac)
val = 0;
#endif
writel(val, &lcdc->tcon0_io_polarity);
writel(0, &lcdc->tcon0_io_tristate);
}