SeqRunMode evgSeqRam::getRunMode() const { if(READ32(m_pReg, SeqControl(m_id)) & EVG_SEQ_RAM_SINGLE) return Single; if(READ32(m_pReg, SeqControl(m_id)) & EVG_SEQ_RAM_RECYCLE) return Auto; else return Normal; }
void evgSeqRam::enable() { if(isAllocated()) { BITSET32(m_pReg, SeqControl(m_id), EVG_SEQ_RAM_ARM); } else throw std::runtime_error("Trying to enable Unallocated seqRam"); }
void evgSeqRam::setRunMode(SeqRunMode mode) { switch (mode) { case(Normal): BITCLR32(m_pReg, SeqControl(m_id), EVG_SEQ_RAM_SINGLE); BITCLR32(m_pReg, SeqControl(m_id), EVG_SEQ_RAM_RECYCLE); break; case(Auto): BITCLR32(m_pReg, SeqControl(m_id), EVG_SEQ_RAM_SINGLE); BITSET32(m_pReg, SeqControl(m_id), EVG_SEQ_RAM_RECYCLE); break; case(Single): BITSET32(m_pReg, SeqControl(m_id), EVG_SEQ_RAM_SINGLE); break; default: throw std::runtime_error("Unknown SeqRam RunMode"); } }
void evgSeqRam::softTrig() { BITSET32(m_pReg, SeqControl(m_id), EVG_SEQ_RAM_SW_TRIG); }
bool evgSeqRam::isRunning() const { return READ32(m_pReg, SeqControl(m_id)) & EVG_SEQ_RAM_RUNNING; }
bool evgSeqRam::isEnabled() const { return READ32(m_pReg, SeqControl(m_id)) & EVG_SEQ_RAM_ENABLED; }
void evgSeqRam::reset() { BITSET32(m_pReg, SeqControl(m_id), EVG_SEQ_RAM_RESET); }
void evgSeqRam::disable() { BITSET32(m_pReg, SeqControl(m_id), EVG_SEQ_RAM_DISABLE); }
REGINFO("Status", Status, 32), REGINFO("Control", Control, 32), REGINFO("IrqFlag", IrqFlag, 32), REGINFO("IrqEnable", IrqEnable, 32), REGINFO("AcTrigControl", AcTrigControl, 32), REGINFO("AcTrigEvtMap", AcTrigEvtMap, 8), REGINFO("SwEventControl", SwEventControl, 8), REGINFO("SwEventCode", SwEventCode, 8), REGINFO("DataTxCtrlEvg", DataTxCtrlEvg, 32), REGINFO("DBusSrc", DBusSrc, 32), REGINFO("FPGAVersion", FWVersion, 32), REGINFO("uSecDiv", uSecDiv, 16), REGINFO("ClockSource", ClockSource, 8), REGINFO("RfDiv", RfDiv, 8), REGINFO("ClockStatus", ClockStatus, 16), REGINFO("SeqControl(0)", SeqControl(0), 32), REGINFO("SeqControl(1)", SeqControl(1), 32), REGINFO("FracSynthWord", FracSynthWord, 32), REGINFO("TrigEventCtrl(0)", TrigEventCtrl(0), 32), REGINFO("TrigEventCtrl(1)", TrigEventCtrl(1), 32), REGINFO("TrigEventCtrl(2)", TrigEventCtrl(2), 32), REGINFO("TrigEventCtrl(3)", TrigEventCtrl(3), 32), REGINFO("TrigEventCtrl(4)", TrigEventCtrl(4), 32), REGINFO("TrigEventCtrl(5)", TrigEventCtrl(5), 32), REGINFO("TrigEventCtrl(6)", TrigEventCtrl(6), 32), REGINFO("TrigEventCtrl(7)", TrigEventCtrl(7), 32), REGINFO("MuxControl(0)", MuxControl(0), 32), REGINFO("MuxPrescaler(0)", MuxPrescaler(0), 32), REGINFO("MuxControl(1)", MuxControl(1), 32), REGINFO("MuxPrescaler(1)", MuxPrescaler(1), 32), REGINFO("MuxControl(2)", MuxControl(2), 32),