void nvds_read_bdaddr_from_otp()
{
const uint16_t BDADDR_OFFSET = 0x7fd4; // offset of BD address in OTP header
uint8_t *otp_bdaddr;
if (!APP_BOOT_FROM_OTP)
{
int cnt = 100000;
#define XPMC_MODE_MREAD 0x1
otp_bdaddr = (uint8_t *)0x40000 + BDADDR_OFFSET; //where in OTP header is BDADDR
SetBits16(CLK_AMBA_REG, OTP_ENABLE, 1); // enable OTP clock
while ((GetWord16(ANA_STATUS_REG) & LDO_OTP_OK) != LDO_OTP_OK && cnt--)
/* Just wait */;
// set OTP in read mode
SetWord32(OTPC_MODE_REG, XPMC_MODE_MREAD);
}
else
otp_bdaddr = (uint8_t *)0x20000000 + BDADDR_OFFSET; //where in OTP header is BDADDR
#if BLE_JWAOO_TOY_SERVER
memcpy(jwaoo_toy_device_data.bd_addr, otp_bdaddr, sizeof(jwaoo_toy_device_data.bd_addr));
#else
memcpy(&dev_bdaddr, otp_bdaddr, sizeof(dev_bdaddr));
#endif
SetBits16(CLK_AMBA_REG, OTP_ENABLE, 0); //disable OTP clock
}
/**
****************************************************************************************
* @brief Enable pad's and peripheral clocks assuming that peripherals' power domain is down. The Uart and SPi clocks are set.
*
* @return void
****************************************************************************************
*/
void periph_init(void) // set i2c, spi, uart, uart2 serial clks
{
// Power up peripherals' power domain
SetBits16(PMU_CTRL_REG, PERIPH_SLEEP, 0);
while (!(GetWord16(SYS_STAT_REG) & PER_IS_UP)) ;
SetBits16(CLK_16M_REG,XTAL16_BIAS_SH_DISABLE, 1);
//rom patch
patch_func();
//Init pads
set_pad_functions();
#if (BLE_APP_PRESENT)
#if BLE_PROX_MONITOR
app_proxm_port_reinit(XCY_LED0_GPIO);
app_button_enable();
#elif BLE_FINDME_LOCATOR
app_button_enable();
#endif //BLE_PROX_REPORTER
#if BLE_BATTERY_SERVER
app_batt_port_reinit();
#endif //BLE_BATTERY_SERVER
#endif //BLE_APP_PRESENT
// Enable the pads
SetBits16(SYS_CTRL_REG, PAD_LATCH_EN, 1);
}
/**
****************************************************************************************
* @brief Function to set the interrupt generated by the GPIO pin
*
* @param[in] port GPIO port
* @param[in] pin GPIO pin
* @param[in] irq GPIO IRQ
* @param[in] low_input TRUE generates an IRQ if the input is low
* @param[in] release_wait TRUE waits for key release after interrupt was reset
* @param[in] debounce_ms duration of a debounce sequence before an IRQ is generated
*
* @return void
****************************************************************************************
*/
void GPIO_EnableIRQ( GPIO_PORT port, GPIO_PIN pin, IRQn_Type irq, bool low_input,
bool release_wait, uint8_t debounce_ms )
{
#if DEVELOPMENT_DEBUG
#ifndef GPIO_DRV_PIN_ALLOC_MON_DISABLED
if ( !(GPIO_status & ( ((uint64_t)1 << pin) << (port * 16) )) )
__asm("BKPT #0\n"); // this pin has not been previously reserved!
#endif //GPIO_DRV_PIN_ALLOC_MON_DISABLED
#endif //DEVELOPMENT_DEBUG
const uint8_t KBRD_IRQn_SEL_BASE[] = {
1,
9,
15,
25
};
SetBits16(GPIO_DEBOUNCE_REG, (DEB_ENABLE0 << (irq-GPIO0_IRQn)), (debounce_ms > 0) );
SetBits16(GPIO_DEBOUNCE_REG, DEB_VALUE, debounce_ms);
SetBits16(GPIO_INT_LEVEL_CTRL_REG, EDGE_LEVELn0 << (irq-GPIO0_IRQn), release_wait);
SetBits16(GPIO_INT_LEVEL_CTRL_REG, INPUT_LEVEL0 << (irq-GPIO0_IRQn), low_input);
SetBits16(GPIO_IRQ0_IN_SEL_REG + 2*(irq-GPIO0_IRQn), KBRD_IRQn_SEL, KBRD_IRQn_SEL_BASE[port] + pin);
NVIC_SetPriority(irq, 2);
NVIC_EnableIRQ(irq);
}
void iq_trim_from_otp()
{
#ifdef IQTRIM_FROM_OTP
#ifndef APP_BOOT_FROM_OTP
int cnt=100000;
#define XPMC_MODE_MREAD 0x1
uint16_t *iqtrim = (uint16_t *)(0x40000 + IQTRIM_FROM_OTP); //where in OTP header is IQ_Trim
SetBits16(CLK_AMBA_REG, OTP_ENABLE, 1); // enable OTP clock
while ((GetWord16(ANA_STATUS_REG) & LDO_OTP_OK) != LDO_OTP_OK && cnt--)
/* Just wait */;
// set OTP in read mode
SetWord32 (OTPC_MODE_REG,XPMC_MODE_MREAD);
#else
uint16_t *iqtrim = (uint16_t *)(0x20000000 + IQTRIM_FROM_OTP); //where in OTP header is IQ_Trim
#endif
iq_trim_bias_ctrl1_reg = *iqtrim++;
iq_trim_rf_mixer_ctrl1_reg = *iqtrim;
SetBits16(CLK_AMBA_REG, OTP_ENABLE, 0); //disable OTP clock
#ifdef SUPPORT_1_8_V
SetBits16(DCDC_CTRL2_REG, DCDC_VBAT3V_LEV, 0x0); ///--Support 1.8V boot
#endif
#endif
}
void nvds_read_bdaddr_from_otp()
{
#ifdef BDADDR_FROM_OTP
#ifndef APP_BOOT_FROM_OTP
int cnt=100000;
#define XPMC_MODE_MREAD 0x1
uint8_t *otp_bdaddr = (uint8_t *)0x40000 + BDADDR_FROM_OTP; //where in OTP header is BDADDR
SetBits16(CLK_AMBA_REG, OTP_ENABLE, 1); // enable OTP clock
while ((GetWord16(ANA_STATUS_REG) & LDO_OTP_OK) != LDO_OTP_OK && cnt--)
/* Just wait */;
// set OTP in read mode
SetWord32 (OTPC_MODE_REG,XPMC_MODE_MREAD);
#else
uint8_t *otp_bdaddr = (uint8_t *)0x20000000 + BDADDR_FROM_OTP; //where in OTP header is BDADDR
#endif
memcpy(&dev_bdaddr, otp_bdaddr, sizeof(dev_bdaddr));
SetBits16(CLK_AMBA_REG, OTP_ENABLE, 0); //disable OTP clock
#ifdef SUPPORT_1_8_V
SetBits16(DCDC_CTRL2_REG, DCDC_VBAT3V_LEV, 0x0); ///--Support 1.8V boot
#endif
#endif
}
/*
* Init TX and RX buffers, they are in EM but not in the retainable part
* so the pointers have to be programmed again *
*/
if(func_check_mem_flag)
{
//init TX/RX buffers after DEEPSLEEP
co_buf_init_deep_sleep();
// Set the first RX descriptor pointer into the HW
ble_currentrxdescptr_set(REG_BLE_EM_RX_ADDR_GET(co_buf_rx_current_get()));
//INIT NONE RET. HEAP after DEEPSLEEP
ke_mem_init(KE_MEM_NON_RETENTION, (uint8_t*)(jump_table_struct[rwip_heap_non_ret_pos]), jump_table_struct[rwip_heap_non_ret_size]);
func_check_mem_flag = false;
}
#endif //RW_BLE_SUPPORT
#endif //DEEP_SLEEP
}
// /*********************************************************************************
// *** SLP_INT ISR
// ***/
void BLE_SLP_Handler(void)
//void BLE_SLP_Handler_func(void)
{
ble_regs_pop();
//smpc_regs_pop();
#if !DEEP_SLEEP_ENABLED
# if DEVELOPMENT__NO_OTP
SetBits16(SYS_CTRL_REG, DEBUGGER_ENABLE, 1);
# endif // DEVELOPMENT__NO_OTP
#endif // !DEEP_SLEEP_ENABLED
SetBits16(GP_CONTROL_REG, BLE_WAKEUP_REQ, 0); //just to be sure, kostas ninos
if(jump_table_struct[0] == TASK_GTL)
{
// UART and pads have already been activated by periph_init() which is called
// at initialization by main_func() and during wakeup by BLE_WAKEUP_LP_Handler().
gtl_eif_init();
}
SetBits32(BLE_INTACK_REG, SLPINTACK, 1);
#if DEEP_SLEEP //Needed only for compilation. Remove when ROM code is ready.
#if RW_BLE_SUPPORT
rwip_wakeup();
#endif //RW_BLE_SUPPORT
#endif //DEEP_SLEEP
}
/**
****************************************************************************************
* @brief Read low power clock selection from
*
* The Hclk and Pclk are set
****************************************************************************************
*/
void select_lp_clk()
{
#if (CFG_LP_CLK == LP_CLK_FROM_OTP)
int cnt = 100000;
# ifndef APP_BOOT_FROM_OTP
#define XPMC_MODE_MREAD 0x1
uint16_t *lp_clk = (uint16_t *)(0x40000 + LP_CLK_OTP_OFFSET); //where in OTP header is IQ_Trim
SetBits16(CLK_AMBA_REG, OTP_ENABLE, 1); //enable OTP clock
while ((GetWord16(ANA_STATUS_REG) & LDO_OTP_OK) != LDO_OTP_OK && cnt--)
/* Just wait */;
// set OTP in read mode
SetWord32(OTPC_MODE_REG, XPMC_MODE_MREAD);
# else
uint16_t *lp_clk = (uint16_t *)(0x20000000 + LP_CLK_OTP_OFFSET); //where in OTP header is IQ_Trim
# endif //APP_BOOT_FROM_OTP
lp_clk_sel = (*lp_clk);
SetBits16(CLK_AMBA_REG, OTP_ENABLE, 0); //disable OTP clock
#else //CFG_LP_CLK
lp_clk_sel = CFG_LP_CLK;
#endif
}
/**
****************************************************************************************
* @brief Enable pad's and peripheral clocks assuming that peripherals' power domain is down. The Uart and SPi clocks are set.
*
* @return void
****************************************************************************************
*/
void periph_init(void)
{
// Power up peripherals' power domain
SetBits16(PMU_CTRL_REG, PERIPH_SLEEP, 0);
while (!(GetWord16(SYS_STAT_REG) & PER_IS_UP)) ;
#if ES4_CODE
SetBits16(CLK_16M_REG,XTAL16_BIAS_SH_DISABLE, 1);
#endif
//rom patch
patch_func();
//Init pads
set_pad_functions();
#if (BLE_APP_PRESENT)
/*
* (Re)Initialize peripherals
i.e.
uart_init(UART_BAUDRATE_115K2, 3);
*/
#endif
// Enable the pads
SetBits16(SYS_CTRL_REG, PAD_LATCH_EN, 1);
}
/**
****************************************************************************************
* @brief Starts RCX20 calibration.
*
* @param[in] cal_time. Calibration time in RCX20 cycles.
*
* @return void
****************************************************************************************
*/
void calibrate_rcx20(uint16_t cal_time)
{
SetWord16(CLK_REF_CNT_REG, cal_time);
SetBits16(CLK_REF_SEL_REG, REF_CLK_SEL, 0x3); //RCX select
SetBits16(CLK_REF_SEL_REG, REF_CAL_START, 0x1); //Start Calibration
cal_enable = 1;
}
/**
****************************************************************************************
* @brief Deactivate communication with the 3-wire SPI
****************************************************************************************
*/
void deactivate_3wire_spi(void)
{
GPIO_SetActive(cs.port, cs.pin); // leave CS high
GPIO_SetPinFunction( sdio.port, sdio.pin, INPUT, PID_SPI_DI);
NVIC_DisableIRQ(SPI_IRQn); // disable SPI interrupt
SetBits16(SPI_CTRL_REG, SPI_ON, 0); // close SPI block, if opened
SetBits16(CLK_PER_REG, SPI_ENABLE, 0); // disable clock for SPI
}
/**
****************************************************************************************
* @brief
*
* @param[in]
*
* @return
****************************************************************************************
*/
void quad_decoder_enable_irq(uint8_t event_count)
{
SetBits16(QDEC_CTRL_REG, QD_IRQ_CLR, 1); // clear any garbagge
NVIC_ClearPendingIRQ(WKUP_QUADEC_IRQn); // clear it to be on the safe side...
SetBits16(QDEC_CTRL_REG, QD_IRQ_THRES, event_count); // Set event counter
SetBits16(QDEC_CTRL_REG, QD_IRQ_MASK, 1); // interrupt not masked
NVIC_EnableIRQ(WKUP_QUADEC_IRQn); // enable the WKUP_QUADEC_IRQn
}
/**
****************************************************************************************
* @brief Starts RCX20 calibration.
*
* @param[in] cal_time. Calibration time in RCX20 cycles.
*
* @return void
****************************************************************************************
*/
void calibrate_rcx20(uint16_t cal_time)
{
if ((CFG_LP_CLK == LP_CLK_FROM_OTP) || (CFG_LP_CLK == LP_CLK_RCX20))
{
SetWord16(CLK_REF_CNT_REG, cal_time);
SetBits16(CLK_REF_SEL_REG, REF_CLK_SEL, 0x3); //RCX select
SetBits16(CLK_REF_SEL_REG, REF_CAL_START, 0x1); //Start Calibration
cal_enable = 1;
}
}
/**
****************************************************************************************
* @brief Initialize communication with the 3-wire SPI
* @param[in] spi_sdio_pin_register: Size of the data to be read
* @param[in] TsradCounterToSet: Counter for the delay between Address and Data phase in reading
*
****************************************************************************************
*/
void initialize_3wire_spi(struct SPI_Config *cfg, bool enable_interrupt, uint16_t TsradCounterToSet)
{
sdio.port = cfg->sdio.port; // initialize with param data;
sdio.pin = cfg->sdio.pin;
cs.port = cfg->cs.port;
cs.pin = cfg->cs.pin;
//configure pins
GPIO_ConfigurePin( cfg->cs.port, cfg->cs.pin, OUTPUT, PID_SPI_EN, true);
GPIO_SetPinFunction( cfg->sdio.port, cfg->sdio.pin, INPUT, PID_SPI_DI);
GPIO_SetPinFunction( cfg->clk.port, cfg->clk.pin, OUTPUT, PID_SPI_CLK);
TsradCounter = TsradCounterToSet; // SPI read address-data delay (refer to sensor datasheet)
// init SPI
SetBits16(CLK_PER_REG, SPI_ENABLE, 1); // enable clock for SPI
SetBits16(SPI_CTRL_REG,SPI_ON,0); // close SPI block, if opened
SetBits16(SPI_CTRL_REG,SPI_WORD, cfg->SPI_Word_Mode); // SPI word mode
SetBits16(SPI_CTRL_REG,SPI_SMN, cfg->SPI_Role); // SPI master mode
SetBits16(SPI_CTRL_REG,SPI_POL, cfg->SPI_Polarity_Mode); // SPI mode selection - polarity
SetBits16(SPI_CTRL_REG,SPI_PHA, cfg->SPI_PHA_Mode); // SPI mode selection - phase
SetBits16(SPI_CTRL_REG,SPI_MINT, cfg->SPI_MINT_Mode); // disable SPI interrupt to the ICU
SetBits16(SPI_CTRL_REG,SPI_CLK, cfg->SPI_XTAL_Freq); // SPI block clock divider
SetBits16(SPI_CTRL_REG,SPI_ON, 1); // enable SPI block
if (enable_interrupt)
NVIC_EnableIRQ(SPI_IRQn); // enable SPI interrupt, if MINT is '1' and enable_interrupt is set
}
void uart_initialization(void)
{
SetBits16(CLK_PER_REG, UART1_ENABLE, 1); // enable clock for UART 1
SetWord16(UART_LCR_REG, 0x80); // set bit to access DLH and DLL register
SetWord16(UART_IER_DLH_REG,(UART_BAUDRATE_115K2&0xFF>>8));//set high byte
SetWord16(UART_RBR_THR_DLL_REG,UART_BAUDRATE_115K2&0xFF);//set low byte
SetWord16(UART_LCR_REG,UART_DATALENGTH|UART_PARITY|UART_STOPBITS);
SetBits16(UART_MCR_REG, UART_SIRE, 0); // mode 0 for normal , 1 for IRDA
SetWord16(UART_IIR_FCR_REG,1); // enable fifo
SetBits16(UART_IER_DLH_REG,ERBFI_dlh0,0); // IER access, disable interrupt for available data
}
/**
****************************************************************************************
* @brief Initialize I2C controller as a master for EEPROM handling.
****************************************************************************************
*/
void i2c_eeprom_init(uint16_t dev_address, uint8_t speed, uint8_t address_mode, uint8_t address_size)
{
mem_address_size = address_size;
SetBits16(CLK_PER_REG, I2C_ENABLE, 1); // enable clock for I2C
SetWord16(I2C_ENABLE_REG, 0x0); // Disable the I2C controller
SetWord16(I2C_CON_REG, I2C_MASTER_MODE | I2C_SLAVE_DISABLE | I2C_RESTART_EN); // Slave is disabled
SetBits16(I2C_CON_REG, I2C_SPEED, speed); // Set speed
SetBits16(I2C_CON_REG, I2C_10BITADDR_MASTER, address_mode); // Set addressing mode
SetWord16(I2C_TAR_REG, dev_address & 0x3FF); // Set Slave device address
SetWord16(I2C_ENABLE_REG, 0x1); // Enable the I2C controller
while( (GetWord16(I2C_STATUS_REG) & 0x20) != 0 ); // Wait for I2C master FSM to be IDLE
i2c_dev_address = dev_address;
}
void NMI_HandlerC(unsigned long *hardfault_args)
{
// Reached this point due to a WDOG timeout
SetBits16(PMU_CTRL_REG, RADIO_SLEEP, 1); // turn off radio PD
SetBits16(PMU_CTRL_REG, PERIPH_SLEEP, 1); // turn off peripheral power domain
SetBits16(CLK_RADIO_REG, BLE_LP_RESET, 1); // reset the BLE LP timer
NVIC_ClearPendingIRQ(BLE_WAKEUP_LP_IRQn); // clear any pending LP IRQs
#if (DEVELOPMENT_DEBUG)
SetWord16(SET_FREEZE_REG, FRZ_WDOG); // Stop WDOG
SetBits16(SYS_CTRL_REG, DEBUGGER_ENABLE, 1); // enable debugger to be able to re-attach
*(volatile unsigned long *)(STATUS_BASE ) = hardfault_args[0]; // R0
*(volatile unsigned long *)(STATUS_BASE + 0x04) = hardfault_args[1]; // R1
*(volatile unsigned long *)(STATUS_BASE + 0x08) = hardfault_args[2]; // R2
*(volatile unsigned long *)(STATUS_BASE + 0x0C) = hardfault_args[3]; // R3
*(volatile unsigned long *)(STATUS_BASE + 0x10) = hardfault_args[4]; // R12
*(volatile unsigned long *)(STATUS_BASE + 0x14) = hardfault_args[5]; // LR
*(volatile unsigned long *)(STATUS_BASE + 0x18) = hardfault_args[6]; // PC
*(volatile unsigned long *)(STATUS_BASE + 0x1C) = hardfault_args[7]; // PSR
*(volatile unsigned long *)(STATUS_BASE + 0x20) = (*((volatile unsigned long *)(0xE000ED28))); // CFSR
*(volatile unsigned long *)(STATUS_BASE + 0x24) = (*((volatile unsigned long *)(0xE000ED2C))); // HFSR
*(volatile unsigned long *)(STATUS_BASE + 0x28) = (*((volatile unsigned long *)(0xE000ED30))); // DFSR
*(volatile unsigned long *)(STATUS_BASE + 0x2C) = (*((volatile unsigned long *)(0xE000ED3C))); // AFSR
*(volatile unsigned long *)(STATUS_BASE + 0x30) = (*((volatile unsigned long *)(0xE000ED34))); // MMAR
*(volatile unsigned long *)(STATUS_BASE + 0x34) = (*((volatile unsigned long *)(0xE000ED38))); // BFAR
if ((GetWord16(SYS_STAT_REG) & DBG_IS_UP) == DBG_IS_UP)
// __asm("BKPT #0\n");
BKPT();
else
{
while(1);
}
#else // DEVELOPMENT_DEBUG
# ifdef PRODUCTION_DEBUG_OUTPUT
// Power up peripherals' power domain
SetBits16(PMU_CTRL_REG, PERIPH_SLEEP, 0);
while (!(GetWord16(SYS_STAT_REG) & PER_IS_UP));
dbg_prod_output(0, hardfault_args);
# endif
// Remap addres 0x00 to ROM and force execution
SetWord16(SYS_CTRL_REG, (GetWord16(SYS_CTRL_REG) & ~REMAP_ADR0) | SW_RESET );
#endif // DEVELOPMENT_DEBUG
}
/**
****************************************************************************************
* @brief Enable pad's and peripheral clocks assuming that peripherals' power domain is down.
* The Uart and SPi clocks are set.
*
****************************************************************************************
*/
void periph_init(void) // set i2c, spi, uart, uart2 serial clks
{
// system init
SetWord16(CLK_AMBA_REG, 0x00); // set clocks (hclk and pclk ) 16MHz
SetWord16(SET_FREEZE_REG,FRZ_WDOG); // stop watch dog
SetBits16(SYS_CTRL_REG,PAD_LATCH_EN,1); // open pads
SetBits16(SYS_CTRL_REG,DEBUGGER_ENABLE,1); // open debugger
SetBits16(PMU_CTRL_REG, PERIPH_SLEEP,0); // exit peripheral power down
// Power up peripherals' power domain
SetBits16(PMU_CTRL_REG, PERIPH_SLEEP, 0);
while (!(GetWord16(SYS_STAT_REG) & PER_IS_UP));
// Initialize UART component
//Init pads
}
void Uart_init(void)
{
SetBits16(CLK_PER_REG, UART1_ENABLE, 1); // enable clock for UART 1
SetWord16(UART_LCR_REG, 0x80); // set bit to access DLH and DLL register
SetWord16(UART_IER_DLH_REG,(UART_BAUDRATE_115K2&0xFF>>8));//set high byte
SetWord16(UART_RBR_THR_DLL_REG,UART_BAUDRATE_115K2&0xFF);//set low byte
SetWord16(UART_LCR_REG,UART_DATALENGTH_8|UART_PARITY_NONE|UART_STOPBITS_1);
SetBits16(UART_MCR_REG, UART_SIRE, 0); // mode 0 for normal , 1 for IRDA
SetWord16(UART_IIR_FCR_REG,1); // enable fifo
SetBits16(UART_IER_DLH_REG,ERBFI_dlh0,1); // IER access, disable interrupt for available data
NVIC_SetPriority(UART_IRQn,1);
NVIC_EnableIRQ(UART_IRQn);
}
/**
****************************************************************************************
* @brief Sets the XTAL16M trim value.
*
* @param[in] trim_value Trim value.
*
* @return void
****************************************************************************************
*/
void set_xtal16m_trim_value(uint16_t trim_value)
{
SetBits16(CLK_16M_REG, RC16M_ENABLE, 1); // enable RC 16MHz
for (volatile int i = 0; i < 20; i++);
SetBits16(CLK_CTRL_REG, SYS_CLK_SEL, 1); // switch to RC16
while( (GetWord16(CLK_CTRL_REG) & RUNNING_AT_RC16M) == 0 ); // wait for actual switch
SetBits16(CLK_CTRL_REG, XTAL16M_DISABLE, 1); // disable XTAL16
SetWord16(CLK_FREQ_TRIM_REG, trim_value); // set default trim value
SetBits16(CLK_CTRL_REG, XTAL16M_DISABLE, 0); // enable XTAL16
while( (GetWord16(SYS_STAT_REG) & XTAL16_SETTLED) == 0 ); // wait for XTAL16 settle
SetBits16(CLK_CTRL_REG , SYS_CLK_SEL ,0); // switch to XTAL16
while( (GetWord16(CLK_CTRL_REG) & RUNNING_AT_XTAL16M) == 0 ); // wait for actual switch
}
/**
****************************************************************************************
* @brief otp_prepare()
*
* About: Prepare OTP Controller in order to be able to reload SysRAM at the next power-up
****************************************************************************************
*/
static __inline void otp_prepare(uint32 code_size)
{
// Enable OPTC clock in order to have access
SetBits16 (CLK_AMBA_REG, OTP_ENABLE, 1);
// Wait a little bit to start the OTP clock...
for(uint8 i=0;i<10;i++); //change this later to a defined time
SetBits16(SYS_CTRL_REG, OTP_COPY, 1);
// Copy the size of software from the first word of the retaintion mem.
SetWord32 (OTPC_NWORDS_REG, code_size - 1);
// And close the OPTC clock to save power
SetBits16 (CLK_AMBA_REG, OTP_ENABLE, 0);
}
static void uart_rec_error_isr(void)
{
void (*callback) (uint8_t) = NULL;
// Reset RX parameters
uart_env.rx.size = 0;
uart_env.rx.bufptr = NULL;
// Disable RX interrupt
SetBits16(UART_IER_DLH_REG, ERBFI_dlh0, 0); // uart_rec_data_avail_setf(0);
// Reset RX FIFO
// uart_rxfifo_res_setf(1); @WIK commented
// Retrieve callback pointer
callback = uart_env.rx.callback;
if(callback != NULL)
{
// Clear callback pointer
uart_env.rx.callback = NULL;
// Call handler
callback(UART_STATUS_ERROR);
}
else
{
ASSERT_ERR(0);
}
}
static void uart_sps_rec_error_isr(void)
{
void (*callback) (uint8_t, uint32_t) = NULL;
// Reset RX parameters
uart_sps_env.rx.size = 0;
uart_sps_env.rx.bufptr = NULL;
// Disable RX interrupt
SetBits16(UART_IER_DLH_REG, ERBFI_dlh0, 0);
// Retrieve callback pointer
callback = uart_sps_env.rx.callback;
if(callback != NULL)
{
// Clear callback pointer
uart_sps_env.rx.callback = NULL;
// Call handler
callback(UART_STATUS_ERROR, NULL);
}
else
{
ASSERT_ERR(0);
}
}
/**
****************************************************************************************
* @brief Checks if system is in startup phase.
* @return uint8 1 if system is in startup phase, otherwise 0.
****************************************************************************************
*/
uint8_t check_sys_startup_period(void)
{
uint8_t ret_value = 0;
if (sys_startup_flag)
{
uint32_t current_time;
current_time = lld_evt_time_get();
if (current_time < startup_sleep_delay) // startup_sleep_delay after system startup to allow system to sleep
ret_value = 1;
else // After 2 seconds system can sleep
{
sys_startup_flag = false;
if ( (app_get_sleep_mode() == 2) || (app_get_sleep_mode() == 1) )
{
SetWord16(SET_FREEZE_REG, FRZ_WDOG); // Stop WDOG until debugger is removed
while ((GetWord16(SYS_STAT_REG) & DBG_IS_UP) == DBG_IS_UP) {};
SetBits16(SYS_CTRL_REG, DEBUGGER_ENABLE, 0); // close debugger
}
#if (USE_WDOG)
SetWord16(RESET_FREEZE_REG, FRZ_WDOG); // Start WDOG
#endif
ret_value = 0;
}
}
return ret_value;
}
/**
****************************************************************************************
* @brief Enable pad's and peripheral clocks assuming that peripherals' power domain is down.
*
* The Uart and SPi clocks are set.
****************************************************************************************
*/
void periph_init(void) // set i2c, spi, uart, uart2 serial clks
{
// Power up peripherals' power domain
SetBits16(PMU_CTRL_REG, PERIPH_SLEEP, 0);
while (!(GetWord16(SYS_STAT_REG) & PER_IS_UP)) ;
// TODO: Application specific - Modify accordingly!
// Example: Activate UART and SPI.
// Initialize UART component
#ifdef PROGRAM_ENABLE_UART
SetBits16(CLK_PER_REG, UART1_ENABLE, 1); // enable clock - always @16MHz
// baudr=9-> 115k2
// mode=3-> no parity, 1 stop bit 8 data length
#ifdef UART_MEGABIT
uart_init(UART_BAUDRATE_1M, 3);
#else
uart_init(UART_BAUDRATE_115K2, 3);
#endif // UART_MEGABIT
//NVIC_SetPriority(UART_IRQn, 1);
#endif // PROGRAM_ENABLE_UART
#if 0
//Example: Do something with the timer if need be...
SetWord16(TIMER0_CTRL_REG, 0);
SetWord16(TIMER0_RELOAD_M_REG, 0);
SetWord16(TIMER0_RELOAD_N_REG, 0);
SetWord16(TIMER0_ON_REG, 0);
#endif
//rom patch
patch_func();
//Init pads
set_pad_functions();
#if (BLE_APP_PRESENT)
#if BLE_BATTERY_SERVER
app_batt_port_reinit();
#endif //BLE_BATTERY_SERVER
#endif //BLE_APP_PRESENT
// Enable the pads
SetBits16(SYS_CTRL_REG, PAD_LATCH_EN, 1);
}
/**
****************************************************************************************
* @brief
*
* @param[in]
*
* @return
****************************************************************************************
*/
void quad_decoder_release(void)
{
// Reset Quadrature Decoder pin assignment (PLEASE REVIEW)
SetWord16(QDEC_CTRL2_REG, QUAD_DEC_CHXA_NONE_AND_CHXB_NONE | QUAD_DEC_CHYA_NONE_AND_CHYB_NONE | QUAD_DEC_CHZA_NONE_AND_CHZB_NONE);
// Disable the Quadrature clock
SetBits16(CLK_PER_REG, QUAD_ENABLE , false);
}
/**
****************************************************************************************
* @brief Start or Restart the 439 SPI to get it ready for fetching Audio Data
*
* @return void
****************************************************************************************
*/
void spi_439_codec_restart(void)
{
/* disable interrupts, and use 16 bits transfers.. */
SetBits16(SPI_CTRL_REG, SPI_MINT, SPI_MINT_DISABLE);
SetBits16(SPI_CTRL_REG, SPI_WORD, SPI_MODE_16BIT );
spi_cs_high();
SetWord439(SC14439_DMA0_CTRL_REG,0x0E2C); // Disable, SYNC_SEL=0, DREQ_LEVEL=1,CIRUCLAR=1., AINC=10,BINC=00 DREQ_MODE=1, RSRV, IND=1, DIR=1, RSRVD, DMA_ON=0 = 0.1110.0010.1100
SetWord439(SC14439_DMA0_A_IDX_REG,20);
SetWord439(SC14439_DMA0_CTRL_REG,0x062D); // Enable, SYNC_SEL=0, DREQ_LEVEL=0,CIRUCLAR=1., AINC=10,BINC=00 DREQ_MODE=1, RSRV, IND=1, DIR=1, RSRVD, DMA_ON=1 = 0.0110.0010.1101
/* Now enable interupts, use 32 bits and pull enable low */
SetBits16(SPI_CTRL_REG, SPI_MINT, SPI_MINT_ENABLE);
SetBits16(SPI_CTRL_REG, SPI_WORD, SPI_MODE_32BIT );
spi_cs_low(); /* This enables the SPI. It can stay low for all Audio SPI transactions */
}
void rfpt_init(void)
{
volatile uint16 wait;
SetWord16(CLK_RADIO_REG, 0x0089); // En BLE clk, dis BLE timer, En RFCU, RFCU div by 2
SetWord16(BLE_CNTL2_REG, 0x2000); //
SetBits16 (CLK_AMBA_REG, OTP_ENABLE, 1);
SetBits16 (CLK_AMBA_REG, HCLK_DIV, 0);
SetBits16 (TEST_CTRL_REG, ENABLE_RFPT, 1);
// Recommended settings
//set_recommended_settings();
rf_regs();
IffCalibration();
DCoffsetCalibration();
WAIT100(); // Wait 100 us to finish all DCF signals
}
void rf_regs(void)
{
SetWord32( BLE_RADIOPWRUPDN_REG, PREF_BLE_RADIOPWRUPDN_REG);
SetWord16( RF_LF_CTRL_REG, PREF_RF_LF_CTRL_REG);
SetWord16( RF_CP_CTRL_REG, PREF_RF_CP_CTRL_REG);
SetWord16( RF_REF_OSC_REG, PREF_RF_REF_OSC_REG);
SetWord16( RF_ENABLE_CONFIG1_REG, PREF_RF_ENABLE_CONFIG1_REG);
SetWord16( RF_ENABLE_CONFIG2_REG, PREF_RF_ENABLE_CONFIG2_REG);
SetWord16( RF_ENABLE_CONFIG6_REG, PREF_RF_ENABLE_CONFIG6_REG);
SetWord16( RF_ENABLE_CONFIG9_REG, PREF_RF_ENABLE_CONFIG9_REG);
SetWord16( RF_ENABLE_CONFIG10_REG, PREF_RF_ENABLE_CONFIG10_REG);
SetWord16( RF_ENABLE_CONFIG13_REG, PREF_RF_ENABLE_CONFIG13_REG);
SetWord16( RF_ENABLE_CONFIG14_REG, PREF_RF_ENABLE_CONFIG14_REG);
SetWord16( RF_ENABLE_CONFIG19_REG, PREF_RF_ENABLE_CONFIG19_REG);
SetWord16( RF_CNTRL_TIMER_3_REG, PREF_RF_CNTRL_TIMER_3_REG);
SetWord16( RF_CNTRL_TIMER_4_REG, PREF_RF_CNTRL_TIMER_4_REG);
SetWord16( RF_CNTRL_TIMER_8_REG, PREF_RF_CNTRL_TIMER_8_REG);
SetWord16( RF_CNTRL_TIMER_9_REG, PREF_RF_CNTRL_TIMER_9_REG);
SetWord16( RF_CNTRL_TIMER_10_REG, PREF_RF_CNTRL_TIMER_10_REG);
SetWord16( RF_CNTRL_TIMER_11_REG, PREF_RF_CNTRL_TIMER_11_REG);
SetWord16( RF_CNTRL_TIMER_12_REG, PREF_RF_CNTRL_TIMER_12_REG);
SetWord16( RF_CNTRL_TIMER_13_REG, PREF_RF_CNTRL_TIMER_13_REG);
SetWord16( RF_CNTRL_TIMER_14_REG, PREF_RF_CNTRL_TIMER_14_REG);
//SetWord16( BIAS_CTRL1_REG, PREF_BIAS_CTRL1_REG);
SetWord16( RF_DEM_CTRL_REG, PREF_RF_DEM_CTRL_REG);
SetWord16( RF_AGC_CTRL1_REG, PREF_RF_AGC_CTRL1_REG);
SetWord16( RF_AGC_CTRL2_REG, PREF_RF_AGC_CTRL2_REG);
SetWord16( RF_AGC_LUT_23_REG, PREF_RF_AGC_LUT_23_REG);
SetWord16( RF_AFC_CTRL_REG, PREF_RF_AFC_CTRL_REG);
SetWord16( RF_DC_OFFSET_CTRL2_REG, PREF_RF_DC_OFFSET_CTRL2_REG);
SetWord16( RF_DC_OFFSET_CTRL3_REG, PREF_RF_DC_OFFSET_CTRL3_REG);
SetWord16( RF_DC_OFFSET_CTRL4_REG, PREF_RF_DC_OFFSET_CTRL4_REG);
SetWord16( RF_PA_CTRL_REG, PREF_RF_PA_CTRL_REG);
SetWord16( RF_SYNTH_CTRL2_REG, PREF_RF_SYNTH_CTRL2_REG);
#if (LUT_PATCH_ENABLED)
SetBits16( RF_VCOCAL_CTRL_REG, VCO_FREQTRIM_SEL, 0x1);
#else
SetWord16( RF_VCOCAL_CTRL_REG, PREF_RF_VCOCAL_CTRL_REG);
#endif
#if (MGCKMODA_PATCH_ENABLED)
SetWord16( RF_MGAIN_CTRL_REG, 0x9503); // GAUSS_GAIN_SEL=0x1 and KMOD_ALPHA=3 to have some range above/below the final SW based KMOD_ALPHA value
#else
SetWord16( RF_MGAIN_CTRL_REG, PREF_RF_MGAIN_CTRL_REG);
#endif
SetWord16( RF_VCO_CALCAP_BIT14_REG, PREF_RF_VCO_CALCAP_BIT14_REG);
SetWord16( RF_LF_RES_CTRL_REG, PREF_RF_LF_RES_CTRL_REG);
SetWord16( RF_MGAIN_CTRL2_REG, PREF_RF_MGAIN_CTRL2_REG);
SetWord16(RF_MIXER_CTRL1_REG, iq_trim_rf_mixer_ctrl1_reg);
SetWord16(BIAS_CTRL1_REG, iq_trim_bias_ctrl1_reg);
// Near Field Mode Register Enable
#ifdef NEAR_FIELD_MODE_ENABLED
SetWord16(RF_ENABLE_CONFIG13_REG, 0x0030);
#endif
}
/**
****************************************************************************************
* @brief Gets ADC sample.
*
* @return ADC sample
****************************************************************************************
*/
int adc_get_sample(void){
int cnt=100000;
SetBits16(GP_ADC_CTRL_REG, GP_ADC_START, 1);
while (cnt-- && (GetWord16(GP_ADC_CTRL_REG) & GP_ADC_START) != 0x0000);
SetWord16(GP_ADC_CLEAR_INT_REG, 0x0000); // Clear interrupt
return GetWord16(GP_ADC_RESULT_REG);
}
void quad_decoder_init(QUAD_DEC_INIT_PARAMS_t *quad_dec_init_params)
{
// Enable the Quadrature clock
SetBits16(CLK_PER_REG, QUAD_ENABLE , true);
// Setup Quadrature Decoder pin assignment
SetWord16(QDEC_CTRL2_REG, quad_dec_init_params->chx_port_sel | quad_dec_init_params->chy_port_sel | quad_dec_init_params->chz_port_sel);
SetWord16(QDEC_CLOCKDIV_REG, quad_dec_init_params->qdec_clockdiv);
}
