Example #1
0
static void Int1Isr(void)
{
    uint8_t regIntr1;
    regIntr1 = SiiRegRead(REG_INTR1);
    if (regIntr1)
    {
        SiiRegWrite(REG_INTR1,regIntr1);
        if (BIT6 & regIntr1)
        {
            uint8_t cbusStatus;
        	cbusStatus = SiiRegRead(REG_MSC_REQ_ABORT_REASON);
        	TX_DEBUG_PRINT(("Drv: dsHpdStatus =%02X\n", (int) dsHpdStatus));
        	if(BIT6 & (dsHpdStatus ^ cbusStatus))
        	{
                uint8_t status = cbusStatus & BIT6;
        		TX_DEBUG_PRINT(("Drv: Downstream HPD changed to: %02X\n", (int) cbusStatus));
        		SiiMhlTxNotifyDsHpdChange( status );
                if(status)
                {
                   AudioVideoIsr(true);
                }
        		dsHpdStatus = cbusStatus;
        	}
        }
        if(BIT7 & regIntr1)
        {
        	TX_DEBUG_PRINT(("MHL soft interrupt triggered \n"));
        }
    }
}
Example #2
0
bool_t SiiMhlTxChipInitialize ( void )
{
    unsigned int initState = 0;
    tmdsPowRdy = false;
    mscCmdInProgress = false;	
    dsHpdStatus = 0;
    fwPowerState = POWER_STATE_D0_NO_MHL;
    SI_OS_DISABLE_DEBUG_CHANNEL(SII_OSAL_DEBUG_SCHEDULER);
    //memset(&video_data, 0x00, sizeof(video_data));	
    video_data.inputColorSpace = COLOR_SPACE_RGB;
    video_data.outputColorSpace = COLOR_SPACE_RGB;
    video_data.outputVideoCode = 2;
    video_data.inputcolorimetryAspectRatio = 0x18;
    video_data.outputcolorimetryAspectRatio = 0x18;
    video_data.output_AR = 0;
    //SiiMhlTxHwReset(TX_HW_RESET_PERIOD,TX_HW_RESET_DELAY);  
    //SiiCraInitialize();

    initState = (SiiRegRead(TX_PAGE_L0 | 0x03) << 8) | SiiRegRead(TX_PAGE_L0 | 0x02);
	//TX_DEBUG_PRINT(("Drv: SiiMhlTxChipInitialize: %02X%02x\n",
//						SiiRegRead(TX_PAGE_L0 | 0x03),
//						SiiRegRead(TX_PAGE_L0 | 0x02)));
	
    TX_DEBUG_PRINT(("Drv: SiiMhlTxChipInitialize: 0x%04X\n", initState));
	WriteInitialRegisterValues();
#ifndef __KERNEL__
    SiiOsMhlTxInterruptEnable();
#endif
	SwitchToD3();
    if (0xFFFF == initState)//0x8356
    {
	    return false;
    }
	return true;
}
uint16_t SiiMhlTxDrvGetDeviceId(void)
{
uint16_t retVal;
    retVal =  SiiRegRead(REG_DEV_IDH);
	retVal <<= 8;
	retVal |= SiiRegRead(REG_DEV_IDL);
    return retVal;
}
/**
 *  @brief Monitors 5293 interrupts and calls an interrupt processor
 *         function in the applicable driver if an interrupt is encountered.
 *
 *  @return     State
 *  @retval     true if device interrupts occurs
 *  @retval     false if no interrupts
 *
 * @note: This function is not designed to be called directly from a physical
 *        interrupt handler unless provisions have been made to avoid conflict
 *        with normal level I2C accesses.
 *        It is intended to be called from normal level by monitoring a flag
 *        set by the physical handler.
 *
 *****************************************************************************/
void SiiDrvDeviceManageInterrupts (void)
{
    uint8_t         intStatus2;

#if defined(__KERNEL__)
    //DEBUG_PRINT(MSG_STAT, ("-------------------SiiMhlTxDeviceIsr start -----------------\n"));
    while(is_interrupt_asserted())   // check interrupt assert bit
#else
    if (SiiRegRead(RX_A__INTR_STATE) & RX_M__INTR_STATE)
#endif
    {
#ifdef MHAWB_SUPPORT
        if (g_mhawb.state >= MHAWB_STATE_INIT)
        {
            if (mhawb_do_isr_work() == MHAWB_EVENT_HANDLER_SUCCESS)
                return;
        }
#endif
        // Determine the pending interrupts and service them with driver calls
        // Each function will call its appropriate callback function if a status
        // change is detected that needs upper level attention.

        // Get the register interrupt info
        intStatus2 = SiiRegRead( REG_INTR_STATE_2 );

        if(intStatus2 & BIT_RX_INTR)
        {
            DEBUG_PRINT(MSG_DBG, ("RX Interrupt\n"));
            SiiRxInterruptHandler();
            SiiRxSetVideoStableTimer();
        }
        if(intStatus2 & BIT_CBUS_INTR)
        {
            DEBUG_PRINT(MSG_DBG, ("CBUS Interrupt\n"));
#ifdef MHAWB_SUPPORT
            if (g_mhawb.state == MHAWB_STATE_TAKEOVER || g_mhawb.state == MHAWB_STATE_DISABLED)
            {
                SiiDrvHawbProcessInterrupts();
            }
#endif
            SiiDrvCbusProcessInterrupts();
            SiiMhlRxIntrHandler();
        }
#if defined(INC_CEC)
        if(intStatus2 & BIT_CEC_INTR)
        {
            DrvCpiProcessInterrupts();
            DEBUG_PRINT(MSG_DBG, ("CEC Interrupt\n"));
        }
#endif

        SiiSwitchConnectionCheck();

    }
#if defined(__KERNEL__)
    //DEBUG_PRINT(MSG_STAT, ("-------------------SiiMhlTxDeviceIsr end -------------------\n"));
#endif
}
int sii_get_h_active(void)
{
    unsigned char high,low;

    high = SiiRegRead(RX_A__DE_PIX2)&MSK__VID_DE_PIXEL_BIT8_11;
    low = SiiRegRead(RX_A__DE_PIX1);

    return ( (high<<8) | low );
}
int sii_get_v_total(void)
{
    unsigned char high,low;

    high = SiiRegRead(RX_A__V_RESH)&MSK__VID_V_RES_BIT8_10;
    low = SiiRegRead(RX_A__V_RESL);

    return ( (high<<8) | low );
}
int sii_get_hs_width(void)
{
    unsigned char high,low;

    high = SiiRegRead(RX_A__VID_HAW2)&MSK__VID_HS_WIDTH_BIT8_9;
    low = SiiRegRead(RX_A__VID_HAW1);

    return ( (high<<8) | low );
}
int sii_get_hs_frontporch(void)
{
    unsigned char high,low;

    high = SiiRegRead(RX_A__VID_HFP2)&MSK__VID_H_FP_BIT8_9;
    low = SiiRegRead(RX_A__VID_HFP);

    return ( (high<<8) | low );
}
int sii_get_v_active(void)
{
    unsigned char high,low;

    high = SiiRegRead(RX_A__DE_LINE2)&MSK__VID_DE_LINE_BIT8_10;
    low = SiiRegRead(RX_A__DE_LINE1);

    return ( (high<<8) | low );
}
Example #10
0
static void SetACRNValue (void)
{
    uint8_t audioFs;
    if ((SiiRegRead(TX_PAGE_L1 | 0x14) & BIT1) && !(SiiRegRead(TX_PAGE_L1 | 0x15) & BIT1))
        audioFs = SiiRegRead(TX_PAGE_L1 | 0x18) & 0x0F;
    else
        audioFs = SiiRegRead(TX_PAGE_L1 | 0x21) & 0x0F;
    switch (audioFs)
    {
        case 0x03:
            SiiRegWrite(TX_PAGE_L1 | 0x05, (uint8_t)(ACR_N_value_32k >> 16));
            SiiRegWrite(TX_PAGE_L1 | 0x04, (uint8_t)(ACR_N_value_32k >> 8));
            SiiRegWrite(TX_PAGE_L1 | 0x03, (uint8_t)(ACR_N_value_32k));
            break;
        case 0x00:
            SiiRegWrite(TX_PAGE_L1 | 0x05, (uint8_t)(ACR_N_value_44k >> 16));
            SiiRegWrite(TX_PAGE_L1 | 0x04, (uint8_t)(ACR_N_value_44k >> 8));
            SiiRegWrite(TX_PAGE_L1 | 0x03, (uint8_t)(ACR_N_value_44k));
            break;
        case 0x02:
            SiiRegWrite(TX_PAGE_L1 | 0x05, (uint8_t)(ACR_N_value_48k >> 16));
            SiiRegWrite(TX_PAGE_L1 | 0x04, (uint8_t)(ACR_N_value_48k >> 8));
            SiiRegWrite(TX_PAGE_L1 | 0x03, (uint8_t)(ACR_N_value_48k));
            break;
        case 0x08:
            SiiRegWrite(TX_PAGE_L1 | 0x05, (uint8_t)(ACR_N_value_88k >> 16));
            SiiRegWrite(TX_PAGE_L1 | 0x04, (uint8_t)(ACR_N_value_88k >> 8));
            SiiRegWrite(TX_PAGE_L1 | 0x03, (uint8_t)(ACR_N_value_88k));
            break;
        case 0x0A:
            SiiRegWrite(TX_PAGE_L1 | 0x05, (uint8_t)(ACR_N_value_96k >> 16));
            SiiRegWrite(TX_PAGE_L1 | 0x04, (uint8_t)(ACR_N_value_96k >> 8));
            SiiRegWrite(TX_PAGE_L1 | 0x03, (uint8_t)(ACR_N_value_96k));
            break;
        case 0x0C:
            SiiRegWrite(TX_PAGE_L1 | 0x05, (uint8_t)(ACR_N_value_176k >> 16));
            SiiRegWrite(TX_PAGE_L1 | 0x04, (uint8_t)(ACR_N_value_176k >> 8));
            SiiRegWrite(TX_PAGE_L1 | 0x03, (uint8_t)(ACR_N_value_176k));
            break;
        case 0x0E:
            SiiRegWrite(TX_PAGE_L1 | 0x05, (uint8_t)(ACR_N_value_192k >> 16));
            SiiRegWrite(TX_PAGE_L1 | 0x04, (uint8_t)(ACR_N_value_192k >> 8));
            SiiRegWrite(TX_PAGE_L1 | 0x03, (uint8_t)(ACR_N_value_192k));
            break;
        default:
            SiiRegWrite(TX_PAGE_L1 | 0x05, (uint8_t)(ACR_N_value_default >> 16));
            SiiRegWrite(TX_PAGE_L1 | 0x04, (uint8_t)(ACR_N_value_default >> 8));
            SiiRegWrite(TX_PAGE_L1 | 0x03, (uint8_t)(ACR_N_value_default));
            break;
    }
    SiiRegModify(REG_AUDP_TXCTRL, BIT2, CLEAR_BITS); 
}
Example #11
0
static void Int5Isr (void)
{
	uint8_t int5Status;
	int5Status = SiiRegRead(REG_INTR5);	
	if (int5Status)
	{
#if (SYSTEM_BOARD == SB_STARTER_KIT_X01)
    	if((int5Status & BIT3) || (int5Status & BIT2))
    	{
    		TX_DEBUG_PRINT (("** Apply MHL FIFO Reset\n"));
    		SiiRegModify(REG_SRST, BIT4, SET_BITS);
    		SiiRegModify(REG_SRST, BIT4, CLEAR_BITS);
    	}
#endif
        if (int5Status & BIT4)
        {
    		TX_DEBUG_PRINT (("** PXL Format changed\n"));
#ifndef __KERNEL__
            SiiOsBumpMhlTxEvent();
#else
            //SiiTriggerExtInt();
#endif
        }
    	SiiRegWrite(REG_INTR5, int5Status);	
	}
}
Example #12
0
static void MhlTxDrvProcessConnection ( void )
{
	TX_DEBUG_PRINT (("MHL Cable Connected. CBUS:0x0A = %02X\n", (int) SiiRegRead(REG_CBUS_BUS_STATUS)));
	if( POWER_STATE_D0_MHL == fwPowerState )
	{
		return;
	}
#ifdef __KERNEL__
    //HalGpioSetPin(GPIO_M2U_VBUS_CTRL,0);
#else
    pinM2uVbusCtrlM = 0;
#endif
#if (SYSTEM_BOARD == SB_EPV5_MARK_II)
    pinMhlConn = 0;
    pinUsbConn = 1;
#elif (SYSTEM_BOARD == SB_STARTER_KIT_X01)
#ifdef __KERNEL__
    //HalGpioSetPin(GPIO_MHL_USB,0);
#else
    pinMhlUsb = 0;
#endif
#endif
	SiiRegWrite(REG_MHLTX_CTL1, 0x10);
	fwPowerState = POWER_STATE_D0_MHL;
	
// change TMDS termination to 50 ohm termination(default)
//bits 1:0 set to 00
	SiiRegWrite(TX_PAGE_2|0x0001, 0x00);
	
	ENABLE_DISCOVERY;
	SiiMhlTxNotifyConnection(true);
}
/**
 *  @brief        Returns the CBus register value
 *
 *  @param[in]        regAddr        register address, channel
 *
 *  @return    register value
 *
 *****************************************************************************/
uint8_t  SiiDrvCbusDevCapsRegisterGet ( uint16_t offset )
{
    uint8_t value;

    value = SiiRegRead( REG_CBUS_DEVICE_CAP_0 + offset );
    return ( value );
}
Example #14
0
void 	SiiMhlTxDeviceIsr( void )
{
    uint8_t intMStatus, i; 
#ifdef TRACE_INT_TIME
    unsigned long K1;
    unsigned long K2;
    printk("-------------------SiiMhlTxDeviceIsr start -----------------\n");
	K1 = get_jiffies_64();
#endif
	i=0;
    do
    {
        if( POWER_STATE_D0_MHL != fwPowerState )
        {
            if(I2C_INACCESSIBLE == Int4Isr())
            {
				TX_DEBUG_PRINT(("Drv: I2C_INACCESSIBLE in Int4Isr in not D0 mode\n"));
                return; 
            }
        }
        else if( POWER_STATE_D0_MHL == fwPowerState )
        {
            if(I2C_INACCESSIBLE == Int4Isr())
            {
           		TX_DEBUG_PRINT(("Drv: I2C_INACCESSIBLE in Int4Isr in D0 mode\n"));
    			return; 
            }
            MhlCbusIsr();
            Int5Isr();
            Int1Isr();
            Int2Isr();
        }
        if( POWER_STATE_D3 != fwPowerState )
        {
    		MhlTxProcessEvents();
        }
		intMStatus = SiiRegRead(REG_INTR_STATE);	
		if(0xFF == intMStatus)
		{
			intMStatus = 0;
		    TX_DEBUG_PRINT(("Drv: EXITING ISR DUE TO intMStatus - 0xFF loop = [%02X] intMStatus = [%02X] \n\n", (int) i, (int)intMStatus));
		}
		i++;
		intMStatus &= 0x01; 
        if(i>60)
        {
            TX_DEBUG_PRINT(("force exit SiiMhlTxDeviceIsr \n"));
            break;
        }
        else if(i> 50)
        {
            TX_DEBUG_PRINT(("something error in SiiMhlTxDeviceIsr \n"));
        }
	} while (intMStatus);
#ifdef TRACE_INT_TIME
    K2 = get_jiffies_64();
    printk("-------------------SiiMhlTxDeviceIsr last %d ms----------------\n",(int)(K2 - K1));
#endif
}
Example #15
0
// audio sampling frequency:
// 0x0 for 44.1 KHz
// 0x1 for Not indicated
// 0x2 for 48 KHz
// 0x3 for 32 KHz
// 0x4 for 22.05 KHz
// 0x6 for 24 kHz
// 0x8 for 88.2 kHz
// 0x9 for 768 kHz (192*4)
// 0xa for 96 kHz
// 0xc for 176.4 kHz
// 0xe for 192 kHz
int sii_get_audio_sampling_freq(void)
{
    unsigned char freq;

    freq = SiiRegRead(RX_A__CHST4)&RX_A__CHST4__BIT_AUD_FS;

    return freq;
}
Example #16
0
int sii_get_vs_to_de(void)
{
    unsigned char low;

    low = SiiRegRead(RX_A__VTAVL)&MSK__VID_VS_AVT_BIT0_5;

    return low;
}
Example #17
0
int sii_get_vs_frontporch(void)
{
    unsigned char low;

    low = SiiRegRead(RX_A__VID_VFP)&MSK__VID_V_FP_BIT0_5;

    return low;
}
Example #18
0
static	int	Int2Isr( void )
{
    if(SiiRegRead(REG_INTR2) & INTR_2_DESIRED_MASK)
    {
        SiiRegWrite(REG_INTR2, INTR_2_DESIRED_MASK);
        if(SiiRegRead(REG_SYS_STAT) & BIT1)
        {
            TX_DEBUG_PRINT(("PCLK is STABLE\n"));
            if (tmdsPowRdy)
            {
                SendAudioInfoFrame();
                SendAviInfoframe();
            }
        }
    }
    return 0;
}
Example #19
0
int sii_get_pwr5v_status(void)
{
    char pwr5v;

    pwr5v = SiiRegRead(RX_A__STATE)&RX_M__STATE__PWR5V;

    return (pwr5v==0)?0:1;
}
Example #20
0
void SiiMhlTxDrvGetScratchPad(uint8_t startReg,uint8_t *pData,uint8_t length)
{
int i;
    for (i = 0; i < length;++i,++startReg)
    {
        *pData++ = SiiRegRead(REG_CBUS_SCRATCHPAD_0 + startReg);
    }
}
Example #21
0
void SiiRegBitsSet ( SiiReg_t virtualAddr, uint8_t bitMask, bool_t setBits )
{
    uint8_t aByte;

    aByte = SiiRegRead( virtualAddr );
    aByte = (setBits) ? (aByte | bitMask) : (aByte & ~bitMask);
    SiiRegWrite( virtualAddr, aByte );
}
///////////////////////////////////////////////////////////////////////////
//
// MhlTxDrvProcessConnection
//
///////////////////////////////////////////////////////////////////////////
static void MhlTxDrvProcessConnection (void)
{
	TX_DEBUG_PRINT (("Drv: MHL Cable Connected. CBUS:0x0A = %02X\n", (int) SiiRegRead(TX_PAGE_CBUS | 0x000A)));

	if( POWER_STATE_D0_MHL == fwPowerState )
	{
		return;
	}
	// VBUS control gpio
	//pinM2uVbusCtrlM = 0;
	//pinMhlConn = 0;
	//pinUsbConn = 1;

	//
	// Discovery over-ride: reg_disc_ovride	
	//
	SiiRegWrite(REG_MHLTX_CTL1, 0x10);

	fwPowerState = POWER_STATE_D0_MHL;

	//
	// Increase DDC translation layer timer (uint8_t mode)
	// Setting DDC Byte Mode
	//
	SiiRegWrite(REG_CBUS_COMMON_CONFIG, 0xF2);

	// Enable segment pointer safety
	//SET_BIT(0x0C44, 1);

	// Un-force HPD (it was kept low, now propagate to source
	//CLR_BIT(REG_INT_CTRL, 4);

	// Enable TMDS
	//SiiMhlTxDrvTmdsControl( true );

	
	// Change TMDS termination to 50 ohm termination (default)
	// Bits 1:0 set to 00
	SiiRegWrite(TX_PAGE_2 | 0x0001, 0x00);

	// Keep the discovery enabled. Need RGND interrupt
	ENABLE_DISCOVERY

	// Wait T_SRC_RXSENSE_CHK ms to allow connection/disconnection to be stable (MHL 1.0 specs)
//	TX_DEBUG_PRINT (("[%d] Drv: Wait T_SRC_RXSENSE_CHK (%d ms) before checking RSEN\n",
//							(int) (HalTimerElapsed( ELAPSED_TIMER ) * MONITORING_PERIOD),
//							(int) T_SRC_RXSENSE_CHK) );

	//
	// Ignore RSEN interrupt for T_SRC_RXSENSE_CHK duration.
	// Get the timer started
	//
//	HalTimerSet(TIMER_TO_DO_RSEN_CHK, T_SRC_RXSENSE_CHK);

	// Notify upper layer of cable connection
	SiiMhlTxNotifyConnection(mhlConnected = true);
}
Example #23
0
void SiiRegModify ( SiiReg_t virtualAddr, uint8_t mask, uint8_t value)
{
    uint8_t aByte;

    aByte = SiiRegRead( virtualAddr );
    aByte &= (~mask);                       // first clear all bits in mask
    aByte |= (mask & value);                // then set bits from value
    SiiRegWrite( virtualAddr, aByte );
}
/*
 SiiMhlTxDrvMscMsgNacked
    returns:
        0 - message was not NAK'ed
        non-zero message was NAK'ed
 */
int SiiMhlTxDrvMscMsgNacked(void)
{
    if (SiiRegRead(REG_MSC_WRITE_BURST_LEN) & MSC_MT_DONE_NACK_MASK)
    {

        TX_DEBUG_PRINT(("MSC MSG NAK'ed - retrying...\n\n"));
        return 1;
    }
    return 0;
}
Example #25
0
void SiiRegBitsSetNew ( SiiReg_t virtualAddr, uint8_t bitMask, bool_t setBits )
{
    uint8_t newByte, oldByte;

    oldByte = SiiRegRead( virtualAddr );
    newByte = (setBits) ? (oldByte | bitMask) : (oldByte & ~bitMask);
    if ( oldByte != newByte )
    {
        SiiRegWrite( virtualAddr, newByte );
    }
}
Example #26
0
static void SetAudioMode(inAudioTypes_t audiomode)
{
    if (audiomode >= AUD_TYP_NUM)
        audiomode = I2S_48;
    SiiRegWrite(REG_AUDP_TXCTRL, audioData[audiomode].regAUD_path);
    SiiRegWrite(TX_PAGE_L1 | 0x14, audioData[audiomode].regAUD_mode);
    SiiRegWrite(TX_PAGE_L1 | 0x1D, audioData[audiomode].regAUD_ctrl);
    SiiRegWrite(TX_PAGE_L1 | 0x21, audioData[audiomode].regAUD_freq);
    SiiRegWrite(TX_PAGE_L1 | 0x23, audioData[audiomode].regAUD_src);
    SiiRegWrite(TX_PAGE_L1 | 0x28, audioData[audiomode].regAUD_tdm_ctrl);
//  SiiRegWrite(TX_PAGE_L1 | 0x22, 0x0B); 
//0x02 for word length=16bits
		    SiiRegWrite(TX_PAGE_L1 | 0x22, 0x02); 
		SiiRegWrite(TX_PAGE_L1 | 0x24,0x02); 

    SiiRegWrite(TX_PAGE_L1 | 0x15, 0x00); 
	//0x7A:0x24 = 0x0B for word lenth is defult 24bit
	
	TX_DEBUG_PRINT(("SiiRegRead(TX_PAGE_L1 | 0x21)=0x%x\n",SiiRegRead(TX_PAGE_L1 | 0x21)));
	TX_DEBUG_PRINT(("SiiRegRead(TX_PAGE_L1 | 0x1D)=0x%x\n",SiiRegRead(TX_PAGE_L1 | 0x1D)));
}
Example #27
0
static void MhlTxDrvProcessDisconnection ( void )
{
	TX_DEBUG_PRINT(("MhlTxDrvProcessDisconnection\n"));
	SiiRegWrite(REG_INTR4, SiiRegRead(REG_INTR4));
	dsHpdStatus &= ~BIT6;  
	SiiRegWrite(REG_MSC_REQ_ABORT_REASON, dsHpdStatus);
	SiiMhlTxNotifyDsHpdChange(0);
	if( POWER_STATE_D0_MHL == fwPowerState )
	{
		SiiMhlTxNotifyConnection(false);
	}
	SwitchToD3();
}
Example #28
0
static	int	Int4Isr( void )
{
	uint8_t int4Status;
	int4Status = SiiRegRead(REG_INTR4);	
    if(!int4Status)
    {
    }
	else if(0xFF == int4Status)
	{
        return I2C_INACCESSIBLE;
	}else
	{
        TX_DEBUG_PRINT(("INT4 Status = %02X\n", (int) int4Status));
    	if(int4Status & BIT0) 
    	{
    		ProcessScdtStatusChange();
    	}
    	if(int4Status & BIT2) 
    	{
    		MhlTxDrvProcessConnection();
    	}
    	else if(int4Status & BIT3)
    	{
    		TX_DEBUG_PRINT(("uUSB-A type device detected.\n"));
    		SiiRegWrite(REG_DISC_STAT2, 0x80);	
    		SwitchToD3();
			return I2C_INACCESSIBLE;
        }
    	if (int4Status & BIT5)
    	{
    		MhlTxDrvProcessDisconnection();
            return I2C_INACCESSIBLE;
    	}
        if((POWER_STATE_D0_MHL != fwPowerState) && (int4Status & BIT6))
    	{
    		SwitchToD0();
    		ProcessRgnd();
    	}
    	if(fwPowerState != POWER_STATE_D3)
        {
            if (int4Status & BIT4)
            {
                TX_DEBUG_PRINT(("CBus Lockout\n"));
                ForceUsbIdSwitchOpen();
                ReleaseUsbIdSwitchOpen();
            }
        }
    }
	SiiRegWrite(REG_INTR4, int4Status);	
	return I2C_ACCESSIBLE;
}
static void ProcessScdtStatusChange(void)
{
	uint8_t scdtStatus;
	uint8_t mhlFifoStatus;

	scdtStatus = SiiRegRead(REG_TMDS_CSTAT);

	TX_DEBUG_PRINT(("Drv: ProcessScdtStatusChange scdtStatus: 0x%02x\n", scdtStatus));

	if (scdtStatus & 0x02)
	{
		 mhlFifoStatus = SiiRegRead(REG_INTR5);
		 TX_DEBUG_PRINT(("MHL FIFO status: 0x%02x\n", mhlFifoStatus));
		 if (mhlFifoStatus & 0x0C)
		 {
			SiiRegWrite(REG_INTR5, 0x0C);

			TX_DEBUG_PRINT(("** Apply MHL FIFO Reset\n"));
			SiiRegWrite(REG_SRST, 0x94);
			SiiRegWrite(REG_SRST, 0x84);
		 }
	}
}
bool_t SiiMhlTxChipInitialize (void)
{
	tmdsPoweredUp = false;
	mhlConnected = false;
	mscCmdInProgress = false;	// false when it is okay to send a new command
	dsHpdStatus = 0;
	fwPowerState = POWER_STATE_FIRST_INIT;
    //SI_OS_DISABLE_DEBUG_CHANNEL(SII_OSAL_DEBUG_SCHEDULER);

    g_chipRevId = SiiRegRead(REG_DEV_REV);

	// then wait 100ms per MHL spec
	HalTimerWait(TX_HW_RESET_DELAY);
	TX_DEBUG_PRINT(("Drv: SiiMhlTxChipInitialize: %02X%02X%02x\n",
						g_chipRevId,
					SiiRegRead(TX_PAGE_L0 | 0x03),
					SiiRegRead(TX_PAGE_L0 | 0x02)));

	// setup device registers. Ensure RGND interrupt would happen.
	WriteInitialRegisterValues();

    //SiiOsMhlTxInterruptEnable();

	// CBUS interrupts are unmasked after performing the reset.
	// UNMASK_CBUS1_INTERRUPTS;
	// UNMASK_CBUS2_INTERRUPTS;

	//
	// Allow regular operation - i.e. pinAllowD3 is high so we do enter
	// D3 first time. Later on, SiIMon shall control this GPIO.
	//
	//pinAllowD3 = 1;

	SwitchToD3();

	return true;
}