static int mtk_capture_alsa_start(struct snd_pcm_substream *substream)
{
printk("mtk_capture_alsa_start \n");
SetMemifSubStream(Soc_Aud_Digital_Block_MEM_VUL, substream);
StartAudioCaptureHardware(substream);
return 0;
}
static int mtk_capture_alsa_start(struct snd_pcm_substream *substream)
{
printk("mtk_capture_alsa_start \n");
SetMemifSubStream(Soc_Aud_Digital_Block_MEM_VUL, substream);
StartAudioCaptureHardware(substream);
#ifdef DENALI_FPGA_EARLYPORTING //ccc early porting, copy from TurnOnDacPower() and ADC_LOOP_DAC_Func()
// Afe_Set_Reg(AFE_SGEN_CON0, 0x24862862, 0xffffffff);
// Ana_Set_Reg(PMIC_AFE_TOP_CON0, 0x0002, 0x0002); //UL from sinetable
// Ana_Set_Reg(PMIC_AFE_TOP_CON0, 0x0001, 0x0001); //DL from sinetable
// Ana_Set_Reg(AFE_SGEN_CFG0 , 0x0080 , 0xffff);
// Ana_Set_Reg(AFE_SGEN_CFG1 , 0x0101 , 0xffff);
Ana_Get_Reg(AFE_AUDIO_TOP_CON0); //power on clock
Ana_Get_Reg(AFUNC_AUD_CON2);
Ana_Get_Reg(AFUNC_AUD_CON0); //sdm audio fifo clock power on
Ana_Get_Reg(AFUNC_AUD_CON2); //sdm power on
Ana_Get_Reg(AFUNC_AUD_CON2); //sdm fifo enable
Ana_Get_Reg(AFE_DL_SDM_CON1); //set attenuation gain
Ana_Get_Reg(AFE_UL_DL_CON0); //[0] afe enable
Ana_Get_Reg(AFE_PMIC_NEWIF_CFG0); //8k sample rate
Ana_Get_Reg(AFE_DL_SRC2_CON0_H);//8k sample rate
Ana_Get_Reg(AFE_DL_SRC2_CON0_L); //turn off mute function and turn on dl
Ana_Get_Reg(PMIC_AFE_TOP_CON0); //set DL in normal path, not from sine gen table
Ana_Get_Reg(AFE_SGEN_CFG0); //set DL in normal path, not from sine gen table
Ana_Get_Reg(AFE_SGEN_CFG1); //set DL in normal path, not from sine gen table
Ana_Get_Reg(TOP_CLKSQ); //Enable CLKSQ 26MHz
Ana_Get_Reg(TOP_CLKSQ_SET); //Turn on 26MHz source clock
Ana_Get_Reg(AFE_AUDIO_TOP_CON0); //power on clock
Ana_Get_Reg(FPGA_CFG1); // must set in FPGA platform for PMIC digital loopback
#endif
return 0;
}
