/**
* FchInitLateHwAcpi - Prepare HwAcpi controller to boot to OS.
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitLateHwAcpi (
IN VOID *FchDataPtr
)
{
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
UINT8 i;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
GcpuRelatedSetting (LocalCfgPtr);
// Mt C1E Enable
MtC1eEnable (LocalCfgPtr);
if (LocalCfgPtr->Gpp.SerialDebugBusEnable == TRUE ) {
RwMem (ACPI_MMIO_BASE + SERIAL_DEBUG_BASE + FCH_SDB_REG00, AccessWidth8, 0xFF, 0x05);
}
StressResetModeLate (LocalCfgPtr);
SbSleepTrapControl (FALSE);
for (i = 0; i < NUM_OF_DEVICE_FOR_APICIRQ; i++) {
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC00, &FchInternalDeviceIrqForApicMode[i].PciIrqIndex, StdHeader);
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC01, &FchInternalDeviceIrqForApicMode[i].PciIrqData, StdHeader);
}
}
/**
* sbLatePost - Prepare Southbridge to boot to OS.
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
sbLatePost (
IN AMDSBCFG* pConfig
)
{
// UINT16 dwVar;
BUILDPARAM *pStaticOptions;
pStaticOptions = &(pConfig->BuildParameters);
TRACE ((DMSG_SB_TRACE, "CIMx - Entering sbLatePost \n"));
commonInitLateBoot (pConfig);
sataInitLatePost (pConfig);
gecInitLatePost (pConfig);
hpetInit (pConfig, pStaticOptions); // SB Configure HPET base and enable bit
#ifndef NO_EC_SUPPORT
ecInitLatePost (pConfig);
#endif
sbPcieGppLateInit (pConfig);
hwmImcInit (pConfig);
// hwmSbtsiAutoPollingOff (pConfig);
imcDisarmSurebootTimer (pConfig);
usbInitLate (pConfig); // Init USB
StressResetModeLate (pConfig); //
}
