/**************************************************************************************************
* @fn SysCtrlSleepSetting
*
* @brief Setup which peripherals are enabled/disabled in Sleep
*
* input parameters
*
* @param None.
*
* output parameters
*
* None.
*
* @return None.
**************************************************************************************************/
void SysCtrlSleepSetting(void)
{
/* Disable General Purpose Timers 0, 1, 2, 3 during sleep */
SysCtrlPeripheralSleepDisable(SYS_CTRL_PERIPH_GPT0);
SysCtrlPeripheralSleepDisable(SYS_CTRL_PERIPH_GPT1);
SysCtrlPeripheralSleepDisable(SYS_CTRL_PERIPH_GPT2);
SysCtrlPeripheralSleepDisable(SYS_CTRL_PERIPH_GPT3);
/* Disable SSI 0, 1 during sleep */
SysCtrlPeripheralSleepEnable(SYS_CTRL_PERIPH_SSI0);
SysCtrlPeripheralSleepDisable(SYS_CTRL_PERIPH_SSI1);
/* Disable UART 0, 1 during sleep */
SysCtrlPeripheralSleepDisable(SYS_CTRL_PERIPH_UART0);
SysCtrlPeripheralSleepEnable(SYS_CTRL_PERIPH_UART1);
/* Disable I2C, PKA, AES during sleep */
SysCtrlPeripheralSleepDisable(SYS_CTRL_PERIPH_I2C);
SysCtrlPeripheralSleepDisable(SYS_CTRL_PERIPH_PKA);
SysCtrlPeripheralSleepDisable(SYS_CTRL_PERIPH_AES);
/*
* Disable RFC during sleep. Please note that this setting is
* only valid for PG2.0. For PG1.0 this is just a dummy instruction.
*/
SysCtrlPeripheralSleepDisable(SYS_CTRL_PERIPH_RFC);
}
void i2c_init(void) {
bool status;
// Enable peripheral except in deep sleep modes (e.g. LPM1, LPM2, LPM3)
SysCtrlPeripheralEnable(I2C_PERIPHERAL);
SysCtrlPeripheralSleepEnable(I2C_PERIPHERAL);
SysCtrlPeripheralDeepSleepDisable(I2C_PERIPHERAL);
// Reset peripheral previous to configuring it
SysCtrlPeripheralReset(I2C_PERIPHERAL);
// Configure the SCL pin
GPIOPinTypeI2C(I2C_BASE, I2C_SCL);
IOCPinConfigPeriphInput(I2C_BASE, I2C_SCL, IOC_I2CMSSCL);
IOCPinConfigPeriphOutput(I2C_BASE, I2C_SCL, IOC_MUX_OUT_SEL_I2C_CMSSCL);
// Configure the SDA pin
GPIOPinTypeI2C(I2C_BASE, I2C_SDA);
IOCPinConfigPeriphInput(I2C_BASE, I2C_SDA, IOC_I2CMSSDA);
IOCPinConfigPeriphOutput(I2C_BASE, I2C_SDA, IOC_MUX_OUT_SEL_I2C_CMSSDA);
// Configure the I2C clock
status = (I2C_BAUDRATE == 400000 ? true : false);
I2CMasterInitExpClk(SysCtrlClockGet(), status);
// Enable the I2C module as master
I2CMasterEnable();
}
/*
* Public API
*/
void
ws_radio_init(void)
{
WS_DEBUG("init\n");
/* Reset state */
memset(&radio_state, 0, sizeof(radio_state));
/* Enable the clock */
/* TODO: Power saving. We're basically leaving the radio on all the time */
SysCtrlPeripheralReset(SYS_CTRL_PERIPH_RFC);
SysCtrlPeripheralEnable(SYS_CTRL_PERIPH_RFC);
SysCtrlPeripheralSleepEnable(SYS_CTRL_PERIPH_RFC);
SysCtrlPeripheralDeepSleepEnable(SYS_CTRL_PERIPH_RFC);
/* Configure CCA */
HWREG(RFCORE_XREG_CCACTRL0) = CC2538_RFCORE_CCA_THRES;
/* User Manual 23.15 - TX and RX settings */
HWREG(RFCORE_XREG_AGCCTRL1) = CC2538_RFCORE_AGC_TARGET;
HWREG(RFCORE_XREG_TXFILTCFG) = CC2538_RFCORE_TX_AA_FILTER;
HWREG(ANA_REGS_BASE + ANA_REGS_O_IVCTRL) = CC2538_RFCORE_BIAS_CURRENT;
HWREG(RFCORE_XREG_FSCAL1) = CC2538_RFCORE_FREQ_CAL;
/* Enable auto CRC calculation (hardware) */
HWREG(RFCORE_XREG_FRMCTRL0) = RFCORE_XREG_FRMCTRL0_AUTOCRC;
/* Enable auto ACK */
HWREG(RFCORE_XREG_FRMCTRL0) |= RFCORE_XREG_FRMCTRL0_AUTOACK;
/* Configure the FIFOP signal to trigger when there are one or more
* complete frames in the RX FIFO */
HWREG(RFCORE_XREG_FIFOPCTRL) = WS_RADIO_MAX_PACKET_LEN;
/* Set the TX output power */
HWREG(RFCORE_XREG_TXPOWER) = CC2538_RFCORE_TX_POWER;
/* Interrupt wth FIFOP signal */
HWREG(RFCORE_XREG_RFIRQM0) = 0x04;
IntRegister(INT_RFCORERTX, &rf_isr);
IntEnable(INT_RFCORERTX);
/* Interrupt with all RF ERROR signals */
HWREG(RFCORE_XREG_RFERRM) = 0x7f;
IntRegister(INT_RFCOREERR, &rf_err_isr);
IntEnable(INT_RFCOREERR);
/* Configure the frame filtering */
HWREG(RFCORE_XREG_FRMFILT0) &= ~RFCORE_XREG_FRMFILT0_MAX_FRAME_VERSION_M;
HWREG(RFCORE_XREG_FRMFILT0) |= WS_MAC_MAX_FRAME_VERSION <<
RFCORE_XREG_FRMFILT0_MAX_FRAME_VERSION_S;
/* Don't bother filtering out the source addresses */
HWREG(RFCORE_XREG_SRCMATCH) &= ~RFCORE_XREG_SRCMATCH_SRC_MATCH_EN;
}
static void SysCtrlSleepSetting(void)
{
/* Disable General Purpose Timers 0, 1, 2, 3 during sleep */
SysCtrlPeripheralSleepDisable(SYS_CTRL_PERIPH_GPT0);
SysCtrlPeripheralSleepDisable(SYS_CTRL_PERIPH_GPT1);
SysCtrlPeripheralSleepDisable(SYS_CTRL_PERIPH_GPT2);
SysCtrlPeripheralSleepDisable(SYS_CTRL_PERIPH_GPT3);
/* Disable SSI 0, 1 during sleep */
SysCtrlPeripheralSleepDisable(SYS_CTRL_PERIPH_SSI0);
SysCtrlPeripheralSleepDisable(SYS_CTRL_PERIPH_SSI1);
/* Disable UART 0, 1 during sleep */
SysCtrlPeripheralSleepDisable(SYS_CTRL_PERIPH_UART1);
/* Disable I2C, PKA, AES during sleep */
SysCtrlPeripheralSleepDisable(SYS_CTRL_PERIPH_I2C);
SysCtrlPeripheralSleepDisable(SYS_CTRL_PERIPH_PKA);
SysCtrlPeripheralSleepDisable(SYS_CTRL_PERIPH_AES);
/* Enable UART and RFC during sleep */
SysCtrlPeripheralSleepEnable(SYS_CTRL_PERIPH_UART0);
SysCtrlPeripheralSleepEnable(SYS_CTRL_PERIPH_RFC);
}
void Spi::enable(uint32_t baudrate)
{
GpioConfig& miso = miso_.getGpioConfig();
GpioConfig& mosi = mosi_.getGpioConfig();
GpioConfig& clk = clk_.getGpioConfig();
// GpioConfig& ncs = ncs_.getGpioConfig();
// Store baudrate in configuration
if (baudrate != 0) {
config_.baudrate = baudrate;
}
// Enable peripheral except in deep sleep modes (e.g. LPM1, LPM2, LPM3)
SysCtrlPeripheralEnable(config_.peripheral);
SysCtrlPeripheralSleepEnable(config_.peripheral);
SysCtrlPeripheralDeepSleepDisable(config_.peripheral);
// Reset peripheral previous to configuring it
SSIDisable(config_.base);
// Set IO clock as SPI0 clock source
SSIClockSourceSet(config_.base, config_.clock);
// Configure the MISO, MOSI, CLK and nCS pins as peripheral
IOCPinConfigPeriphInput(miso.port, miso.pin, miso.ioc);
IOCPinConfigPeriphOutput(mosi.port, mosi.pin, mosi.ioc);
IOCPinConfigPeriphOutput(clk.port, clk.pin, clk.ioc);
// IOCPinConfigPeriphOutput(ncs.port, ncs.pin, ncs.ioc);
// Configure MISO, MOSI, CLK and nCS GPIOs
GPIOPinTypeSSI(miso.port, miso.pin);
GPIOPinTypeSSI(mosi.port, mosi.pin);
GPIOPinTypeSSI(clk.port, clk.pin);
// GPIOPinTypeSSI(ncs.port, ncs.pin);
// Configure the SPI0 clock
SSIConfigSetExpClk(config_.base, SysCtrlIOClockGet(), config_.protocol, \
config_.mode, config_.baudrate, config_.datawidth);
// Enable the SPI0 module
SSIEnable(config_.base);
}
void Uart::enable(uint32_t baudrate)
{
// Get GpioConfig structures
GpioConfig& rx = rx_.getGpioConfig();
GpioConfig& tx = tx_.getGpioConfig();
// Store baudrate in configuration
if (baudrate != 0) {
config_.baudrate = baudrate;
}
// Enable peripheral except in deep sleep modes (e.g. LPM1, LPM2, LPM3)
SysCtrlPeripheralEnable(config_.peripheral);
SysCtrlPeripheralSleepEnable(config_.peripheral);
SysCtrlPeripheralDeepSleepDisable(config_.peripheral);
// Disable peripheral previous to configuring it
UARTDisable(config_.peripheral);
// Set IO clock as UART clock source
UARTClockSourceSet(config_.base, config_.clock);
// Configure the UART RX and TX pins
IOCPinConfigPeriphInput(rx.port, rx.pin, rx.ioc);
IOCPinConfigPeriphOutput(tx.port, tx.pin, tx.ioc);
// Configure the UART GPIOs
GPIOPinTypeUARTInput(rx.port, rx.pin);
GPIOPinTypeUARTOutput(tx.port, tx.pin);
// Configure the UART
UARTConfigSetExpClk(config_.base, SysCtrlIOClockGet(), config_.baudrate, config_.mode);
// Disable FIFO as we only use a one-byte buffer
UARTFIFODisable(config_.base);
// Raise an interrupt at the end of transmission
UARTTxIntModeSet(config_.base, UART_TXINT_MODE_EOT);
// Enable UART hardware
UARTEnable(config_.base);
}
void Uart::enable(uint32_t baudrate, uint32_t config, uint32_t mode)
{
// Store the UART baudrate, configuration and mode
baudrate_ = baudrate;
config_ = config;
mode_ = mode;
// Enable peripheral except in deep sleep modes (e.g. LPM1, LPM2, LPM3)
SysCtrlPeripheralEnable(uart_.peripheral);
SysCtrlPeripheralSleepEnable(uart_.peripheral);
SysCtrlPeripheralDeepSleepDisable(uart_.peripheral);
// Disable peripheral previous to configuring it
UARTDisable(uart_.peripheral);
// Set IO clock as UART clock source
UARTClockSourceSet(uart_.base, uart_.clock);
// Configure the UART RX and TX pins
IOCPinConfigPeriphInput(rx_.getPort(), rx_.getPin(), rx_.getIoc());
IOCPinConfigPeriphOutput(tx_.getPort(), tx_.getPin(), tx_.getIoc());
// Configure the UART GPIOs
GPIOPinTypeUARTInput(rx_.getPort(), rx_.getPin());
GPIOPinTypeUARTOutput(tx_.getPort(), tx_.getPin());
// Configure the UART
UARTConfigSetExpClk(uart_.base, SysCtrlIOClockGet(), baudrate_, config_);
// Disable FIFO as we only use a one-byte buffer
UARTFIFODisable(uart_.base);
// Raise an interrupt at the end of transmission
UARTTxIntModeSet(uart_.base, mode_);
// Enable UART hardware
UARTEnable(uart_.base);
}
void Spi::enable(uint32_t mode, uint32_t protocol, uint32_t datawidth, uint32_t baudrate)
{
// Store SPI mode, protoco, baudrate and datawidth
mode_ = mode;
protocol_ = protocol;
baudrate_ = baudrate;
datawidth_ = datawidth;
// Enable peripheral except in deep sleep modes (e.g. LPM1, LPM2, LPM3)
SysCtrlPeripheralEnable(peripheral_);
SysCtrlPeripheralSleepEnable(peripheral_);
SysCtrlPeripheralDeepSleepDisable(peripheral_);
// Reset peripheral previous to configuring it
SSIDisable(base_);
// Set IO clock as SPI0 clock source
SSIClockSourceSet(base_, clock_);
// Configure the MISO, MOSI, CLK and nCS pins as peripheral
IOCPinConfigPeriphInput(miso_.getPort(), miso_.getPin(), miso_.getIoc());
IOCPinConfigPeriphOutput(mosi_.getPort(), mosi_.getPin(), mosi_.getIoc());
IOCPinConfigPeriphOutput(clk_.getPort(), clk_.getPin(), clk_.getIoc());
// IOCPinConfigPeriphOutput(ncs_.getPort(), ncs_.getPin(), ncs_.getIoc());
// Configure MISO, MOSI, CLK and nCS GPIOs
GPIOPinTypeSSI(miso_.getPort(), miso_.getPin());
GPIOPinTypeSSI(mosi_.getPort(), mosi_.getPin());
GPIOPinTypeSSI(clk_.getPort(), clk_.getPin());
// GPIOPinTypeSSI(ncs_.getPort(), ncs_.getPin());
// Configure the SPI0 clock
SSIConfigSetExpClk(base_, SysCtrlIOClockGet(), protocol_, \
mode_, baudrate_, datawidth_);
// Enable the SPI0 module
SSIEnable(base_);
}
