/*
* ======== SysMin_abort ========
*/
Void SysMin_abort(String str)
{
Char ch;
if (SysMin_bufSize != 0) {
if (str != NULL) {
while ((ch = *str++) != '\0') {
SysMin_putch(ch);
}
}
/* Only flush if configured to do so */
if (SysMin_flushAtExit) {
SysMin_flush();
}
}
/*
* System_abort() in xdc/runtime/System.c enters the System gate
* before aborting, but does not leave the gate. Aforementioned
* System gate maps to the Inter-core gate entered by the Hwi lock.
* Since Hwi lock is never released, the other core's dispacther
* may spin forever, waiting to acquire the Hwi lock.
*
* We Unlock Hwi before returning so all locks are released before
* exiting.
*/
Core_unlock();
}
/*
* ======== SysMin_abort ========
*/
Void SysMin_abort(String str)
{
Char ch;
if (SysMin_bufSize != 0) {
if (str != NULL) {
while ((ch = *str++) != '\0') {
SysMin_putch(ch);
}
}
/* Only flush if configured to do so */
if (SysMin_flushAtExit) {
SysMin_flush();
}
}
}
/*
* ======== SysMin_exit ========
*/
Void SysMin_exit(Int stat)
{
/*
* System_rtsExit() in xdc/runtime/System.c enters the System gate
* before exiting, but does not leave the gate. The BASEPRI
* register on Arm M3 is therefore not restored to 0 (disabled state).
* When SysMin_flush() enters Hwi gate, the key returned by
* Hwi_disable() is incorrect (Its equal to Hwi disable priority
* instead of 0). This prevents the Hwi_restore() function,
* called when SysMin_flush() exits, from freeing the Hwi lock.
* Since Hwi lock is never released, the other core's dispacther
* may spin forever, waiting to acquire the Hwi lock.
*
* We Unlock Hwi before returning so all locks are released before
* exiting.
*/
if ((SysMin_flushAtExit) && (SysMin_bufSize != 0)) {
SysMin_flush();
Core_unlock();
}
}
/*
* ======== SysMin_exit ========
*/
Void SysMin_exit(Int stat)
{
if ((SysMin_flushAtExit) && (SysMin_bufSize != 0)) {
SysMin_flush();
}
}
