void timer0_stop(void)
{
TIMER0_STOP();
count0 = 0;
TCNT0 = 0;
// Clear Match A interrupt.
TIFR0 = (uint8_t)(_BV(OCF0A));
// Disable Match A interrupt.
TIMSK0 = 0;
} // End of timer0_stop().
void timer0_start(void)
{
TIMER0_STOP();
OCR0A = 250;
// Clear Match A interrupt.
TIFR0 = (uint8_t)(_BV(OCF0A));
// Enable Match A interrupt.
TIMSK0 = (uint8_t)(_BV(OCIE0A));
TIMER0_CLK64();
} // End of timer0_start().
// process the TWI command
void processTWI( void )
{
uint8_t b,c;
// receive the command
b = usiTwiReceiveByte();
switch (b) {
case CMD_01_SEGMENTS: // save brightness
// receive the 4 digits
for (c = 0 ; c < DIGIT_NUMBER ; c++)
buffer[c] = usiTwiReceiveByte();
break;
case CMD_02_BRIGHTNESS:
// receive the brightness byte
brightness = usiTwiReceiveByte(); // update the output compare A with new value
if (brightness == 0xFF)
UNSET_OCR0A_INT();
else
SET_OCR0A_INT();
break;
case CMD_03_RATE:
c = usiTwiReceiveByte();
switch (c)
{
case 0x00:
TIMER0_STOP();
break;
case 0x01:
TIMER0_SET_RATE(TIMER0_CLKDIV_4kHz);
break;
case 0x02:
TIMER0_SET_RATE(TIMER0_CLKDIV_488Hz);
break;
case 0x03:
TIMER0_SET_RATE(TIMER0_CLKDIV_61Hz);
break;
}
break;
default:
// nothing to do
break;
}
}
/**
* Starts the clock driver. This will map the memory region where the
* registers are in uncached mode, start the time stamp timer register
* and enable the interrupts for our time stamp timer and the general
* purpose timer 0.
*
* @return CLOCK_R_OK if the timer is started successfully
* CLOCK_R_FAIL if the memory region could not be mapped
*/
int start_timer(void) {
assert(!driver_initialized);
// initialize variables
timestamp_irq_tid = L4_GlobalId(NSLU2_TIMESTAMP_IRQ, 1);
timer0_irq_tid = L4_GlobalId(NSLU2_TIMER0_IRQ, 1);
registers_fpage = L4_FpageLog2(NSLU2_OSTS_PHYS_BASE, 12);
// Set up uncached memory mapping for registers
L4_Set_Rights(®isters_fpage, L4_FullyAccessible);
L4_PhysDesc_t phys = L4_PhysDesc(NSLU2_OSTS_PHYS_BASE, L4_UncachedMemory);
if(L4_MapFpage(L4_Pager(), registers_fpage, phys)) {
// enable timer0 interrupts
TIMER0_ONE_SHOT(0);
TIMER0_STOP();
(*(L4_Word_t*)OST_STATUS) |= (0x1 << 0);
int res = L4_AssociateInterrupt(timer0_irq_tid, root_thread_g);
assert(res);
// start timestamp timer
*((L4_Word_t*)OST_TS) = 0x00000000; // reset counter
// enable timestamp interrupts
(*(L4_Word_t*)OST_STATUS) |= (0x1 << 2);
res = L4_AssociateInterrupt(timestamp_irq_tid, root_thread_g);
assert(res);
driver_initialized = TRUE;
return CLOCK_R_OK;
}
else {
return CLOCK_R_FAIL;
}
}
