/**
* @brief Configure the TIMER peripheral.
* @param None
* @retval None
*/
void TIMER_Configuration(void)
{
/* TIMER1 DMA Transfer example -------------------------------------------------
TIMER1CLK = 72MHz, Prescaler = 72
TIMER1 counter clock = SystemCoreClock/72 = 1MHz.
The objective is to configure TIMER1 channel 1 to generate PWM
signal with a frequency equal to 1KHz and a variable duty cycle(25%,50%,75%) that is
changed by the DMA after a specific number of Update DMA request.
The number of this repetitive requests is defined by the TIMER1 Repetition counter,
each 2 Update Requests, the TIMER1 Channel 1 Duty Cycle changes to the next new
value defined by the buffer .
-----------------------------------------------------------------------------*/
TIMER_BaseInitPara TIMER_TimeBaseStructure;
TIMER_OCInitPara TIMER_OCInitStructure;
/* TIMERS clock enable */
RCC_APB2PeriphClock_Enable(RCC_APB2PERIPH_TIMER1|RCC_APB2PERIPH_TIMER15|RCC_APB2PERIPH_TIMER16|RCC_APB2PERIPH_TIMER17,ENABLE);
RCC_APB1PeriphClock_Enable(RCC_APB1PERIPH_TIMER2|RCC_APB1PERIPH_TIMER3|RCC_APB1PERIPH_TIMER6|RCC_APB1PERIPH_TIMER14,ENABLE);
/* TIMER1 configuration */
TIMER_DeInit(TIMER1);
TIMER_TimeBaseStructure.TIMER_Prescaler = 71;
TIMER_TimeBaseStructure.TIMER_CounterMode = TIMER_COUNTER_UP;
TIMER_TimeBaseStructure.TIMER_Period = 999;
TIMER_TimeBaseStructure.TIMER_ClockDivision = TIMER_CDIV_DIV1;
TIMER_TimeBaseStructure.TIMER_RepetitionCounter = 1;
TIMER_BaseInit(TIMER1,&TIMER_TimeBaseStructure);
/* CH1 Configuration in PWM mode */
TIMER_OCInitStructure.TIMER_OCMode = TIMER_OC_MODE_PWM1;
TIMER_OCInitStructure.TIMER_OCPolarity = TIMER_OC_POLARITY_HIGH;
TIMER_OCInitStructure.TIMER_OCNPolarity = TIMER_OCN_POLARITY_HIGH;
TIMER_OCInitStructure.TIMER_OutputState = TIMER_OUTPUT_STATE_ENABLE;
TIMER_OCInitStructure.TIMER_OutputNState = TIMER_OUTPUTN_STATE_ENABLE;
TIMER_OCInitStructure.TIMER_OCIdleState = TIMER_OC_IDLE_STATE_SET;
TIMER_OCInitStructure.TIMER_OCNIdleState = TIMER_OCN_IDLE_STATE_RESET;
TIMER_OCInitStructure.TIMER_Pulse = buffer[0];
TIMER_OC1_Init(TIMER1, &TIMER_OCInitStructure);
TIMER_OC1_Preload(TIMER1,TIMER_OC_PRELOAD_DISABLE);
/* TIMER1 output enable */
TIMER_CtrlPWMOutputs(TIMER1,ENABLE);
/* Auto-reload preload enable */
TIMER_CARLPreloadConfig(TIMER1,ENABLE);
/* TIMER1 Update DMA Request enable */
TIMER_DMACmd( TIMER1, TIMER_DMA_UPDATE, ENABLE);
/* TIMER enable counter*/
TIMER_Enable( TIMER1, ENABLE );
}
void main(void)
#endif
{
uint32_t i;
RST_CLK_DeInit();
RST_CLK_CPU_PLLconfig (RST_CLK_CPU_PLLsrcHSIdiv2,0);
/* Enable peripheral clocks --------------------------------------------------*/
RST_CLK_PCLKcmd((RST_CLK_PCLK_RST_CLK | RST_CLK_PCLK_TIMER1 | RST_CLK_PCLK_DMA),ENABLE);
RST_CLK_PCLKcmd((RST_CLK_PCLK_PORTA), ENABLE);
/* Init NVIC */
SCB->AIRCR = 0x05FA0000 | ((uint32_t)0x500);
SCB->VTOR = 0x08000000;
/* Disable all interrupt */
NVIC->ICPR[0] = 0xFFFFFFFF;
NVIC->ICER[0] = 0xFFFFFFFF;
/* Disable all DMA request */
MDR_DMA->CHNL_REQ_MASK_CLR = 0xFFFFFFFF;
MDR_DMA->CHNL_USEBURST_CLR = 0xFFFFFFFF;
/* Reset PORTB settings */
PORT_DeInit(MDR_PORTB);
/* Reset PORTF settings */
PORT_DeInit(MDR_PORTF);
/* Configure TIMER1 pins: CH1, CH2 */
/* Configure PORTA pins 1, 3 */
PORT_InitStructure.PORT_Pin = PORT_Pin_1;
PORT_InitStructure.PORT_OE = PORT_OE_OUT;
PORT_InitStructure.PORT_FUNC = PORT_FUNC_ALTER;
PORT_InitStructure.PORT_MODE = PORT_MODE_DIGITAL;
PORT_InitStructure.PORT_SPEED = PORT_SPEED_FAST;
PORT_Init(MDR_PORTA, &PORT_InitStructure);
PORT_InitStructure.PORT_Pin = PORT_Pin_3;
PORT_InitStructure.PORT_OE = PORT_OE_IN;
PORT_Init(MDR_PORTA, &PORT_InitStructure);
/* Init RAM */
Init_RAM (DstBuf, BufferSize);
/* Reset all TIMER1 settings */
TIMER_DeInit(MDR_TIMER1);
TIMER_BRGInit(MDR_TIMER1,TIMER_HCLKdiv1);
/* TIM1 configuration ------------------------------------------------*/
/* Initializes the TIMERx Counter ------------------------------------*/
sTIM_CntInit.TIMER_Prescaler = 0x10;
sTIM_CntInit.TIMER_Period = 0x200;
sTIM_CntInit.TIMER_CounterMode = TIMER_CntMode_ClkFixedDir;
sTIM_CntInit.TIMER_CounterDirection = TIMER_CntDir_Up;
sTIM_CntInit.TIMER_EventSource = TIMER_EvSrc_None;
sTIM_CntInit.TIMER_FilterSampling = TIMER_FDTS_TIMER_CLK_div_1;
sTIM_CntInit.TIMER_ARR_UpdateMode = TIMER_ARR_Update_Immediately;
sTIM_CntInit.TIMER_ETR_FilterConf = TIMER_Filter_1FF_at_TIMER_CLK;
sTIM_CntInit.TIMER_ETR_Prescaler = TIMER_ETR_Prescaler_None;
sTIM_CntInit.TIMER_ETR_Polarity = TIMER_ETRPolarity_NonInverted;
sTIM_CntInit.TIMER_BRK_Polarity = TIMER_BRKPolarity_NonInverted;
TIMER_CntInit (MDR_TIMER1,&sTIM_CntInit);
/* Initializes the TIMER1 Channel1 -------------------------------------*/
TIMER_ChnStructInit(&sTIM_ChnInit);
sTIM_ChnInit.TIMER_CH_Number = TIMER_CHANNEL1;
sTIM_ChnInit.TIMER_CH_Mode = TIMER_CH_MODE_PWM;
sTIM_ChnInit.TIMER_CH_REF_Format = TIMER_CH_REF_Format3;
TIMER_ChnInit(MDR_TIMER1, &sTIM_ChnInit);
TIMER_SetChnCompare(MDR_TIMER1, TIMER_CHANNEL1, 0x100);
/* Initializes the TIMER1 Channel1 Output -------------------------------*/
TIMER_ChnOutStructInit(&sTIM_ChnOutInit);
sTIM_ChnOutInit.TIMER_CH_Number = TIMER_CHANNEL1;
sTIM_ChnOutInit.TIMER_CH_DirOut_Polarity = TIMER_CHOPolarity_NonInverted;
sTIM_ChnOutInit.TIMER_CH_DirOut_Source = TIMER_CH_OutSrc_REF;
sTIM_ChnOutInit.TIMER_CH_DirOut_Mode = TIMER_CH_OutMode_Output;
TIMER_ChnOutInit(MDR_TIMER1, &sTIM_ChnOutInit);
/* Initializes the TIMER1 Channel2 -------------------------------------*/
TIMER_ChnStructInit(&sTIM_ChnInit);
sTIM_ChnInit.TIMER_CH_Number = TIMER_CHANNEL2;
sTIM_ChnInit.TIMER_CH_Mode = TIMER_CH_MODE_CAPTURE;
TIMER_ChnInit(MDR_TIMER1, &sTIM_ChnInit);
/* Initializes the TIMER1 Channel2 Output -------------------------------*/
TIMER_ChnOutStructInit(&sTIM_ChnOutInit);
sTIM_ChnOutInit.TIMER_CH_Number = TIMER_CHANNEL2;
sTIM_ChnOutInit.TIMER_CH_DirOut_Polarity = TIMER_CHOPolarity_NonInverted;
sTIM_ChnOutInit.TIMER_CH_DirOut_Source = TIMER_CH_OutSrc_Only_0;
sTIM_ChnOutInit.TIMER_CH_DirOut_Mode = TIMER_CH_OutMode_Input;
TIMER_ChnOutInit(MDR_TIMER1, &sTIM_ChnOutInit);
/* Enable TIMER1 DMA request */
TIMER_DMACmd(MDR_TIMER1,(TIMER_STATUS_CCR_CAP_CH2), ENABLE);
/* Reset all DMA settings */
DMA_DeInit();
DMA_StructInit(&DMA_InitStr);
/* DMA_Channel_TIM1 configuration ---------------------------------*/
/* Set Primary Control Data */
DMA_PriCtrlStr.DMA_SourceBaseAddr = (uint32_t)(&(MDR_TIMER1->CCR2));
DMA_PriCtrlStr.DMA_DestBaseAddr = (uint32_t)DstBuf;
DMA_PriCtrlStr.DMA_SourceIncSize = DMA_SourceIncNo;
DMA_PriCtrlStr.DMA_DestIncSize = DMA_DestIncHalfword;
DMA_PriCtrlStr.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
DMA_PriCtrlStr.DMA_Mode = DMA_Mode_Basic;
DMA_PriCtrlStr.DMA_CycleSize = BufferSize;
DMA_PriCtrlStr.DMA_NumContinuous = DMA_Transfers_1;
DMA_PriCtrlStr.DMA_SourceProtCtrl = DMA_SourcePrivileged;
DMA_PriCtrlStr.DMA_DestProtCtrl = DMA_DestPrivileged;
/* Set Channel Structure */
DMA_InitStr.DMA_PriCtrlData = &DMA_PriCtrlStr;
DMA_InitStr.DMA_Priority = DMA_Priority_High;
DMA_InitStr.DMA_UseBurst = DMA_BurstClear;
DMA_InitStr.DMA_SelectDataStructure = DMA_CTRL_DATA_PRIMARY;
/* Init DMA channel */
DMA_Init(DMA_Channel_TIM1, &DMA_InitStr);
/* Enable TIMER1 */
TIMER_Cmd(MDR_TIMER1,ENABLE);
/* Transfer complete */
while((DMA_GetFlagStatus(DMA_Channel_TIM1, DMA_FLAG_CHNL_ENA)))
{
}
/* Check the corectness of written dada */
for(i = 0; i < BufferSize; i++)
{
if (DstBuf[i] != MDR_TIMER1->CCR1)
{
TransferStatus &= FAILED;
break;
}
else
{
TransferStatus = PASSED;
}
}
/* TransferStatus = PASSED, if the data transmitted are correct */
/* TransferStatus = FAILED, if the data transmitted are not correct */
while(1)
{
}
}
void main(void)
#endif
{
RST_CLK_DeInit();
RST_CLK_CPU_PLLconfig (RST_CLK_CPU_PLLsrcHSIdiv2,0);
/* Enable peripheral clocks --------------------------------------------------*/
RST_CLK_PCLKcmd((RST_CLK_PCLK_RST_CLK | RST_CLK_PCLK_DMA | RST_CLK_PCLK_PORTE),ENABLE);
RST_CLK_PCLKcmd((RST_CLK_PCLK_TIMER1 | RST_CLK_PCLK_DAC),ENABLE);
RST_CLK_PCLKcmd((RST_CLK_PCLK_SSP1 | RST_CLK_PCLK_SSP2),ENABLE);
/* Disable all interrupt */
NVIC->ICPR[0] = 0xFFFFFFFF;
NVIC->ICER[0] = 0xFFFFFFFF;
/* Reset PORTE settings */
PORT_DeInit(MDR_PORTE);
/* Configure DAC pin: DAC1_OUT */
/* Configure PORTE pin 9 */
PORT_InitStructure.PORT_Pin = PORT_Pin_2;
PORT_InitStructure.PORT_OE = PORT_OE_OUT;
PORT_InitStructure.PORT_MODE = PORT_MODE_ANALOG;
PORT_Init(MDR_PORTE, &PORT_InitStructure);
/* DMA Configuration */
/* Reset all DMA settings */
DMA_DeInit();
DMA_StructInit(&DMA_InitStr);
/* Set Primary Control Data */
DMA_PriCtrlStr.DMA_SourceBaseAddr = (uint32_t)Sine12bit;
DMA_PriCtrlStr.DMA_DestBaseAddr = (uint32_t)(&(MDR_DAC->DAC1_DATA));
DMA_PriCtrlStr.DMA_SourceIncSize = DMA_SourceIncHalfword;
DMA_PriCtrlStr.DMA_DestIncSize = DMA_DestIncNo;
DMA_PriCtrlStr.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
DMA_PriCtrlStr.DMA_Mode = DMA_Mode_PingPong;
DMA_PriCtrlStr.DMA_CycleSize = 32;
DMA_PriCtrlStr.DMA_NumContinuous = DMA_Transfers_1;
DMA_PriCtrlStr.DMA_SourceProtCtrl = DMA_SourcePrivileged;
DMA_PriCtrlStr.DMA_DestProtCtrl = DMA_DestPrivileged;
/* Set Alternate Control Data */
DMA_AltCtrlStr.DMA_SourceBaseAddr = (uint32_t)Sine12bit;
DMA_AltCtrlStr.DMA_DestBaseAddr = (uint32_t)(&(MDR_DAC->DAC1_DATA));
DMA_AltCtrlStr.DMA_SourceIncSize = DMA_SourceIncHalfword;
DMA_AltCtrlStr.DMA_DestIncSize = DMA_DestIncNo;
DMA_AltCtrlStr.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
DMA_AltCtrlStr.DMA_Mode = DMA_Mode_PingPong;
DMA_AltCtrlStr.DMA_CycleSize = 32;
DMA_AltCtrlStr.DMA_NumContinuous = DMA_Transfers_1;
DMA_AltCtrlStr.DMA_SourceProtCtrl = DMA_SourcePrivileged;
DMA_AltCtrlStr.DMA_DestProtCtrl = DMA_DestPrivileged;
/* Set Channel Structure */
DMA_InitStr.DMA_PriCtrlData = &DMA_PriCtrlStr;
DMA_InitStr.DMA_AltCtrlData = &DMA_AltCtrlStr;
DMA_InitStr.DMA_Priority = DMA_Priority_Default;
DMA_InitStr.DMA_UseBurst = DMA_BurstClear;
DMA_InitStr.DMA_SelectDataStructure = DMA_CTRL_DATA_PRIMARY;
/* Init DMA channel TIM1*/
DMA_Init(DMA_Channel_REQ_TIM1, &DMA_InitStr);
/* Enable dma_req or dma_sreq to generate DMA request */
MDR_DMA->CHNL_REQ_MASK_CLR = DMA_SELECT(DMA_Channel_REQ_TIM1);
MDR_DMA->CHNL_USEBURST_CLR = DMA_SELECT(DMA_Channel_REQ_TIM1);
/* Enable DMA_Channel_TIM1 */
DMA_Cmd(DMA_Channel_REQ_TIM1, ENABLE);
/* ADC Configuration */
/* Reset all ADC settings */
DAC_DeInit();
/* DAC channel1 Configuration */
DAC1_Init(DAC1_AVCC);
/* DAC channel1 enable */
DAC1_Cmd(ENABLE);
/* TIMER1 Configuration */
/* Time base configuration */
TIMER_DeInit(MDR_TIMER1);
TIMER_BRGInit(MDR_TIMER1,TIMER_HCLKdiv1);
sTIM_CntInit.TIMER_Prescaler = 0;
sTIM_CntInit.TIMER_Period = 0xFF;
sTIM_CntInit.TIMER_CounterMode = TIMER_CntMode_ClkFixedDir;
sTIM_CntInit.TIMER_CounterDirection = TIMER_CntDir_Up;
sTIM_CntInit.TIMER_EventSource = TIMER_EvSrc_None;
sTIM_CntInit.TIMER_FilterSampling = TIMER_FDTS_TIMER_CLK_div_1;
sTIM_CntInit.TIMER_ARR_UpdateMode = TIMER_ARR_Update_Immediately;
sTIM_CntInit.TIMER_ETR_FilterConf = TIMER_Filter_1FF_at_TIMER_CLK;
sTIM_CntInit.TIMER_ETR_Prescaler = TIMER_ETR_Prescaler_None;
sTIM_CntInit.TIMER_ETR_Polarity = TIMER_ETRPolarity_NonInverted;
sTIM_CntInit.TIMER_BRK_Polarity = TIMER_BRKPolarity_NonInverted;
TIMER_CntInit (MDR_TIMER1,&sTIM_CntInit);
/* Enable DMA for TIMER1 */
TIMER_DMACmd(MDR_TIMER1, TIMER_STATUS_CNT_ARR, TIMER_DMA_Channel0, ENABLE);
/* TIMER1 enable counter */
TIMER_Cmd(MDR_TIMER1,ENABLE);
/* Enable DMA IRQ */
NVIC_EnableIRQ(DMA_IRQn);
/* Infinite loop */
while(1)
{
}
}
