static int __init sun5i_setup_clocksource(struct device_node *node, void __iomem *base, struct clk *clk, int irq) { struct sun5i_timer_clksrc *cs; unsigned long rate; int ret; cs = kzalloc(sizeof(*cs), GFP_KERNEL); if (!cs) return -ENOMEM; ret = clk_prepare_enable(clk); if (ret) { pr_err("Couldn't enable parent clock\n"); goto err_free; } rate = clk_get_rate(clk); cs->timer.base = base; cs->timer.clk = clk; cs->timer.clk_rate_cb.notifier_call = sun5i_rate_cb_clksrc; cs->timer.clk_rate_cb.next = NULL; ret = clk_notifier_register(clk, &cs->timer.clk_rate_cb); if (ret) { pr_err("Unable to register clock notifier.\n"); goto err_disable_clk; } writel(~0, base + TIMER_INTVAL_LO_REG(1)); writel(TIMER_CTL_ENABLE | TIMER_CTL_RELOAD, base + TIMER_CTL_REG(1)); cs->clksrc.name = node->name; cs->clksrc.rating = 340; cs->clksrc.read = sun5i_clksrc_read; cs->clksrc.mask = CLOCKSOURCE_MASK(32); cs->clksrc.flags = CLOCK_SOURCE_IS_CONTINUOUS; ret = clocksource_register_hz(&cs->clksrc, rate); if (ret) { pr_err("Couldn't register clock source.\n"); goto err_remove_notifier; } return 0; err_remove_notifier: clk_notifier_unregister(clk, &cs->timer.clk_rate_cb); err_disable_clk: clk_disable_unprepare(clk); err_free: kfree(cs); return ret; }
static void __init sun5i_timer_init(struct device_node *node) { struct reset_control *rstc; unsigned long rate; struct clk *clk; int ret, irq; u32 val; timer_base = of_iomap(node, 0); if (!timer_base) panic("Can't map registers"); irq = irq_of_parse_and_map(node, 0); if (irq <= 0) panic("Can't parse IRQ"); clk = of_clk_get(node, 0); if (IS_ERR(clk)) panic("Can't get timer clock"); clk_prepare_enable(clk); rate = clk_get_rate(clk); rstc = of_reset_control_get(node, NULL); if (!IS_ERR(rstc)) reset_control_deassert(rstc); writel(~0, timer_base + TIMER_INTVAL_LO_REG(1)); writel(TIMER_CTL_ENABLE | TIMER_CTL_RELOAD, timer_base + TIMER_CTL_REG(1)); sched_clock_register(sun5i_timer_sched_read, 32, rate); clocksource_mmio_init(timer_base + TIMER_CNTVAL_LO_REG(1), node->name, rate, 340, 32, clocksource_mmio_readl_down); ticks_per_jiffy = DIV_ROUND_UP(rate, HZ); ret = setup_irq(irq, &sun5i_timer_irq); if (ret) pr_warn("failed to setup irq %d\n", irq); /* Enable timer0 interrupt */ val = readl(timer_base + TIMER_IRQ_EN_REG); writel(val | TIMER_IRQ_EN(0), timer_base + TIMER_IRQ_EN_REG); sun5i_clockevent.cpumask = cpu_possible_mask; sun5i_clockevent.irq = irq; clockevents_config_and_register(&sun5i_clockevent, rate, TIMER_SYNC_TICKS, 0xffffffff); }
static void sun5i_clkevt_time_setup(struct sun5i_timer_clkevt *ce, u8 timer, u32 delay) { writel(delay, ce->timer.base + TIMER_INTVAL_LO_REG(timer)); }
static void sun5i_clkevt_time_setup(u8 timer, u32 delay) { writel(delay, timer_base + TIMER_INTVAL_LO_REG(timer)); }