void Pwm_stm32::write_channel(void) { //select the output period if (TIM_ARR(timer_) > period_) { print_util_dbg_print("should keep slower period.\r\n"); } else { TIM_ARR(timer_) = period_; } if(channel_id_ == PWM_STM32_CHANNEL_1) { //select duty cycle TIM_CCR1(timer_) = duty_cyle_; } else if(channel_id_ == PWM_STM32_CHANNEL_2) { //select duty cycle TIM_CCR2(timer_) = duty_cyle_; } else if(channel_id_ == PWM_STM32_CHANNEL_3) { //select duty cycle TIM_CCR3(timer_) = duty_cyle_; } else if(channel_id_ == PWM_STM32_CHANNEL_4) { //select duty cycle TIM_CCR4(timer_) = duty_cyle_; } }
void setLEDColor(uint8_t red, uint8_t green, uint8_t blue) { if (false == g_isRedBlinking) { int cnt = TIM_CNT(RGB_TIMER); TIM_CCR1(RGB_TIMER) = TIM_ARR(RGB_TIMER) - green; TIM_CCR2(RGB_TIMER) = TIM_ARR(RGB_TIMER) - red; int tim_ccr1 = TIM_CCR1(RGB_TIMER); int tim_ccr2 = TIM_CCR2(RGB_TIMER); UNUSED(tim_ccr1); UNUSED(tim_ccr2); UNUSED(cnt); if (0 == blue) { gpio_set(LED_PORT, LED_B_PIN); } else { gpio_clear(LED_PORT, LED_B_PIN); } } }
void tim1_cc_isr(void) { if(timer_get_flag(TIM1, TIM_SR_CC2IF)) { int ccr = TIM_CCR2(TIM1); int save_n_overflow = n_overflow; n_overflow = 0; int delta = (ccr + (save_n_overflow<<16)) - last_ccr; if(dma_enabled) start_dma(); timer_clear_flag(TIM1, TIM_SR_CC2IF); //gpio_set(DEBUG0_OUT_PORT, DEBUG0_OUT_PIN); //gpio_clear(DEBUG0_OUT_PORT, DEBUG0_OUT_PIN); last_ccr = ccr; int speed_delta = motor_ctrl_step(delta); // Wait for motor speed to get stable. if(!dma_enabled && speed_delta > -10 && speed_delta < 10) { if(motor_ok == 0) { set_status(LED_GREEN, 1); set_status(LED_RED, 0); dma_enabled = 1; } else { motor_ok--; } } if(dma_enabled && (speed_delta < -100 || speed_delta > 100)) { set_status(LED_GREEN, 0); set_status(LED_RED, 1); dma_enabled = 0; motor_ok = 16; } if(delta < 100) { gpio_set(GPIOB, GPIO0); __asm("nop"); __asm("nop"); __asm("nop"); __asm("nop"); gpio_clear(GPIOB, GPIO0); } } }
void timer_set_oc_value(u32 timer_peripheral, enum tim_oc_id oc_id, u32 value) { switch (oc_id) { case TIM_OC1: TIM_CCR1(timer_peripheral) = value; break; case TIM_OC2: TIM_CCR2(timer_peripheral) = value; break; case TIM_OC3: TIM_CCR3(timer_peripheral) = value; break; case TIM_OC4: TIM_CCR4(timer_peripheral) = value; break; case TIM_OC1N: case TIM_OC2N: case TIM_OC3N: /* Ignoring as this option applies to the whole channel. */ break; } }
static int timer_dma(uint8_t *tx_buf, int tx_len) { dma_int_enable(); /* Reset DMA channels*/ dma_channel_reset(DMA1, DMA_CHANNEL3); /* Set up tx dma */ dma_set_peripheral_address(DMA1, DMA_CHANNEL3, (uint32_t)&TIM_CCR2(TIM3)); dma_set_memory_address(DMA1, DMA_CHANNEL3, (uint32_t)tx_buf); dma_set_number_of_data(DMA1, DMA_CHANNEL3, tx_len); dma_set_read_from_memory(DMA1, DMA_CHANNEL3); dma_enable_memory_increment_mode(DMA1, DMA_CHANNEL3); dma_set_peripheral_size(DMA1, DMA_CHANNEL3, DMA_CCR_PSIZE_32BIT); dma_set_memory_size(DMA1, DMA_CHANNEL3, DMA_CCR_MSIZE_8BIT); dma_set_priority(DMA1, DMA_CHANNEL3, DMA_CCR_PL_HIGH); dma_enable_circular_mode(DMA1, DMA_CHANNEL3); dma_enable_transfer_complete_interrupt(DMA1, DMA_CHANNEL3); dma_enable_half_transfer_interrupt(DMA1, DMA_CHANNEL3); dma_enable_channel(DMA1, DMA_CHANNEL3); return 0; }
bool Pwm_stm32::init(void) { bool success = true; /* Enable peripheral port & TIM clock. */ //rcc_periph_clock_enable(RCC_GPIOx); rcc_periph_clock_enable(pwm_config_.rcc_timer_config); gpio_mode_setup(pwm_config_.gpio_config.port, GPIO_MODE_AF, GPIO_PUPD_NONE, pwm_config_.gpio_config.pin); gpio_set_af(pwm_config_.gpio_config.port, pwm_config_.gpio_config.alt_fct, pwm_config_.gpio_config.pin); gpio_set_output_options(pwm_config_.gpio_config.port, GPIO_OTYPE_PP, GPIO_OSPEED_100MHZ, pwm_config_.gpio_config.port); //WARNING Common to all channels of that TIMER //select prescaler TIM_PSC(pwm_config_.timer_config) = prescaler_; //select the output period TIM_ARR(pwm_config_.timer_config) = period_; //enable the autoreload TIM_CR1(pwm_config_.timer_config) |= TIM_CR1_ARPE; //select counting mode (edge-aligned) TIM_CR1(pwm_config_.timer_config) |= TIM_CR1_CMS_EDGE; //counting up TIM_CR1(pwm_config_.timer_config) |= TIM_CR1_DIR_UP; //enable counter TIM_CR1(pwm_config_.timer_config) |= TIM_CR1_CEN; //CHANNEL SPECIFIC if (pwm_config_.channel_config == PWM_STM32_CHANNEL_1) { //Disable channel1 TIM_CCER(pwm_config_.timer_config) &= (uint16_t)~TIM_CCER_CC1E; //Reset output compare TIM_CCMR1(pwm_config_.timer_config) &= (uint16_t)~TIM_CCMR1_OC1M_MASK; TIM_CCMR1(pwm_config_.timer_config) &= (uint16_t)~TIM_CCMR1_CC1S_MASK; //Select output mode TIM_CCMR1(pwm_config_.timer_config) |= TIM_CCMR1_CC1S_OUT; //select polarity low TIM_CCER(pwm_config_.timer_config) |= TIM_CCER_CC1NP; //select PWM mode 1 TIM_CCMR1(pwm_config_.timer_config) |= TIM_CCMR1_OC1M_PWM1; //select duty cycle TIM_CCR1(pwm_config_.timer_config) = duty_cyle_; //set the preload bit TIM_CCMR1(pwm_config_.timer_config) |= TIM_CCMR1_OC1PE; //enable capture/compare TIM_CCER(pwm_config_.timer_config) |= TIM_CCER_CC1E; } else if (pwm_config_.channel_config == PWM_STM32_CHANNEL_2) { //Disable channel2 TIM_CCER(pwm_config_.timer_config) &= (uint16_t)~TIM_CCER_CC2E; //Reset output compare TIM_CCMR1(pwm_config_.timer_config) &= (uint16_t)~TIM_CCMR1_OC2M_MASK; TIM_CCMR1(pwm_config_.timer_config) &= (uint16_t)~TIM_CCMR1_CC2S_MASK; //Select output mode TIM_CCMR1(pwm_config_.timer_config) |= TIM_CCMR1_CC2S_OUT; //select polarity low TIM_CCER(pwm_config_.timer_config) |= TIM_CCER_CC2NP; //select PWM mode 1 TIM_CCMR1(pwm_config_.timer_config) |= TIM_CCMR1_OC2M_PWM1; //select duty cycle TIM_CCR2(pwm_config_.timer_config) = duty_cyle_; //set the preload bit TIM_CCMR1(pwm_config_.timer_config) |= TIM_CCMR1_OC2PE; //enable capture/compare TIM_CCER(pwm_config_.timer_config) |= TIM_CCER_CC2E; } else if (pwm_config_.channel_config == PWM_STM32_CHANNEL_3) { //Disable channel3 TIM_CCER(pwm_config_.timer_config) &= (uint16_t)~TIM_CCER_CC3E; //Reset output compare TIM_CCMR2(pwm_config_.timer_config) &= (uint16_t)~TIM_CCMR2_OC3M_MASK; TIM_CCMR2(pwm_config_.timer_config) &= (uint16_t)~TIM_CCMR2_CC3S_MASK; //Select output mode TIM_CCMR2(pwm_config_.timer_config) |= TIM_CCMR2_CC3S_OUT; //select polarity low TIM_CCER(pwm_config_.timer_config) |= TIM_CCER_CC3NP; //select PWM mode 1 TIM_CCMR2(pwm_config_.timer_config) |= TIM_CCMR2_OC3M_PWM1; //select duty cycle TIM_CCR3(pwm_config_.timer_config) = duty_cyle_; //set the preload bit TIM_CCMR2(pwm_config_.timer_config) |= TIM_CCMR2_OC3PE; //enable capture/compare TIM_CCER(pwm_config_.timer_config) |= TIM_CCER_CC3E; } else if (pwm_config_.channel_config == PWM_STM32_CHANNEL_4) { //Disable channel4 TIM_CCER(pwm_config_.timer_config) &= (uint16_t)~TIM_CCER_CC4E; //Reset output compare TIM_CCMR2(pwm_config_.timer_config) &= (uint16_t)~TIM_CCMR2_OC4M_MASK; TIM_CCMR2(pwm_config_.timer_config) &= (uint16_t)~TIM_CCMR2_CC4S_MASK; //Select output mode TIM_CCMR2(pwm_config_.timer_config) |= TIM_CCMR2_CC4S_OUT; //select polarity low TIM_CCER(pwm_config_.timer_config) |= (1 << 15); //TODO TIM_CCER_CC4NP does not exist in libopencm3 library //select PWM mode 1 TIM_CCMR2(pwm_config_.timer_config) |= TIM_CCMR2_OC4M_PWM1; //select duty cycle TIM_CCR4(pwm_config_.timer_config) = duty_cyle_; //set the preload bit TIM_CCMR2(pwm_config_.timer_config) |= TIM_CCMR2_OC4PE; //enable capture/compare TIM_CCER(pwm_config_.timer_config) |= TIM_CCER_CC4E; } return success; }