//-----------------------------------------------------------------------------
// void RFSendPacket(char *txBuffer, char size)
//
// DESCRIPTION:
// This function transmits a packet with length up to 63 bytes. To use this
// function, GD00 must be configured to be asserted when sync word is sent and
// de-asserted at the end of the packet, which is accomplished by setting the
// IOCFG0 register to 0x06, per the CCxxxx datasheet. GDO0 goes high at
// packet start and returns low when complete. The function polls GDO0 to
// ensure packet completion before returning.
//
// ARGUMENTS:
// char *txBuffer
// Pointer to a buffer containing the data to be transmitted
//
// char size
// The size of the txBuffer
//-----------------------------------------------------------------------------
void RFSendPacket(char *txBuffer, char size)
{
// the following code is "borrowed" from MRFI
TI_CC_GDO0_PxIE &= ~TI_CC_GDO0_PIN; // disable receive interrupts
TI_CC_SPIStrobe(TI_CCxxx0_SFRX); // flush the receive FIFO of any residual data
TI_CC_SPIStrobe(TI_CCxxx0_SIDLE); // set IDLE
// done MRFI code. Hopefully it works well
TI_CC_SPIWriteBurstReg(TI_CCxxx0_TXFIFO, txBuffer, size); // Write TX data
TI_CC_SPIStrobe(TI_CCxxx0_STX); // Change state to TX, initiating
// data transfer
while (!(TI_CC_GDO0_PxIN&TI_CC_GDO0_PIN));
// Wait GDO0 to go hi -> sync TX'ed
while (TI_CC_GDO0_PxIN&TI_CC_GDO0_PIN);
TI_CC_SPIStrobe(TI_CCxxx0_SFTX); // flush the FIFO for a clean state
// taken from MRFI;
// Wait GDO0 to clear -> end of pkt
TI_CC_GDO0_PxIFG &= ~TI_CC_GDO0_PIN; // After pkt TX, this flag is set.
// Has to be cleared before existing
TI_CC_GDO0_PxIE |= TI_CC_GDO0_PIN; // re-enable receive interrupts
}
void ModeTransmissio(void) {
TI_CC_SPIStrobe(TI_CCxxx0_SIDLE);
TI_CC_SPIStrobe(TI_CCxxx0_STX); // Initialize CCxxxx in TX mode.
IoWait(900);
// Comprovo que hagi entrat en mode de transmissió, ja que tenim el CCA activat
RadioMode=TX_Mode;
}
//-----------------------------------------------------------------------------
// void RFSendPacket(char *txBuffer, char size)
//
// DESCRIPTION:
// This function transmits a packet with length up to 63 bytes. To use this
// function, GD00 must be configured to be asserted when sync word is sent and
// de-asserted at the end of the packet, which is accomplished by setting the
// IOCFG0 register to 0x06, per the CCxxxx datasheet. GDO0 goes high at
// packet start and returns low when complete. The function polls GDO0 to
// ensure packet completion before returning.
//
// ARGUMENTS:
// char *txBuffer
// Pointer to a buffer containing the data to be transmitted
//
// char size
// The size of the txBuffer
//-----------------------------------------------------------------------------
void RFSendPacket(char *txBuffer, char size)
{
// TI_CC_SPIWriteBurstReg(TI_CCxxx0_TXFIFO, txBuffer, size); // Write TX data
// TI_CC_SPIStrobe(TI_CCxxx0_STX); // Change state to TX, initiating
// // data transfer
//
// while (!(TI_CC_GDO0_PxIN&TI_CC_GDO0_PIN));
// // Wait GDO0 to go hi -> sync TX'ed
// while (TI_CC_GDO0_PxIN&TI_CC_GDO0_PIN);
// // Wait GDO0 to clear -> end of pkt
// TI_CC_GDO0_PxIFG &= ~TI_CC_GDO0_PIN; // After pkt TX, this flag is set.
// // Has to be cleared before existing
// added 20120123 based on ANAREN code
TI_CC_SPIStrobe(TI_CCxxx0_SIDLE); // set to IDLE
TI_CC_SPIStrobe(TI_CCxxx0_SFRX); // Flush RX
TI_CC_SPIStrobe(TI_CCxxx0_SFTX); // Flush TX
// end new 20120123
TI_CC_SPIWriteBurstReg(TI_CCxxx0_TXFIFO, txBuffer, size); // Write TX packet structure data
TI_CC_SPIStrobe(TI_CCxxx0_STX); // Change state to TX, initiating data transfer
while (!(TI_CC_GDO0_PxIN&TI_CC_GDO0_PIN)); // Wait GDO0 to go hi -> sync TX'ed
while (TI_CC_GDO0_PxIN&TI_CC_GDO0_PIN); // Wait GDO0 to clear -> end of pkt
TI_CC_SPIStrobe(TI_CCxxx0_SRX); // Change state to RX after sending
TI_CC_GDO0_PxIFG &= ~TI_CC_GDO0_PIN; // After pkt TX, this interrupt flag is set.
// Has to be cleared before exiting
}
// Contributed by Cor
void Radio_WakeUp()
{
TI_CC_CSn_PxOUT &= ~TI_CC_CSn_PIN; // /CS low
while (TI_CC_SPI_USCIB0_PxIN & TI_CC_SPI_USCIB0_SOMI); //wait till P1.6 goes low
TI_CC_CSn_PxOUT |= TI_CC_CSn_PIN; // /CS high
// write some test setting back;
TI_CC_SPIWriteReg(TI_CCxxx0_TEST2, 0x88); // Various test settings.
TI_CC_SPIWriteReg(TI_CCxxx0_TEST1, 0x31); // Various test settings.
TI_CC_SPIWriteReg(TI_CCxxx0_TEST0, 0x0B); // Various test settings.
TI_CC_SPIStrobe(TI_CCxxx0_SFRX); // flush the receive FIFO of any residual data
TI_CC_SPIStrobe(TI_CCxxx0_SIDLE); // set IDLE
}
//-----------------------------------------------------------------------------
char RFReceivePacket(char *rxBuffer, char *length)
{
char pktLen;
if ((TI_CC_SPIReadStatus(TI_CCxxx0_RXBYTES) & TI_CCxxx0_NUM_RXBYTES)) {
pktLen = TI_CC_SPIReadReg(TI_CCxxx0_RXFIFO); // Quantes dades hi ha?
#ifdef LSMAKER_BASE
// LS_USB_printf("\r\nLenR %d LenE %d\r\n", pktLen, *length);
#endif
if ((pktLen <= *length) && (pktLen > 0)) { // Suficients=
TI_CC_SPIReadBurstReg(TI_CCxxx0_RXFIFO, rxBuffer, pktLen+2); // Llegeix les dades + 2 d'estat
*length = pktLen; // Returna el tamany real
RssiAct = rxBuffer[LengthDATA]; // El primer byte indica el RSSI
LQIAct = rxBuffer[LengthDATA+TI_CCxxx0_LQI_RX] & 0x7f; // I el segon l'indicador de qualitat de l'enllaç
ModeRecepcio();
return (char)(rxBuffer[LengthDATA+TI_CCxxx0_LQI_RX]&TI_CCxxx0_CRC_OK); // Return CRC_OK bit
} else {
*length = pktLen; // Return the large size
TI_CC_SPIStrobe(TI_CCxxx0_SFRX); // Flush RXFIFO
IoWait(2);
ModeRecepcio();
return 0; // Error
}
} else {
ModeRecepcio();
return 0; // Error
}
return 0;
}
int main(int argc, char ** argv) {
int res;
printf("Start rpiCC2500\n");
TICC *cc = (TICC *) malloc(sizeof(TICC));
res = CC_Init(cc, "/dev/spidev0.0", 25 /*GNO0-pin Not yet used*/);
if (res < 0) {
printf("Failed to init TICC.");
return 1;
}
perror("SPI init");
usleep(30000);
TI_CC_SPIStrobe( cc->fd, TI_CCxxx0_SRES);
printf("Wait for RF to be Ready\n");
usleep(40);
printf("RF ok\n");
writeRFSettings(cc);
printf("BurstReg\n");
TI_CC_SPIWriteBurstReg(cc->fd, TI_CCxxx0_PATABLE, paTable, paTableLen);
printf("Strobe\n");
//TI_CC_SPIStrobe(cc->fd, TI_CCxxx0_SRX); // Initialize CCxxxx in RX mode.
// When a pkt is received, it will
// signal on GDO0
char rxBuffer[50];
printf("entering LOOP\n");
printf("Part No.: %d\n",TI_CC_SPIReadStatus(cc->fd, TI_CCxxx0_PARTNUM));
printf("Version No.: %d\n",TI_CC_SPIReadStatus(cc->fd, TI_CCxxx0_VERSION));
char len = 50;
int j,i;
for(j=0;j<10;j++){ // for now send every 500ms a message and check for received packages
rxBuffer[0] =3;
rxBuffer[1] =0x01;
rxBuffer[2] =12;
rxBuffer[3] =rxBuffer[1]^rxBuffer[2]^0x01;
printf("Send Package\n");
RFSendPacket(cc, rxBuffer, 4);
usleep(500000);
printf("Check for Package\n");
while(RFReceivePacket(cc, rxBuffer, &len)){
printf("Got A Package %d\n",len);
for(i =0; i< len; i++){
printf("%d ",rxBuffer[i]);
}
printf("\n");
//Receiveddata are stored in rxBuffer
//Put some intelligence here
len = 50;
}
}
printf("exiting LOOP\n");
CC_dispose(cc);
free(cc);
return 0;
}
//-----------------------------------------------------------------------------
// char RFReceivePacket(char *rxBuffer, char *length)
//
// DESCRIPTION:
// Receives a packet of variable length (first byte in the packet must be the
// length byte). The packet length should not exceed the RXFIFO size. To use
// this function, APPEND_STATUS in the PKTCTRL1 register must be enabled. It
// is assumed that the function is called after it is known that a packet has
// been received; for example, in response to GDO0 going low when it is
// configured to output packet reception status.
//
// The RXBYTES register is first read to ensure there are bytes in the FIFO.
// This is done because the GDO signal will go high even if the FIFO is flushed
// due to address filtering, CRC filtering, or packet length filtering.
//
// ARGUMENTS:
// char *rxBuffer
// Pointer to the buffer where the incoming data should be stored
// char *length
// Pointer to a variable containing the size of the buffer where the
// incoming data should be stored. After this function returns, that
// variable holds the packet length.
//
// RETURN VALUE:
// char
// 0x80: CRC OK
// 0x00: CRC NOT OK (or no pkt was put in the RXFIFO due to filtering)
//-----------------------------------------------------------------------------
char RFReceivePacket(char *rxBuffer, char *length, char *retStatus)
{
char status[2];
char pktLen;
if ((TI_CC_SPIReadStatus(TI_CCxxx0_RXBYTES) & TI_CCxxx0_NUM_RXBYTES))
{
pktLen = TI_CC_SPIReadReg(TI_CCxxx0_RXFIFO); // Read length byte
if (pktLen <= *length) // If pktLen size <= rxBuffer
{
TI_CC_SPIReadBurstReg(TI_CCxxx0_RXFIFO, rxBuffer, pktLen); // Pull data
*length = pktLen; // Return the actual size
TI_CC_SPIReadBurstReg(TI_CCxxx0_RXFIFO, status, 2); // Read appended status bytes
if (retStatus){
retStatus[0]=status[0];
retStatus[1]=status[1];
}
return (char)(status[TI_CCxxx0_LQI_RX]&TI_CCxxx0_CRC_OK);
} // Return CRC_OK bit
else
{
*length = pktLen; // Return the large size
TI_CC_SPIStrobe(TI_CCxxx0_SFRX); // Flush RXFIFO
return 0; // Error
}
}
else
return 0; // Error
}
void RF_init()
{
TI_CC_SPISetup(); // Initialize SPI port
TI_CC_PowerupResetCCxxxx(); // Reset CCxxxx
writeRFSettings(); // Write RF settings to config reg
TI_CC_SPIWriteBurstReg(TI_CCxxx0_PATABLE, paTable, paTableLen);//Write PATABLE
//TI_CC_SPIStrobe(TI_CCxxx0_SIDLE); // set IDLE
TI_CC_SPIWriteReg (TI_CCxxx0_PATABLE,paTable[0]); // init at max powerlevel
// Configure ports -- switch inputs, LEDs, GDO0 to RX packet info from CCxxxx
TI_CC_SW_PxREN |= TI_CC_SW1; // Enable Pull up resistor
TI_CC_SW_PxOUT |= TI_CC_SW1; // Enable pull up resistor
TI_CC_SW_PxIES |= TI_CC_SW1; // Int on falling edge
TI_CC_SW_PxIFG &= ~(TI_CC_SW1); // Clr flags
TI_CC_SW_PxIE |= TI_CC_SW1; // Activate interrupt enables
TI_CC_GDO0_PxIES |= TI_CC_GDO0_PIN; // Int on falling edge (end of pkt)
TI_CC_GDO0_PxIFG &= ~TI_CC_GDO0_PIN; // Clear flag
TI_CC_GDO0_PxIE |= TI_CC_GDO0_PIN; // Enable int on end of packet
TI_CC_SPIStrobe(TI_CCxxx0_SRX); // Initialize CCxxxx in RX mode.
// When a pkt is received, it will
// signal on GDO0 and wake CPU
}
void main (void)
{
WDTCTL = WDTPW + WDTHOLD; // Stop WDT
TI_CC_SPISetup(); // Initialize SPI port
TI_CC_PowerupResetCCxxxx(); // Reset CCxxxx
writeRFSettings(); // Write RF settings to config reg
TI_CC_SPIWriteBurstReg(TI_CCxxx0_PATABLE, paTable, paTableLen);//Write PATABLE
// Configure ports -- switch inputs, LEDs, GDO0 to RX packet info from CCxxxx
TI_CC_SW_PxREN |= TI_CC_SW1+TI_CC_SW2; // Enable pull-up resistor
TI_CC_SW_PxOUT |= TI_CC_SW1+TI_CC_SW2; // Enable pull-up resistor
TI_CC_SW_PxIES = TI_CC_SW1+TI_CC_SW2; // Int on falling edge
TI_CC_SW_PxIFG &= ~(TI_CC_SW1+TI_CC_SW2); // Clr flags
TI_CC_SW_PxIE = TI_CC_SW1+TI_CC_SW2; // Activate interrupt enables
TI_CC_LED_PxOUT &= ~(TI_CC_LED1 + TI_CC_LED2); // Outputs = 0
TI_CC_LED_PxDIR |= TI_CC_LED1 + TI_CC_LED2;// LED Direction to Outputs
TI_CC_GDO0_PxIES |= TI_CC_GDO0_PIN; // Int on falling edge (end of pkt)
TI_CC_GDO0_PxIFG &= ~TI_CC_GDO0_PIN; // Clear flag
TI_CC_GDO0_PxIE |= TI_CC_GDO0_PIN; // Enable int on end of packet
TI_CC_SPIStrobe(TI_CCxxx0_SRX); // Initialize CCxxxx in RX mode.
// When a pkt is received, it will
// signal on GDO0 and wake CPU
__bis_SR_register(LPM3_bits + GIE); // Enter LPM3, enable interrupts
}
void RF_change_Power(char power)
{
if (power<paTableLen)
{TI_CC_SPIStrobe(TI_CCxxx0_SIDLE); // set IDLE
TI_CC_SPIWriteReg (TI_CCxxx0_PATABLE,paTable[power]);
//Out_Payload.Status.power=TI_CC_SPIReadReg(TI_CCxxx0_PATABLE);
}
}
//-----------------------------------------------------------------------------
// void RFSendPacket(char *txBuffer, char size)
//
// DESCRIPTION:
// This function transmits a packet with length up to 63 bytes. To use this
// function, GD00 must be configured to be asserted when sync word is sent and
// de-asserted at the end of the packet, which is accomplished by setting the
// IOCFG0 register to 0x06, per the CCxxxx datasheet. GDO0 goes high at
// packet start and returns low when complete. The function polls GDO0 to
// ensure packet completion before returning.
//
// ARGUMENTS:
// char *txBuffer
// Pointer to a buffer containing the data to be transmitted
//
// char size
// The size of the txBuffer
//-----------------------------------------------------------------------------
void RFSendPacket(char *txBuffer, char size)
{
TI_CC_SPIStrobe(TI_CCxxx0_SIDLE);
TI_CC_SPIWriteBurstReg(TI_CCxxx0_TXFIFO, txBuffer, size); // Write TX data
// The CC1100 won't transmit the contents of the FIFO until the state is
// changed to TX state. During configuration we placed it in RX state and
// configured it to return to RX whenever it is done transmitting, so it is
// in RX now. Use the appropriate library function to change the state to TX.
TI_CC_SPIStrobe(TI_CCxxx0_STX); // Change state to TX, initiating
// data transfer
while (!(TI_CC_GDO0_PxIN&TI_CC_GDO0_PIN));// Wait GDO0 to go hi -> sync TX'ed
while (TI_CC_GDO0_PxIN&TI_CC_GDO0_PIN); // Wait GDO0 to clear -> end of pkt
TI_CC_SPIStrobe(TI_CCxxx0_SRX);
}
//-----------------------------------------------------------------------------
// char RFReceivePacket(char *rxBuffer, char *length)
//
// DESCRIPTION:
// Receives a packet of variable length (first byte in the packet must be the
// length byte). The packet length should not exceed the RXFIFO size. To use
// this function, APPEND_STATUS in the PKTCTRL1 register must be enabled. It
// is assumed that the function is called after it is known that a packet has
// been received; for example, in response to GDO0 going low when it is
// configured to output packet reception status.
//
// The RXBYTES register is first read to ensure there are bytes in the FIFO.
// This is done because the GDO signal will go high even if the FIFO is flushed
// due to address filtering, CRC filtering, or packet length filtering.
//
// ARGUMENTS:
// char *rxBuffer
// Pointer to the buffer where the incoming data should be stored
// char *length
// Pointer to a variable containing the size of the buffer where the
// incoming data should be stored. After this function returns, that
// variable holds the packet length.
//
// RETURN VALUE:
// char
// 0x80: CRC OK
// 0x00: CRC NOT OK (or no pkt was put in the RXFIFO due to filtering)
//-----------------------------------------------------------------------------
char RFReceivePacket(char *rxBuffer, char *length)
{
char status[2];
char pktLen;
char rxBytesVerify;
char rxBytes;
//mrfi code
rxBytesVerify = TI_CC_SPIReadReg( TI_CCxxx0_RXBYTES );
do
{
rxBytes = rxBytesVerify;
rxBytesVerify = TI_CC_SPIReadReg( TI_CCxxx0_RXBYTES );
}
while (rxBytes != rxBytesVerify);
if (rxBytes ==0) return 0;
//end of mrfi code
//if ((TI_CC_SPIReadStatus(TI_CCxxx0_RXBYTES) & TI_CCxxx0_NUM_RXBYTES))
{
pktLen = TI_CC_SPIReadReg(TI_CCxxx0_RXFIFO); // Read length byte
if (pktLen > *length) // If pktLen size <= rxBuffer
{
*length = pktLen; // Return the large size
TI_CC_SPIStrobe(TI_CCxxx0_SIDLE); // set IDLE - MRFI code
TI_CC_SPIStrobe(TI_CCxxx0_SFRX); // Flush RXFIFO
TI_CC_SPIStrobe(TI_CCxxx0_SRX); // RX state - from MRFI
return 0; // Error
}
else
{
TI_CC_SPIReadBurstReg(TI_CCxxx0_RXFIFO, rxBuffer, pktLen); // Pull data
*length = pktLen; // Return the actual size
TI_CC_SPIReadBurstReg(TI_CCxxx0_RXFIFO, status, 2);
// Read appended status bytes
return (char)(status[TI_CCxxx0_LQI_RX]&TI_CCxxx0_CRC_OK);
} // Return CRC_OK bit
}
//else
return 0; // Error
}
//-----------------------------------------------------------------------------
// void RFSendPacket(char *txBuffer, char size)
//
// DESCRIPTION:
// This function transmits a packet with length up to 63 bytes. To use this
// function, GD00 must be configured to be asserted when sync word is sent and
// de-asserted at the end of the packet, which is accomplished by setting the
// IOCFG0 register to 0x06, per the CCxxxx datasheet. GDO0 goes high at
// packet start and returns low when complete. The function polls GDO0 to
// ensure packet completion before returning.
//
// ARGUMENTS:
// char *txBuffer
// Pointer to a buffer containing the data to be transmitted
//
// char size
// The size of the txBuffer
//-----------------------------------------------------------------------------
void RFSendPacket(char *txBuffer, char size)
{
TI_CC_SPIWriteBurstReg(TI_CCxxx0_TXFIFO, txBuffer, size); // Write TX data
TI_CC_SPIStrobe(TI_CCxxx0_STX); // Change state to TX, initiating
// data transfer
while (!(TI_CC_GDO0_PxIN&TI_CC_GDO0_PIN));
// Wait GDO0 to go hi -> sync TX'ed
while (TI_CC_GDO0_PxIN&TI_CC_GDO0_PIN);
// Wait GDO0 to clear -> end of pkt
}
int main(void) {
WDTCTL = WDTPW | WDTHOLD; // Stop watchdog timer
//P2REN |= BIT3; // enable pull up resistor on p2.3
//P2OUT |= BIT3; // This does not seem to be working as expected.
// Initialize radio and SPI
TI_CC_SPISetup(); // Initialize SPI port
TI_CC_PowerupResetCCxxxx(); // Reset CCxxxx
writeRFSettings(); // Write RF settings to config reg
TI_CC_SPIWriteBurstReg(TI_CCxxx0_PATABLE, paTable, paTableLen);//Write PATABLE
// Enable interrupts from radio module
TI_CC_GDO0_PxIES |= TI_CC_GDO0_PIN; // Int on falling edge (end of pkt)
TI_CC_GDO0_PxIFG &= ~TI_CC_GDO0_PIN; // Clear flag
TI_CC_GDO0_PxIE |= TI_CC_GDO0_PIN; // Enable int on end of packet
// Enable radio
TI_CC_SPIStrobe(TI_CCxxx0_SRX); // Initialize CCxxxx in RX mode.
// configure packet
// --------------------------------------------
txBuffer[0] = MSGLEN-1; // Packet length
txBuffer[1] = 0x01; // Packet address - If this is 0xFF, it's an ack and not data.
// Begin data
// --------------------------------------------
txBuffer[2] = VALID_LEVEL; // default flag is valid. This is set on request from other module.
txBuffer[3] = 0x30;
txBuffer[4] = 0x31;
txBuffer[5] = 0x34;
txBuffer[6] = 0x35;
txBuffer[7] = 0x36;
txBuffer[8] = 0x37;
txBuffer[9] = 0x38;
txBuffer[10] = 0x39; // the rest of this data is used as filler.
// ------
// End Data
txBuffer[11] = 0x00; // terimate
// --------------------------------------------
_BIS_SR(GIE); // turn on interrupts. Initialization must be complete by this point
while(1) {
if(water_level_request) {
// Ideally, P2.3 should be pulled high. This is causing strange behavior
// on the pin that should be investigated.
// Check the status of P2.3 and set the r
txBuffer[WATER_DATA_TX_INDEX] = (P2IN & BIT3) ? 0 : VALID_LEVEL;// turn on the pump if the water level is valid.
RFSendPacket(txBuffer, MSGLEN); // Send water level data back to controller
__delay_cycles(450000); // delay a few cycles. Note that this means requests that take place during
// a pump cycle will be ignored completely.
water_level_request = 0; // clear requested data flag
}
}
}
//-----------------------------------------------------------------------------
// void RFSendPacket(char *txBuffer, char size)
//
// DESCRIPTION:
// This function transmits a packet with length up to 63 bytes. To use this
// function, GD00 must be configured to be asserted when sync word is sent and
// de-asserted at the end of the packet, which is accomplished by setting the
// IOCFG0 register to 0x06, per the CCxxxx datasheet. GDO0 goes high at
// packet start and returns low when complete. The function polls GDO0 to
// ensure packet completion before returning.
//
// ARGUMENTS:
// char *txBuffer
// Pointer to a buffer containing the data to be transmitted
//
// char size
// The size of the txBuffer
//-----------------------------------------------------------------------------
void RFSendPacket(char *txBuffer, char size)
{
TI_CC_SPIWriteBurstReg(TI_CCxxx0_TXFIFO, txBuffer, size); // Write TX data
TI_CC_SPIStrobe(TI_CCxxx0_STX); // Change state to TX, initiating
// data transfer
while (!(TI_CC_GDO0_PxIN&TI_CC_GDO0_PIN));
// Wait GDO0 to go hi -> sync TX'ed
while (TI_CC_GDO0_PxIN&TI_CC_GDO0_PIN);
// Wait GDO0 to clear -> end of pkt
TI_CC_GDO0_PxIFG &= ~TI_CC_GDO0_PIN; // After pkt TX, this flag is set.
// Has to be cleared before existing
}
void main (void)
{
WDTCTL = WDTPW + WDTHOLD; // Stop WDT
// 5ms delay to compensate for time to startup between MSP430 and CC1100/2500
__delay_cycles(5000);
TI_CC_SPISetup(); // Initialize SPI port
DCOCTL = 0; // Select lowest DCOx and MODx settings
BCSCTL1 = CALBC1_1MHZ; // Set DCO
DCOCTL = CALDCO_1MHZ;
P2SEL = 0; // Sets P2.6 & P2.7 as GPIO
TI_CC_PowerupResetCCxxxx(); // Reset CCxxxx
writeRFSettings(); // Write RF settings to config reg
TI_CC_SPIWriteBurstReg(TI_CCxxx0_PATABLE, paTable, paTableLen);//Write PATABLE
// Configure ports -- switch inputs, LEDs, GDO0 to RX packet info from CCxxxx
COM_Init();
TI_CC_SW_PxREN = TI_CC_SW1; // Enable Pull up resistor
TI_CC_SW_PxOUT = TI_CC_SW1; // Enable pull up resistor
TI_CC_SW_PxIES = TI_CC_SW1; // Int on falling edge
TI_CC_SW_PxIFG &= ~(TI_CC_SW1); // Clr flags
TI_CC_SW_PxIE = TI_CC_SW1; // Activate interrupt enables
TI_CC_LED_PxOUT &= ~(TI_CC_LED1 + TI_CC_LED2); // Outputs = 0
TI_CC_LED_PxDIR |= TI_CC_LED1 + TI_CC_LED2;// LED Direction to Outputs
TI_CC_GDO0_PxIES |= TI_CC_GDO0_PIN; // Int on falling edge (end of pkt)
TI_CC_GDO0_PxIFG &= ~TI_CC_GDO0_PIN; // Clear flag
TI_CC_GDO0_PxIE |= TI_CC_GDO0_PIN; // Enable int on end of packet
TI_CC_SPIStrobe(TI_CCxxx0_SRX); // Initialize CCxxxx in RX mode.
// When a pkt is received, it will
// signal on GDO0 and wake CPU
__bis_SR_register(LPM0_bits + GIE); // Enter LPM3, enable interrupts
}
//Perform the scan, returns the amount of bytes stored in the rssiArray
unsigned int scanFreqBands(void) {
//Amount of bytes stored in the rssiArray
unsigned int rssiLen=0;
BYTE i;
//RSSI value as reported by the CC device
UINT8 rssi_dec;
//RSSI value translated to dBm
INT16 rssi_dBm;
//Variable to store the current value of the TEST0 register
BYTE currentTest0;
//Variable to store the FREQ register value for the current frequency
UINT32 freqRegs;
//Temp variables for the FREQ register calculation
BYTE tempFreq2,tempFreq1,tempFreq0;
//Variables to store the current frequency to be scanned
UINT16 currentFreqMhz, currentFreqKhz;
//Controls if we should perform a calibration before starting RX
//in the current frequency
BOOL calNeeded;
//Copy of the pointer to the RSSI array
BYTE * rssiPtr=rssiTable;
//Initialize the value of the frequency counters
currentFreqMhz = scanParameters.startFreqMhz;
currentFreqKhz = scanParameters.startFreqKhz;
//Initialize freqRegs to the value for startFreq
freqRegs=freqRegsBase;
//Get reset value of TEST0
currentTest0=TI_CC_SPIReadReg(TI_CCxxx0_TEST0);
//For the start frequency a calibration is always needed
calNeeded=TRUE;
while (currentFreqMhz<scanParameters.stopFreqMhz || currentFreqKhz<scanParameters.stopFreqKhz) {
//Find out if we need to change the TEST0 register
for(i=0; i<NUM_TEST0_RANGES; i++){
//Find the TEST0 range the current frequency belongs to
if(currentFreqMhz>=test0RangeLimits[i] && currentFreqMhz<=test0RangeLimits[i+1]){
if(currentTest0!=test0Values[i]){
TI_CC_SPIWriteReg(TI_CCxxx0_TEST0, test0Values[i]);
currentTest0=TI_CC_SPIReadReg(TI_CCxxx0_TEST0);
//Also change the value of the FSCAL2 register to enable the VCO calibration stage
TI_CC_SPIWriteReg(TI_CCxxx0_FSCAL2, 0x2A);
calNeeded=TRUE;
}
break;
}
}
//Write the frequency registers FREQ2, FREQ1 and FREQ0
tempFreq0=(BYTE)freqRegs;
tempFreq1=(BYTE)(freqRegs>>8);
tempFreq2=(BYTE)(freqRegs>>16);
TI_CC_SPIWriteReg(TI_CCxxx0_FREQ2, tempFreq2);
TI_CC_SPIWriteReg(TI_CCxxx0_FREQ1, tempFreq1);
TI_CC_SPIWriteReg(TI_CCxxx0_FREQ0, tempFreq0);
//Calibrate if needed
if(calNeeded){
TI_CC_SPIStrobe(TI_CCxxx0_SCAL);
calNeeded=FALSE;
}
//Enter RX mode by issuing an SRX strobe command
TI_CC_SPIStrobe(TI_CCxxx0_SRX);
static BYTE state;
//Wait for radio to enter RX state by checking the status byte
do {
//state = TI_CC_GetTxStatus() & TI_CCxxx0_STATUS_STATE_BM;
state=TI_CC_SPIReadStatus(TI_CCxxx0_MARCSTATE);
state&=TI_CCxxx0_MARCSTATE_MASK;
//Flush the FIFO RX buffer in case of overflow
if(state==TI_CCxxx0_MARCSTATE_SM_RXFIFO_OVERFLOW)
TI_CC_SPIStrobe(TI_CCxxx0_SFRX);
} while (state != TI_CCxxx0_MARCSTATE_SM_RX);
//Wait for RSSI to be valid
usleep(scanParameters.rssiWait);
//Enter IDLE state by issuing an SIDLE strobe command
TI_CC_SPIStrobe(TI_CCxxx0_SIDLE);
//Read RSSI value and store it in rssi_dec
rssi_dec = TI_CC_SPIReadStatus(TI_CCxxx0_RSSI);
//Store the value in the rssi array
*rssiPtr++=rssi_dec;
//Update rssiLen
rssiLen+=sizeof(BYTE);
//Flush the FIFO buffer, just in case
TI_CC_SPIStrobe(TI_CCxxx0_SFRX);
//At the end of the loop, update the frequency counters
//TODO: Consider using Horner division code
currentFreqKhz += scanParameters.freqResolution;
if (currentFreqKhz >= 1000) {
currentFreqMhz += currentFreqKhz/1000;
currentFreqKhz %= 1000;
//According to DN508, a frequency calibration
//covers all frequencies less than 1Mhz apart
//from the one we calibrated for
calNeeded=TRUE;
}
//Update the value of the FREQ2:FREQ1:FREQ0 register value
freqRegs+=freqRegsStep;
}
return rssiLen;
}
// Contributed by Cor
void Radio_GotoSleep()
{
TI_CC_SPIStrobe(TI_CCxxx0_SIDLE); // set IDLE
TI_CC_SPIStrobe(TI_CCxxx0_SPWD); // power down.
}
void ModeRecepcio(void) {
TI_CC_SPIStrobe(TI_CCxxx0_SIDLE);
TI_CC_SPIStrobe(TI_CCxxx0_SRX); // Initialize CCxxxx in RX mode.
IoWait(900);
RadioMode=RX_Mode;
}
int main(void) {
WDTCTL = WDTPW | WDTHOLD; // Stop watchdog timer
P2DIR |= BIT3 | BIT4; // output to BLDC and LED
P2OUT &= ~BIT3; // make sure pump is off
P2OUT &= ~BIT4; //make sure LED is off
// Port 1 pushbutton config
P1REN |= TI_CC_SW1; // enable pullup/down on switch1
P1OUT |= TI_CC_SW1; // configure PUR as pull down (active low)
P1IES |= TI_CC_SW1; // interrupt on falling edge
P1IFG = 0; // clear all interurpt flags
P1IE = TI_CC_SW1; // enable interrupts on pushbutton
// Initialize radio and SPI - This code is derived from TI radio drivers
TI_CC_SPISetup(); // Initialize SPI port
TI_CC_PowerupResetCCxxxx(); // Reset CCxxxx
writeRFSettings(); // Write RF settings to config reg
TI_CC_SPIWriteBurstReg(TI_CCxxx0_PATABLE, paTable, paTableLen);//Write PATABLE
// Enable interrupts from radio module
P2IES |= TI_CC_GDO0_PIN; // Int on falling edge (end of pkt)
P2IFG &= ~TI_CC_GDO0_PIN; // Clear flag
P2IE |= TI_CC_GDO0_PIN; // Enable int on end of packet
// Enable radio
TI_CC_SPIStrobe(TI_CCxxx0_SRX); // Initialize CCxxxx in RX mode.
// configure packet
// --------------------------------------------
txBuffer[0] = MSGLEN-1; // Packet length -- this will get trimmed off.
txBuffer[1] = 0x01; // Packet address - If this is 0xFF, it's an ack and not data.
// Begin data
// --------------------------------------------
txBuffer[2] = OPERATE_SENSOR; // flag for other node to know that it needs to read switch state.
txBuffer[3] = 0x30; // Filler data to be used later on
txBuffer[4] = 0x31;
txBuffer[5] = 0x34;
txBuffer[6] = 0x35;
txBuffer[7] = 0x36;
txBuffer[8] = 0x37;
txBuffer[9] = 0x38;
txBuffer[10] = 0x39; // the rest of this data isn't used in ths project
// Extra data could be used in the event that more controller nodes are added
// ------
// End Data
txBuffer[11] = 0x00; // terimate
// --------------------------------------------
_BIS_SR(GIE); // turn on interrupts. Initialization is now complete.
while(1) {
if(buttonPressed) { // buttonPressed is a user interrupt flag
P1IE &= ~TI_CC_SW1; // disable user interrupts to avoid conflicting pump cycles
if (WaterLevelValid()) { // WaterLevelValid() will retrieve water level status from the other node
P2OUT |= BIT3; // turn on pump
__delay_cycles(1000000); // delay for a second while pump runs
P2OUT &= ~BIT3; // turn off pump
P2OUT &= ~BIT4; // turn off LED
}
buttonPressed = 0; // clear flag
P1IE = TI_CC_SW1; // Enable user interrupts (accept a new pump cycle)
}
}
}
