int ti_edma3_request_qdma_ch(unsigned int ch, unsigned int tccn, unsigned int eqn) { uint32_t reg; if (ch >= TI_EDMA3_NUM_DMA_CHS) return (EINVAL); /* Enable the QDMA channel in the QRAE registers */ reg = ti_edma3_cc_rd_4(TI_EDMA3CC_QRAE(0)); reg |= (0x01 << ch); ti_edma3_cc_wr_4(TI_EDMA3CC_QRAE(0), reg); /* Associate QDMA Channel to Event Queue */ reg = ti_edma3_cc_rd_4(TI_EDMA3CC_QDMAQNUM); reg |= TI_EDMA3CC_QDMAQNUM_SET(ch, eqn); ti_edma3_cc_wr_4(TI_EDMA3CC_QDMAQNUM, reg); /* Set TCC in corresponding PaRAM Entry */ reg = ti_edma3_cc_rd_4(TI_EDMA3CC_OPT(ch)); reg &= TI_EDMA3CC_OPT_TCC_CLR; reg |= TI_EDMA3CC_OPT_TCC_SET(ch); ti_edma3_cc_wr_4(TI_EDMA3CC_OPT(ch), reg); return 0; }
void ti_edma3_init(unsigned int eqn) { uint32_t reg; int i; /* on AM335x Event queue 0 is always mapped to Transfer Controller 0, * event queue 1 to TC2, etc. So we are asking PRCM to power on specific * TC based on what event queue we need to initialize */ ti_prcm_clk_enable(EDMA_TPTC0_CLK + eqn); /* Clear Event Missed Regs */ ti_edma3_cc_wr_4(TI_EDMA3CC_EMCR, 0xFFFFFFFF); ti_edma3_cc_wr_4(TI_EDMA3CC_EMCRH, 0xFFFFFFFF); ti_edma3_cc_wr_4(TI_EDMA3CC_QEMCR, 0xFFFFFFFF); /* Clear Error Reg */ ti_edma3_cc_wr_4(TI_EDMA3CC_CCERRCLR, 0xFFFFFFFF); /* Enable DMA channels 0-63 */ ti_edma3_cc_wr_4(TI_EDMA3CC_DRAE(0), 0xFFFFFFFF); ti_edma3_cc_wr_4(TI_EDMA3CC_DRAEH(0), 0xFFFFFFFF); for (i = 0; i < 64; i++) { ti_edma3_cc_wr_4(TI_EDMA3CC_DCHMAP(i), i<<5); } /* Initialize the DMA Queue Number Registers */ for (i = 0; i < TI_EDMA3_NUM_DMA_CHS; i++) { reg = ti_edma3_cc_rd_4(TI_EDMA3CC_DMAQNUM(i>>3)); reg &= TI_EDMA3CC_DMAQNUM_CLR(i); reg |= TI_EDMA3CC_DMAQNUM_SET(i, eqn); ti_edma3_cc_wr_4(TI_EDMA3CC_DMAQNUM(i>>3), reg); } /* Enable the QDMA Region access for all channels */ ti_edma3_cc_wr_4(TI_EDMA3CC_QRAE(0), (1 << TI_EDMA3_NUM_QDMA_CHS) - 1); /*Initialize QDMA Queue Number Registers */ for (i = 0; i < TI_EDMA3_NUM_QDMA_CHS; i++) { reg = ti_edma3_cc_rd_4(TI_EDMA3CC_QDMAQNUM); reg &= TI_EDMA3CC_QDMAQNUM_CLR(i); reg |= TI_EDMA3CC_QDMAQNUM_SET(i, eqn); ti_edma3_cc_wr_4(TI_EDMA3CC_QDMAQNUM, reg); } }