VOID
PcieAspmEnableOnLink (
IN PCI_ADDR Downstream,
IN PCI_ADDR Upstream,
IN UINT8 Lx,
IN AMD_NB_CONFIG *pConfig
)
{
ASPM_LINK_INFO AspmLinkInfo;
AspmLinkInfo.UpstreamLxCap = PcieAspmGetPmCapability (Upstream, pConfig);
AspmLinkInfo.DownstreamLxCap = PcieAspmGetPmCapability (Downstream, pConfig);
AspmLinkInfo.DownstreamPort = Downstream;
AspmLinkInfo.UpstreamPort = Upstream;
AspmLinkInfo.RequestedLx = Lx;
CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), " Downstream ASPM Capability %d:%d:%d - %x\n", Downstream.Address.Bus, Downstream.Address.Device, Downstream.Address.Function, AspmLinkInfo.DownstreamLxCap));
CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), " Upstream ASPM Capability %d:%d:%d - %x\n", Upstream.Address.Bus, Upstream.Address.Device, Upstream.Address.Function, AspmLinkInfo.UpstreamLxCap));
CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), " Requested ASPM State - %x\n", Lx));
AspmLinkInfo.DownstreamLx = AspmLinkInfo.UpstreamLxCap & AspmLinkInfo.DownstreamLxCap & Lx & ASPM_L1;
AspmLinkInfo.UpstreamLx = AspmLinkInfo.DownstreamLx;
if ((AspmLinkInfo.UpstreamLxCap & ASPM_L0s) != 0 && (Lx & ASPM_UPSTREAM_L0s) != 0) {
AspmLinkInfo.UpstreamLx |= ASPM_L0s;
}
if ((AspmLinkInfo.DownstreamLxCap & ASPM_L0s) != 0 && (Lx & ASPM_DOWNSTREAM_L0s) != 0) {
AspmLinkInfo.DownstreamLx |= ASPM_L0s;
}
#ifndef ASPM_WORKAROUND_DISABLE
PcieAspmWorkarounds (&AspmLinkInfo, pConfig);
#endif
LibNbCallBack (PHCB_AmdPcieAsmpInfo, (UINTN)&AspmLinkInfo, pConfig);
CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), " Upstream ASPM State - %x\n", AspmLinkInfo.UpstreamLx));
PcieAspmEnableOnDevice (Upstream, AspmLinkInfo.UpstreamLx, pConfig);
CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), " Downstream ASPM State - %x\n", AspmLinkInfo.DownstreamLx));
PcieAspmEnableOnFunction (Downstream, AspmLinkInfo.DownstreamLx, pConfig);
}
AGESA_STATUS
CALLCONV
AmdNbDispatcher (
IN OUT VOID*ConfigPtr
)
{
AGESA_STATUS Status;
IMAGE_ENTRY ImageEntry;
ImageEntry = NULL;
Status = AGESA_UNSUPPORTED;
CIMX_INIT_TRACE ((ConfigPtr));
CIMX_TRACE ((TRACE_DATA (ConfigPtr, CIMX_TRACE_ALL), "CIMx - RD890 Entry \n"));
CIMX_TRACE ((TRACE_DATA (ConfigPtr, CIMX_TRACE_ALL), " Funcid = %x Callout = %x\n", ((AMD_CONFIG_PARAMS*)ConfigPtr)->Func, ((AMD_CONFIG_PARAMS*)ConfigPtr)->CalloutPtr));
// 2. AltImage not supported
// 4. Try next dispatcher if possible, and we have not already got status back
if ((mNbModuleID.NextBlock != NULL) && (Status == AGESA_UNSUPPORTED)) {
MODULE_ENTRY ModuleEntry;
CIMX_TRACE ((TRACE_DATA (ConfigPtr, CIMX_TRACE_ALL), "CIMx - RD890 control goes to next Module \n"));
ModuleEntry = mNbModuleID.NextBlock->ModuleDispatcher;
Status = (*ModuleEntry) (ConfigPtr);
}
CIMX_TRACE ((TRACE_DATA (ConfigPtr, CIMX_TRACE_ALL), "CIMx - RD890 Exit\n"));
return Status;
}
/*----------------------------------------------------------------------------------------*/
SCAN_STATUS
PcieSetDeviceAspm (
IN PCI_SCAN_PROTOCOL *This,
IN PCI_ADDR Function
)
{
PCIE_DEVICE_TYPE DeviceType;
UINT8 SecondaryBus;
ASPM_WORKSPACE *WorkspacePtr;
WorkspacePtr = (ASPM_WORKSPACE*)This;
DeviceType = PcieGetDeviceType (Function, This->pConfig);
if (DeviceType == PcieDeviceRootComplex || DeviceType == PcieDeviceDownstreamPort) {
PCI_ADDR UpstreamDevice;
CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (This->pConfig), CIMX_NBPCIE_TRACE), " Reached downstream port\n"));
//Lets enable Common clock
LibNbPciRead (Function.AddressValue | 0x19, AccessWidth8, &SecondaryBus, This->pConfig);
LibNbPciRMW(Function.AddressValue | 0x18, AccessS3SaveWidth32, 0xffffffff, 0, This->pConfig); //This done to help UEFI bootscript restore bud topology.
if (SecondaryBus == 0) {
return SCAN_FINISHED;
}
//New Downstream Port
WorkspacePtr->LinkCount++;
if (WorkspacePtr->DownstreamPort.AddressValue == 0) {
WorkspacePtr->DownstreamPort.AddressValue = Function.AddressValue;
}
//Lets enable Common clock
UpstreamDevice.AddressValue = MAKE_SBDFO (0, SecondaryBus, 0, 0, 0);
if (LibNbIsDevicePresent (UpstreamDevice, This->pConfig)) {
PcieAspmEnableCommonClock (Function, UpstreamDevice, This->pConfig);
}
This->ScanBus (This, UpstreamDevice);
if (WorkspacePtr->DownstreamPort.AddressValue == Function.AddressValue) {
WorkspacePtr->DownstreamPort.AddressValue = 0;
PcieAspmEnableOnLink (Function, UpstreamDevice, WorkspacePtr->Lx, This->pConfig);
}
} else if (DeviceType == PcieDeviceUpstreamPort ) {
PCI_ADDR DownstreamDevice;
if (WorkspacePtr->DownstreamPort.AddressValue == 0) {
return SCAN_FINISHED;
}
CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (This->pConfig), CIMX_NBPCIE_TRACE), " Reached upstream port\n"));
LibNbPciRead (Function.AddressValue | 0x19, AccessWidth8, &SecondaryBus, This->pConfig);
LibNbPciRMW(Function.AddressValue | 0x18, AccessS3SaveWidth32, 0xffffffff, 0, This->pConfig); //This done to help UEFI bootscript restore bud topology.
if (SecondaryBus == 0) {
return SCAN_FINISHED;
}
DownstreamDevice.AddressValue = MAKE_SBDFO (0, SecondaryBus, 0, 0, 0);
This->ScanBus (This, DownstreamDevice);
} else if (DeviceType < PcieDeviceLegacyEndPoint) {
// We reach end of link @toDo code to check exit latency.
CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (This->pConfig), CIMX_NBPCIE_TRACE), " Reached endpoint \n"));
}
return SCAN_FINISHED;
}
/**
* Power Off Pll for unused lanes.
*
*
*
* @param[in] CoreId PCI Express Core ID
* @param[in] pConfig Northbridge configuration structure pointer.
*/
VOID
PcieLibPowerOffPll (
IN CORE CoreId,
IN AMD_NB_CONFIG *pConfig
)
{
PCIE_CONFIG *pPcieConfig;
UINT32 CoreAddress;
UINT32 PowerOfPllValue;
UINT32 PadsMap;
//UINT32 TxClockOffValue;
UINT32 PowerOfPllRegister;
pPcieConfig = GET_PCIE_CONFIG_PTR (pConfig);
CoreAddress = PcieLibGetCoreAddress (CoreId, pConfig);
PowerOfPllValue = 0;
PadsMap = 0;
//TxClockOffValue = 0;
PowerOfPllRegister = NB_MISC_REG23;
LibNbPciIndexRead (pConfig->NbPciAddress.AddressValue | NB_BIF_INDEX, NB_BIFNB_REG65 | CoreAddress, AccessS3SaveWidth32, &PadsMap, pConfig);
if (CoreAddress == GPP1_CORE || CoreAddress == GPP2_CORE) {
if ((PadsMap & 0xf0) == 0xf0) {
//Power Off PLL1
PowerOfPllValue |= (BIT1 | BIT3);
if ((PadsMap & 0x0f) == 0x0f && pPcieConfig->CoreConfiguration[CoreId] != GFX_CONFIG_AABB) {
//Power Off PLL0
PowerOfPllValue |= (BIT0 | BIT2);
}
}
if (CoreAddress == GPP2_CORE) {
PowerOfPllValue <<= 8;
//TxClockOffValue = BIT1;
} else {
//TxClockOffValue = BIT0;
}
if ((UINT16)PadsMap != 0xffff) {
//TxClockOffValue = 0; //Do not disable TX clock in case any line is ON
}
}
if (CoreAddress == GPP3a_CORE ) {
if ((UINT16)PadsMap == 0x3F3F) {
PowerOfPllValue = BIT18 | BIT16;
//TxClockOffValue = BIT2;
}
}
if (CoreAddress == GPP3b_CORE ) {
PowerOfPllRegister = NB_MISC_REG2E;
if ((UINT16)PadsMap == 0x0F0F) {
PowerOfPllValue = BIT8 | BIT6;
//TxClockOffValue = BIT3;
}
}
//Power Off Pll
LibNbPciIndexRMW (pConfig->NbPciAddress.AddressValue | NB_MISC_INDEX, PowerOfPllRegister , AccessS3SaveWidth32, 0xffffffff, PowerOfPllValue, pConfig);
CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), " Power off PLL CoreId %d, Value 0x%x\n", CoreId, PowerOfPllValue));
//Turn off TXCLK
//LibNbPciIndexRMW (pConfig->NbPciAddress.AddressValue | NB_MISC_INDEX, NB_MISC_REG07, AccessS3SaveWidth32, 0xffffffff, TxClockOffValue, pConfig);
}
/*----------------------------------------------------------------------------------------*/
UINT32
PcieInitHotplug (
IN AMD_NB_CONFIG *pConfig
)
{
UINT32 ServerHotplugPortMask;
PORT PortId;
PCI_ADDR ClkPciAddress;
NB_INFO NbInfo;
PCIE_CONFIG *pPcieConfig;
CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE]PcieInitHotplug Enter\n"));
pPcieConfig = GET_PCIE_CONFIG_PTR (pConfig);
NbInfo = LibNbGetRevisionInfo (pConfig);
ServerHotplugPortMask = 0;
ClkPciAddress = pConfig->NbPciAddress;
ClkPciAddress.Address.Function = 1;
if (NbInfo.Type == NB_SR5690) {
for (PortId = MIN_PORT_ID; PortId <= MAX_PORT_ID; PortId++) {
if (pPcieConfig->PortConfiguration[PortId].PortPresent == ON &&
pPcieConfig->PortConfiguration[PortId].PortHotplug != OFF ) {
PCI_ADDR Port;
Port = PcieLibGetPortPciAddress (PortId, pConfig);
if (pPcieConfig->PortConfiguration[PortId].PortHotplug == SERVER_HOTPLUG) {
UINT8 HpDescriptorRegister;
UINT8 HpDescriptorOffset;
ServerHotplugPortMask |= 1 << PortId;
HpDescriptorOffset = (PcieLibGetStaticPortInfo (PcieLibNativePortId (PortId, pConfig), pConfig))->HotplugAddress;
if (HpDescriptorOffset != 0xff) {
ServerHotplugPortMask |= 1 << PortId;
HpDescriptorRegister = (PcieLibGetCoreInfo (PcieLibGetCoreId (PortId, pConfig), pConfig))->HotplugRegister;
//Enable CLK config
LibNbEnableClkConfig (pConfig);
//Setup descriptor
LibNbPciRMW (
ClkPciAddress.AddressValue | HpDescriptorRegister ,
AccessWidth32,
0xffffffff,
((1 << 3) | (pPcieConfig->ExtPortConfiguration[PortId].PortHotplugDevMap << 2) | pPcieConfig->ExtPortConfiguration[PortId].PortHotplugByteMap) << HpDescriptorOffset,
pConfig
);
//Hide CLK config
LibNbDisableClkConfig (pConfig);
// Enable power fault
LibNbPciIndexRMW (Port.AddressValue | NB_BIF_INDEX, NB_BIFNBP_REG10, AccessWidth32, (UINT32)~BIT4, BIT4, pConfig);
//Set up capability. Keep NO_COMMAND_COMPLETED_SUPPORTED (bit 18) to zero
LibNbPciRMW (Port.AddressValue | NB_PCIP_REG6C, AccessWidth32, 0xfffbffff, SERVER_HOTPLUG_CAPABILITY, pConfig);
//Clear Status
LibNbPciRMW (Port.AddressValue | NB_PCIP_REG72, AccessWidth16, 0xffffffff, 0x11F, pConfig);
}
}
if (pPcieConfig->PortConfiguration[PortId].PortHotplug == NATIVE_HOTPLUG) {
LibNbPciRMW (Port.AddressValue | NB_PCIP_REG6C, AccessWidth32, 0xffffffff, NATIVE_HOTPLUG_CAPABILITY, pConfig);
}
}
}
}
return ServerHotplugPortMask;
}
/*----------------------------------------------------------------------------------------*/
VOID
PcieAsmpEnableOnPort (
IN PORT PortId,
IN PCIE_LINK_ASPM AsmpState,
IN AMD_NB_CONFIG *pConfig
)
{
PCI_ADDR Port;
UINT8 Lx;
PCI_ADDR NbPciAddress;
CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "PcieAsmpEnableOnPort Enter PortId [%d]\n", PortId));
NbPciAddress.AddressValue = NB_SBDFO;
switch (AsmpState) {
case PcieLinkAspmDisabled:
return ;
case PcieLinkAspmL0s:
Lx = ASPM_UPSTREAM_L0s | ASPM_DOWNSTREAM_L0s;
break;
case PcieLinkAspmL1:
Lx = ASPM_L1;
break;
case PcieLinkAspmL0sAndL1:
Lx = ASPM_UPSTREAM_L0s | ASPM_DOWNSTREAM_L0s | ASPM_L1;
break;
case PcieLinkAspmL0sDownstreamOnly:
Lx = ASPM_DOWNSTREAM_L0s;
break;
case PcieLinkAspmL0sDownstreamOnlyAndL1:
Lx = ASPM_DOWNSTREAM_L0s | ASPM_L1;
break;
default:
CIMX_ASSERT (FALSE);
return ;
}
Port = PcieLibGetPortPciAddress (PortId, pConfig);
//NB-SB link
if (PortId == 8 && NbPciAddress.AddressValue == 0) {
if (PcieSbInitAspm ((Lx & ASPM_L1) | ((Lx & ASPM_UPSTREAM_L0s)?ASPM_L0s:0), pConfig) == AGESA_SUCCESS) {
PcieAspmEnableOnFunction (Port, (Lx & ASPM_L1) | ((Lx & ASPM_DOWNSTREAM_L0s)?ASPM_L0s:0), pConfig);
}
return ;
}
PcieAspmSetOnRc (Port, Lx, pConfig);
CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "PcieAsmpEnableOnPort Exit. Lx[0x%x]\n", Lx));
return ;
}
VOID
PcieAspmEnableCommonClock (
IN PCI_ADDR Downstream,
IN PCI_ADDR Upstream,
IN AMD_NB_CONFIG *pConfig
)
{
UINT16 DownstreamCommonClockCap;
UINT16 UpstreamCommonClockCap;
UINT16 Value;
UINT8 DownstreamPcieCapPtr;
UINT8 UpstreamPcieCapPtr;
DownstreamPcieCapPtr = LibNbFindPciCapability (Downstream.AddressValue, PCIE_CAP_ID, pConfig);
UpstreamPcieCapPtr = LibNbFindPciCapability (Upstream.AddressValue, PCIE_CAP_ID, pConfig);
if (DownstreamPcieCapPtr == 0 || UpstreamPcieCapPtr == 0) {
return ;
}
LibNbPciRead (Downstream.AddressValue | (DownstreamPcieCapPtr + 0x10) , AccessWidth16, &DownstreamCommonClockCap, pConfig);
if ((DownstreamCommonClockCap & BIT6) != 0) {
//Aready enabled
return ;
}
LibNbPciRead (Downstream.AddressValue | (DownstreamPcieCapPtr + 0x12) , AccessWidth16, &DownstreamCommonClockCap, pConfig);
CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), " Downstream Common Clock Capability %d:%d:%d - %x\n", Downstream.Address.Bus, Downstream.Address.Device, Downstream.Address.Function, DownstreamCommonClockCap));
LibNbPciRead (Upstream.AddressValue | (UpstreamPcieCapPtr + 0x12) , AccessWidth16, &UpstreamCommonClockCap, pConfig);
CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), " Upstream Common Clock Capability %d:%d:%d - %x\n", Upstream.Address.Bus, Upstream.Address.Device, Upstream.Address.Function, UpstreamCommonClockCap));
if ((DownstreamCommonClockCap & UpstreamCommonClockCap & BIT12) != 0) {
//Enable common clock
PcieAspmCommonClockOnFunction (Downstream, pConfig);
PcieAspmCommonClockOnDevice (Upstream, pConfig);
// LibNbPciRMW (Downstream.AddressValue | (DownstreamPcieCapPtr + 0x10) , AccessS3SaveWidth8, 0xff, BIT6, pConfig);
// LibNbPciRMW (Upstream.AddressValue | (UpstreamPcieCapPtr + 0x10) , AccessS3SaveWidth8, 0xff, BIT6, pConfig);
//Reatrain link
LibNbPciRMW (Downstream.AddressValue | (DownstreamPcieCapPtr + 0x10) , AccessS3SaveWidth8, 0xff, BIT5, pConfig);
do {
LibNbPciRead (Downstream.AddressValue | (DownstreamPcieCapPtr + 0x12) , AccessWidth16, (UINT16*)&Value, pConfig);
STALL (GET_BLOCK_CONFIG_PTR (pConfig), 200, CIMX_S3_SAVE);
} while ((Value & BIT11) != 0);
}
}
/*----------------------------------------------------------------------------------------*/
VOID
PcieAspmSetOnRc (
IN PCI_ADDR Device,
IN UINT8 Lx,
IN AMD_NB_CONFIG *pConfig
)
{
ASPM_WORKSPACE AspmWorkspace;
CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE]PcieSetPortAspm Enter\n"));
LibAmdMemFill (&AspmWorkspace, 0, sizeof (AspmWorkspace), (AMD_CONFIG_PARAMS *)&(pConfig->sHeader));
AspmWorkspace.ScanPciePort.pConfig = pConfig;
AspmWorkspace.ScanPciePort.ScanBus = LibNbScanPciBus;
AspmWorkspace.ScanPciePort.ScanDevice = LibNbScanPciDevice;
AspmWorkspace.ScanPciePort.ScanFunction = PcieSetDeviceAspm;
AspmWorkspace.Lx = Lx;
AspmWorkspace.ScanPciePort.ScanFunction (&AspmWorkspace.ScanPciePort, Device);
if (AspmWorkspace.LinkCount > 1) {
LibNbScanPciBridgeBuses (&AspmWorkspace.ScanPciePort, Device);
}
CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE]PcieSetPortAspm Exit\n"));
}
/*----------------------------------------------------------------------------------------*/
VOID
PcieCheckHotplug (
IN UINT32 ServerHotplugPortMask,
IN AMD_NB_CONFIG *pConfig
)
{
PORT PortId;
CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE]PcieCheckHotplug Enter\n"));
//Check if Firmware loaded successfully
for (PortId = MIN_PORT_ID; PortId <= MAX_PORT_ID; PortId++) {
//Check Firmware Loaded successfully
if ((ServerHotplugPortMask & (1 << PortId)) != 0) {
UINT32 Count;
PCI_ADDR Port;
UINT16 SlotStatus;
Count = 30; //Setup counter for 30ms
Port = PcieLibGetPortPciAddress (PortId, pConfig);
do {
STALL (GET_BLOCK_CONFIG_PTR (pConfig), 1000, 0);
LibNbPciRead (Port.AddressValue | NB_PCIP_REG72, AccessWidth16, &SlotStatus, pConfig);
} while ((SlotStatus & (ATTN_BUTTON_PRESSED | PWR_FAULT_DETECTED)) == 0 && --Count != 0);
CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), " Hotplug Firmware Init PortId = %d SlotStatus = 0x%x Retry = %d\n", PortId, SlotStatus, Count));
if ((SlotStatus & PWR_FAULT_DETECTED) != 0 || (SlotStatus & (PWR_FAULT_DETECTED | ATTN_BUTTON_PRESSED)) == 0) {
REPORT_EVENT (AGESA_ERROR, PCIE_ERROR_HOTPLUG_INIT, PortId, 0, 0, 0, pConfig);
CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), " ERROR!!!Hotplug Firmware Init FAIL\n"));
LibNbPciRMW (Port.AddressValue | NB_PCIP_REG6C, AccessWidth32, (UINT32)~SERVER_HOTPLUG_CAPABILITY, 0x0, pConfig);
} else {
//Clear Status
LibNbPciRMW (Port.AddressValue | NB_PCIP_REG72, AccessWidth16, 0xffffffff, 0x11F, pConfig);
if ((SlotStatus & PRESENCE_DETECT_CHANGED) != 0) {
//Power on slot
LibNbPciRMW (Port.AddressValue | NB_PCIP_REG70, AccessWidth16, (UINT32)~PWR_CONTROLLER_CNTL, 0x0, pConfig);
}
}
}
}
CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE]PcieCheckHotplug Exit\n"));
}
/**
* Enable TX clock gating or shutdown TX clock if possible
*
*
*
* @param[in] CoreId PCI Express Core ID
* @param[in] pConfig Northbridge configuration structure pointer. *
*/
VOID
PcieLibManageTxClock (
IN CORE CoreId,
IN AMD_NB_CONFIG *pConfig
)
{
PCIE_CONFIG *pPcieConfig;
UINT32 CoreAddress;
UINT32 Value;
pPcieConfig = GET_PCIE_CONFIG_PTR (pConfig);
CoreAddress = PcieLibGetCoreAddress (CoreId, pConfig);
if (pPcieConfig->CoreSetting[CoreId].TxClockGating == ON) {
switch (CoreAddress) {
case GPP1_CORE:
Value = BIT4;
break;
case GPP2_CORE:
Value = BIT5;
break;
case GPP3a_CORE:
Value = BIT6;
break;
case GPP3b_CORE:
Value = BIT24;
break;
case SB_CORE:
Value = BIT7;
break;
default:
Value = 0;
CIMX_ASSERT (FALSE);
}
LibNbPciIndexRMW (pConfig->NbPciAddress.AddressValue | NB_MISC_INDEX, NB_MISC_REG07, AccessS3SaveWidth32, 0xffffffff, Value, pConfig);
LibNbPciIndexRMW (pConfig->NbPciAddress.AddressValue | NB_BIF_INDEX, NB_BIFNB_REG40 | CoreAddress, AccessS3SaveWidth32, (UINT32)~BIT6, BIT6, pConfig);
LibNbPciIndexRMW (pConfig->NbPciAddress.AddressValue | NB_BIF_INDEX, NB_BIFNB_REG11 | CoreAddress, AccessS3SaveWidth32, 0xfffffff0, 0x0C, pConfig);
}
if (pPcieConfig->CoreSetting[CoreId].TxClockOff == ON) {
UINT8 ActiveCoreMap;
ActiveCoreMap = PcieLibGetActiveCoreMap (pConfig);
if ((ActiveCoreMap & (1 << CoreId)) == 0) {
//Core not active we can shutdown TX clk permanantly
CORE_INFO *pCoreInfo;
CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), " Shutdown TX clock\n"));
pPcieConfig->CoreSetting[CoreId].CoreDisableStatus = ON;
pCoreInfo = PcieLibGetCoreInfo (CoreId, pConfig);
LibNbPciIndexRMW (pConfig->NbPciAddress.AddressValue | NB_MISC_INDEX, NB_MISC_REG07, AccessS3SaveWidth32, 0xffffffff, 1 << pCoreInfo->TxOffOffset, pConfig);
}
}
}
AGESA_STATUS
MiscInitializer (
IN OUT AMD_NB_CONFIG *NbConfigPtr
)
{
AMD_NB_CONFIG_BLOCK *ConfigPtr;
CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (NbConfigPtr), CIMX_NB_TRACE), "[NB]NbMiscInitializer Enter\n"));
ConfigPtr = GET_BLOCK_CONFIG_PTR (NbConfigPtr);
if (ConfigPtr == NULL) {
return AGESA_FATAL;
}
if (ConfigPtr->PlatformType == DetectPlatform) {
NB_INFO NbInfo;
NbInfo = LibNbGetRevisionInfo (NbConfigPtr);
if (NbInfo.Type != NB_UNKNOWN && NbInfo.Type >= NB_SR5690 && NbInfo.Type <= NB_SR5650) {
ConfigPtr->PlatformType = ServerPlatform;
} else {
ConfigPtr->PlatformType = DesktopPlatform;
}
}
CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (NbConfigPtr), CIMX_NB_TRACE), "[NB]NbMiscInitializer Exit\n"));
return AGESA_SUCCESS;
}
static int composite_enumerate(struct usbtrace_s *trace, void *arg)
{
switch (trace->event)
{
case TRACE_DEVINIT:
printf("USB controller initialization: %04x\n", trace->value);
break;
case TRACE_DEVUNINIT:
printf("USB controller un-initialization: %04x\n", trace->value);
break;
case TRACE_DEVREGISTER:
printf("usbdev_register(): %04x\n", trace->value);
break;
case TRACE_DEVUNREGISTER:
printf("usbdev_unregister(): %04x\n", trace->value);
break;
case TRACE_EPCONFIGURE:
printf("Endpoint configure(): %04x\n", trace->value);
break;
case TRACE_EPDISABLE:
printf("Endpoint disable(): %04x\n", trace->value);
break;
case TRACE_EPALLOCREQ:
printf("Endpoint allocreq(): %04x\n", trace->value);
break;
case TRACE_EPFREEREQ:
printf("Endpoint freereq(): %04x\n", trace->value);
break;
case TRACE_EPALLOCBUFFER:
printf("Endpoint allocbuffer(): %04x\n", trace->value);
break;
case TRACE_EPFREEBUFFER:
printf("Endpoint freebuffer(): %04x\n", trace->value);
break;
case TRACE_EPSUBMIT:
printf("Endpoint submit(): %04x\n", trace->value);
break;
case TRACE_EPCANCEL:
printf("Endpoint cancel(): %04x\n", trace->value);
break;
case TRACE_EPSTALL:
printf("Endpoint stall(true): %04x\n", trace->value);
break;
case TRACE_EPRESUME:
printf("Endpoint stall(false): %04x\n", trace->value);
break;
case TRACE_DEVALLOCEP:
printf("Device allocep(): %04x\n", trace->value);
break;
case TRACE_DEVFREEEP:
printf("Device freeep(): %04x\n", trace->value);
break;
case TRACE_DEVGETFRAME:
printf("Device getframe(): %04x\n", trace->value);
break;
case TRACE_DEVWAKEUP:
printf("Device wakeup(): %04x\n", trace->value);
break;
case TRACE_DEVSELFPOWERED:
printf("Device selfpowered(): %04x\n", trace->value);
break;
case TRACE_DEVPULLUP:
printf("Device pullup(): %04x\n", trace->value);
break;
case TRACE_CLASSBIND:
printf("Class bind(): %04x\n", trace->value);
break;
case TRACE_CLASSUNBIND:
printf("Class unbind(): %04x\n", trace->value);
break;
case TRACE_CLASSDISCONNECT:
printf("Class disconnect(): %04x\n", trace->value);
break;
case TRACE_CLASSSETUP:
printf("Class setup(): %04x\n", trace->value);
break;
case TRACE_CLASSSUSPEND:
printf("Class suspend(): %04x\n", trace->value);
break;
case TRACE_CLASSRESUME:
printf("Class resume(): %04x\n", trace->value);
break;
case TRACE_CLASSRDCOMPLETE:
printf("Class RD request complete: %04x\n", trace->value);
break;
case TRACE_CLASSWRCOMPLETE:
printf("Class WR request complete: %04x\n", trace->value);
break;
default:
switch (TRACE_ID(trace->event))
{
case TRACE_CLASSAPI_ID: /* Other class driver system API calls */
printf("Class API call %d: %04x\n",
TRACE_DATA(trace->event), trace->value);
break;
case TRACE_CLASSSTATE_ID: /* Track class driver state changes */
printf("Class state %d: %04x\n",
TRACE_DATA(trace->event), trace->value);
break;
case TRACE_INTENTRY_ID: /* Interrupt handler entry */
printf("Interrupt %d entry: %04x\n",
TRACE_DATA(trace->event), trace->value);
break;
case TRACE_INTDECODE_ID: /* Decoded interrupt trace->event */
printf("Interrupt decode %d: %04x\n",
TRACE_DATA(trace->event), trace->value);
break;
case TRACE_INTEXIT_ID: /* Interrupt handler exit */
printf("Interrupt %d exit: %04x\n",
TRACE_DATA(trace->event), trace->value);
break;
case TRACE_OUTREQQUEUED_ID: /* Request queued for OUT endpoint */
printf("EP%d OUT request queued: %04x\n",
TRACE_DATA(trace->event), trace->value);
break;
case TRACE_INREQQUEUED_ID: /* Request queued for IN endpoint */
printf("EP%d IN request queued: %04x\n",
TRACE_DATA(trace->event), trace->value);
break;
case TRACE_READ_ID: /* Read (OUT) action */
printf("EP%d OUT read: %04x\n",
TRACE_DATA(trace->event), trace->value);
break;
case TRACE_WRITE_ID: /* Write (IN) action */
printf("EP%d IN write: %04x\n",
TRACE_DATA(trace->event), trace->value);
break;
case TRACE_COMPLETE_ID: /* Request completed */
printf("EP%d request complete: %04x\n",
TRACE_DATA(trace->event), trace->value);
break;
case TRACE_DEVERROR_ID: /* USB controller driver error event */
printf("Controller error: %02x:%04x\n",
TRACE_DATA(trace->event), trace->value);
break;
case TRACE_CLSERROR_ID: /* USB class driver error event */
printf("Class error: %02x:%04x\n",
TRACE_DATA(trace->event), trace->value);
break;
default:
printf("Unrecognized event: %02x:%02x:%04x\n",
TRACE_ID(trace->event) >> 8,
TRACE_DATA(trace->event), trace->value);
break;
}
}
return OK;
}
AGESA_STATUS
PciePortRemapInit (
IN AMD_NB_CONFIG *pConfig
)
{
AGESA_STATUS Status;
PORT FinalDeviceIdList[MAX_PORT_ID + 1];
UINT8 UsedDeviceIdMap[MAX_PORT_ID + 1];
BOOLEAN IsDeviceRemapEnabled;
PORT PortId;
PCIE_CONFIG *pPcieConfig;
CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE]PciePortDeviceNumberRemap Enter \n"));
pPcieConfig = GET_PCIE_CONFIG_PTR (pConfig);
Status = AGESA_SUCCESS;
IsDeviceRemapEnabled = FALSE;
// Remap Device
LibAmdMemFill (&UsedDeviceIdMap, 0, sizeof (UsedDeviceIdMap), (AMD_CONFIG_PARAMS *)&(pConfig->sHeader));
LibAmdMemFill (&FinalDeviceIdList, 0, sizeof (FinalDeviceIdList), (AMD_CONFIG_PARAMS *)&(pConfig->sHeader));
for (PortId = MIN_PORT_ID; PortId <= MAX_PORT_ID; PortId++) {
if (PcieLibIsValidPortId (PortId, pConfig)) {
PORT NativePortId = PcieLibNativePortId (PortId, pConfig);
if (pPcieConfig->PortConfiguration[PortId].PortPresent) {
//FinalDeviceIdList[PortId] = PortId;
if (pPcieConfig->ExtPortConfiguration[PortId].PortMapping != 0) {
if (pPcieConfig->ExtPortConfiguration[PortId].PortMapping < MIN_PORT_ID ||
pPcieConfig->ExtPortConfiguration[PortId].PortMapping > MAX_PORT_ID ||
pPcieConfig->ExtPortConfiguration[PortId].PortMapping == 8) {
return AGESA_ERROR;
}
FinalDeviceIdList[NativePortId] = pPcieConfig->ExtPortConfiguration[PortId].PortMapping;
IsDeviceRemapEnabled = TRUE;
} else {
FinalDeviceIdList[NativePortId] = PortId;
}
CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), " Requested Port Mapping %d -> %d\n", PortId, FinalDeviceIdList[PortId]));
if (UsedDeviceIdMap[FinalDeviceIdList[NativePortId]] == 0 ) {
UsedDeviceIdMap[FinalDeviceIdList[NativePortId]] = 1;
} else {
return AGESA_ERROR;
}
}
}
}
if (!IsDeviceRemapEnabled) {
return Status;
}
for (PortId = MIN_PORT_ID; PortId <= MAX_PORT_ID; PortId++) {
PORT_STATIC_INFO *pStaticPortInfo;
pStaticPortInfo = PcieLibGetStaticPortInfo (PortId, pConfig);
if (pStaticPortInfo->MappingAddress == 0xFF) {
continue;
}
if (FinalDeviceIdList[PortId] == 0) {
FinalDeviceIdList[PortId] = PciePortRemapAllocateDeviceId (&UsedDeviceIdMap[0]);
}
CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), " Port Mapping %d -> %d\n", PortId, FinalDeviceIdList[PortId]));
LibNbPciIndexRMW (
NB_SBDFO | NB_MISC_INDEX,
(PortId > 9)?NB_MISC_REG21:NB_MISC_REG20,
AccessWidth32,
0xffffffff,
FinalDeviceIdList [PortId] << pStaticPortInfo->MappingAddress,
pConfig
);
}
LibNbPciIndexRMW (NB_SBDFO | NB_MISC_INDEX, NB_MISC_REG20, AccessWidth32, 0xffffffff, 0x3, pConfig);
CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE]PciePortDeviceNumberRemap Exit [0x%x] \n", Status));
return Status;
}
/**
* Enable LCLK clock gating or shutdown LCLK clock banch if possible
*
*
*
* @param[in] CoreId PCI Express Core ID
* @param[in] pConfig Northbridge configuration structure pointer.
*
*/
VOID
PcieLibManageLclkClock (
IN CORE CoreId,
IN AMD_NB_CONFIG *pConfig
)
{
UINT32 Value;
UINT32 Mask;
PCI_ADDR ClkPciAddress;
UINT32 CoreAddress;
PCIE_CONFIG *pPcieConfig;
CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE]PcieLibManageLclkClock [CoreId %d] Enter \n", CoreId));
pPcieConfig = GET_PCIE_CONFIG_PTR (pConfig);
CoreAddress = PcieLibGetCoreAddress (CoreId, pConfig);
ClkPciAddress = pConfig->NbPciAddress;
ClkPciAddress.Address.Function = 1;
LibNbEnableClkConfig (pConfig);
if (pPcieConfig->CoreSetting[CoreId].LclkClockGating == ON) {
ClkPciAddress.Address.Register = NB_CLK_REGE8;
Value = 0;
Mask = 0;
switch (CoreAddress) {
case GPP1_CORE:
ClkPciAddress.Address.Register = NB_CLK_REG94;
Mask = BIT16;
break;
case GPP2_CORE:
Value = BIT28;
break;
case GPP3a_CORE:
Value = BIT31;
break;
case GPP3b_CORE:
Value = BIT25;
break;
case SB_CORE:
ClkPciAddress.Address.Register = NB_CLK_REG94;
Mask = BIT24;
break;
default:
CIMX_ASSERT (FALSE);
}
LibNbPciRMW (ClkPciAddress.AddressValue, AccessS3SaveWidth32, ~Mask, Value, pConfig);
}
if (pPcieConfig->CoreSetting[CoreId].LclkClockOff == ON) {
UINT8 ActiveCoreMap;
ActiveCoreMap = PcieLibGetActiveCoreMap (pConfig);
if ((ActiveCoreMap & (1 << CoreId)) == 0) {
//Core not active we can shutdown LCLK permanantly
CORE_INFO *pCoreInfo;
CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), " Shutdown LCKL clock\n"));
pCoreInfo = PcieLibGetCoreInfo (CoreId, pConfig);
ClkPciAddress.Address.Register = NB_CLK_REGE0;
pPcieConfig->CoreSetting[CoreId].CoreDisableStatus = ON;
// We have to setup Index for BIFNB to point out to SB core. After this point core registers no longer accesasable
LibNbPciIndexRMW (pConfig->NbPciAddress.AddressValue | NB_BIF_INDEX, 0x00 | SB_CORE, AccessS3SaveWidth32, 0xffffffff, 0x00, pConfig);
LibNbPciRMW (ClkPciAddress.AddressValue, AccessS3SaveWidth32, 0xffffffff, 1 << pCoreInfo->LclkOffOffset, pConfig);
Value = 0;
if (CoreAddress == GPP1_CORE) {
if ((ActiveCoreMap & 0xb) == 0 && !LibNbIsIommuEnabled (pConfig)) {
// Can shutdown master core
Value = 1 << pCoreInfo->LclkPermOffOffset;
}
} else {
Value = 1 << pCoreInfo->LclkPermOffOffset;
}
if (Value != 0) {
NbIommuDisconnectPcieCore (CoreId, pConfig);
LibNbPciIndexRMW (pConfig->NbPciAddress.AddressValue | NB_MISC_INDEX, NB_MISC_REG27, AccessS3SaveWidth32, 0xffffffff, Value, pConfig);
}
}
}
LibNbDisableClkConfig (pConfig);
}