/** * @brief Initializes the acquisition module. * @param None * @retval Status */ TSL_Status_enum_T TSL_acq_Init(void) { #if TSLPRM_TSC_GPIO_CONFIG > 0 TSL_acq_InitGPIOs(); #endif // Enable TSC clock RCC->AHBENR |= RCC_AHBENR_TSEN; // TSC enabled TSC->CR = 0x01; // Set CTPH #if TSLPRM_TSC_CTPH > 0 TSC->CR |= (uint32_t)((uint32_t)TSLPRM_TSC_CTPH << 28) & 0xF0000000; #endif // Set CTPL #if TSLPRM_TSC_CTPL > 0 TSC->CR |= (uint32_t)((uint32_t)TSLPRM_TSC_CTPL << 24) & 0x0F000000; #endif // Set SpreadSpectrum #if TSLPRM_TSC_USE_SS > 0 TSC->CR |= (uint32_t)((uint32_t)TSLPRM_TSC_USE_SS << 16) & 0x00010000; TSC->CR |= (uint32_t)((uint32_t)TSLPRM_TSC_SSD << 17) & 0x00FE0000; TSC->CR |= (uint32_t)((uint32_t)TSLPRM_TSC_SSPSC << 15) & 0x00008000; #endif // Set Prescaler #if TSLPRM_TSC_PGPSC > 0 TSC->CR |= (uint32_t)((uint32_t)TSLPRM_TSC_PGPSC << 12) & 0x00007000; #endif // Set Max Count #if TSLPRM_TSC_MCV > 0 TSC->CR |= (uint32_t)((uint32_t)TSLPRM_TSC_MCV << 5) & 0x000000E0; #endif // Set IO default in Output PP Low to discharge all capacitors TSC->CR &= (uint32_t)(~(1 << 4)); // Set Synchronization Mode #if TSLPRM_TSC_AM > 0 // Set Synchronization Pin in Alternate-Function mode #if TSLPRM_TSC_SYNC_PIN == 0 // PB08 RCC->AHBENR |= RCC_AHBENR_GPIOBEN; // Set GPIOB clock GPIOB->MODER &= 0xFFFCFFFF; GPIOB->MODER |= 0x00020000; GPIOB->AFR[1] |= 0x00000003; #endif #if TSLPRM_TSC_SYNC_PIN == 1 // PB10 RCC->AHBENR |= RCC_AHBENR_GPIOBEN; // Set GPIOB clock GPIOB->MODER &= 0xFFCFFFFF; GPIOB->MODER |= 0x00200000; GPIOB->AFR[1] |= 0x00000300; #endif #if TSLPRM_TSC_SYNC_PIN == 2 // PA15 RCC->AHBENR |= RCC_AHBENR_GPIOAEN; // Set GPIOA clock GPIOA->MODER &= 0x3FFFFFFF; GPIOA->MODER |= 0x80000000; GPIOA->AFR[1] |= 0x30000000; #endif // Set Synchronization Polarity TSC->CR |= (uint32_t)((uint32_t)TSLPRM_TSC_SYNC_POL << 3) & 0x00000008; // Set acquisition mode TSC->CR |= (uint32_t)((uint32_t)TSLPRM_TSC_AM << 2) & 0x00000004; #endif #if TSLPRM_USE_ACQ_INTERRUPT > 0 // Set both EOA and MCE interrupts TSC->IER |= 0x03; // Configure NVIC NVIC_SetPriority(EXTI2_TS_IRQn, 0); NVIC_EnableIRQ(EXTI2_TS_IRQn); #endif // Initialize the delay that will be used to discharge the capacitors DelayDischarge = (uint32_t)((TSLPRM_DELAY_DISCHARGE_ALL * (uint32_t)(SystemCoreClock/1000000)) / 72); return TSL_STATUS_OK; }
/** * @brief Initializes the acquisition module. * @param None * @retval Status */ TSL_Status_enum_T TSL_acq_Init(void) { #if TSLPRM_TSC_GPIO_CONFIG > 0 TSL_acq_InitGPIOs(); #endif // Enable TSC clock RCC->AHBENR |= RCC_AHBENR_TSEN; // TSC enabled TSC->CR = 0x01; // Set CTPH TSC->CR |= (uint32_t)((uint32_t)TSLPRM_TSC_CTPH << 28) & 0xF0000000; // Set CTPL TSC->CR |= (uint32_t)((uint32_t)TSLPRM_TSC_CTPL << 24) & 0x0F000000; // Set SpreadSpectrum TSC->CR |= (uint32_t)((uint32_t)TSLPRM_TSC_USE_SS << 16) & 0x00010000; TSC->CR |= (uint32_t)((uint32_t)TSLPRM_TSC_SSD << 17) & 0x00FE0000; TSC->CR |= (uint32_t)((uint32_t)TSLPRM_TSC_SSPSC << 15) & 0x00008000; // Set Prescaler TSC->CR |= (uint32_t)((uint32_t)TSLPRM_TSC_PGPSC << 12) & 0x00007000; // Set Max Count TSC->CR |= (uint32_t)((uint32_t)TSLPRM_TSC_MCV << 5) & 0x000000E0; // Set IO default in Output PP Low to discharge all capacitors TSC->CR &= (uint32_t)(~(1 << 4)); // Set Synchronization Mode #if TSLPRM_TSC_AM > 0 // Set Synchronization Pin in Alternate-Function mode RCC->AHBENR |= RCC_AHBENR_GPIOBEN; // Set GPIOB clock #if TSLPRM_TSC_SYNC_PIN == 0 // PB08 GPIOB->MODER &= 0xFFFCFFFF; GPIOB->MODER |= 0x00020000; GPIOB->AFR[1] |= 0x00000003; #else // PB10 GPIOB->MODER &= 0xFFCFFFFF; GPIOB->MODER |= 0x00200000; GPIOB->AFR[1] |= 0x00000300; #endif // Set Synchronization Polarity TSC->CR |= (uint32_t)((uint32_t)TSLPRM_TSC_SYNC_POL << 3) & 0x00000008; #endif // Set acquisition mode TSC->CR |= (uint32_t)((uint32_t)TSLPRM_TSC_AM << 2) & 0x00000004; #if TSLPRM_USE_ACQ_INTERRUPT > 0 // Set both EOA and MCE interrupts TSC->IER |= 0x03; // Configure NVIC NVIC_SetPriority(TS_IRQn, 0); NVIC_EnableIRQ(TS_IRQn); #endif return TSL_STATUS_OK; }