void Timer0AIntHandler(void){
static char flag = 0;
if(flag){
GPIOPinWrite(SONAR_PORT,TRIG_PIN,0);
TimerIntDisable(TIMER0_BASE, TIMER_TIMA_MATCH);
TimerIntEnable(TIMER0_BASE, TIMER_TIMA_TIMEOUT);
flag = 0;
}else{
GPIOPinWrite(SONAR_PORT,TRIG_PIN,1);
TimerIntDisable(TIMER0_BASE, TIMER_TIMA_TIMEOUT);
TimerIntEnable(TIMER0_BASE, TIMER_TIMA_MATCH);
flag = 1;
}
}
void CommutationControllerClass::releasePeripherals()
{
TimerIntDisable(TIMER_BASE, TIMER_TIMA_TIMEOUT);
TimerIntUnregister(TIMER_BASE, TIMER_A);
TimerDisable(TIMER_BASE, TIMER_A);
SysCtlPeripheralDisable(SYSCTL_PERIPH_TIMER);
}
void mode2unset()
{
GPIOIntClear(GPIO_PORTF_BASE, GPIO_PIN_4); //Clear any existing interrupts
GPIOIntDisable(GPIO_PORTF_BASE, GPIO_PIN_4); //Enable the GPIO Interrupts on Port F
IntDisable(INT_TIMER1A);
TimerIntDisable(TIMER1_BASE,TIMER_TIMA_TIMEOUT);
}
//*****************************************************************************
//
// The interrupt handler for the Timer0B interrupt.
//
//*****************************************************************************
void
Timer0BIntHandler(void)
{
//
// Clear the timer interrupt flag.
//
TimerIntClear(TIMER0_BASE, TIMER_TIMB_TIMEOUT);
//
// Update the periodic interrupt counter.
//
g_ui32Counter++;
//
// Once NUMBER_OF_INTS interrupts have been received, turn off the
// TIMER0B interrupt.
//
if(g_ui32Counter == NUMBER_OF_INTS)
{
//
// Disable the Timer0B interrupt.
//
IntDisable(INT_TIMER0B);
//
// Turn off Timer0B interrupt.
//
TimerIntDisable(TIMER0_BASE, TIMER_TIMB_TIMEOUT);
//
// Clear any pending interrupt flag.
//
TimerIntClear(TIMER0_BASE, TIMER_TIMB_TIMEOUT);
}
}
void mode3unset()
{
IntDisable(INT_TIMER4A);
TimerIntDisable(TIMER4_BASE, TIMER_TIMA_TIMEOUT);
TimerDisable(WTIMER0_BASE, TIMER_A);
TimerDisable(TIMER4_BASE, TIMER_A);
}
//PID控制结束，并让电机停止运行
void PID_Stop(void) {
TimerIntDisable(PID_TIMER, TIMER_TIMA_TIMEOUT);
PID_G = 0;
Motor_G = 0;
PID_Param_Clear();
Motor_SetDir(1, 1);
Motor_SetPWM_And_Move(1, 1);
}
void SCCBStop(void){
//
// Enable the timer interrupt.
// TODO: change this to whichever timer interrupt you are using.
//
GPIOPinWrite(SCCBMaster.GpioBase, SCCBMaster.sdaGpio,SCCBMaster.sdaGpio);
SCCBMaster.state=SCCB_DONE;
IntDisable(INT_TIMER0A);
TimerIntDisable(TIMER0_BASE, TIMER_TIMA_TIMEOUT);
TimerIntClear(TIMER0_BASE, TIMER_TIMA_TIMEOUT);
}
/**
* \brief The systick interrupt service routine (ISR) which will be called every millisecond
*
* This ISR will increase the systick_ms variable and reset the interrupt flags.
*
* \return none
**/
void systick_isr_C(void) {
/* Disable the timer interrupt */
TimerIntDisable(SOC_TMR_0_REGS, TMR_INT_TMR34_NON_CAPT_MODE);
/* Clear the interrupt status in AINTC and in timer */
IntSystemStatusClear(SYS_INT_TINT34_0);
TimerIntStatusClear(SOC_TMR_0_REGS, TMR_INT_TMR34_NON_CAPT_MODE);
++systick_ms;
/* Enable the timer interrupt */
TimerIntEnable(SOC_TMR_0_REGS, TMR_INT_TMR34_NON_CAPT_MODE);
}
void readDataBit(){
if(dataBitReadStatus < 40){
switch(bitTimingStatus){
case 0:
HWREG(GPIO_PORTB | GPIO_OFFSET_INTERRUPT_CLEAR) |= 0x02;
bitEntryTime = count1uS;
endTimeControlModule();
bitTimingStatus = 1;
break;
case 1:
HWREG(GPIO_PORTB | GPIO_OFFSET_INTERRUPT_CLEAR) |= 0x02;
bitExitTime = count1uS;
bitTimeElapsed();
initTimeControlModule();
bitTimingStatus = 0;
count1uS = 0;
break;
}
}
else{
convertTimetoBits();
decodeData();
IntDisable(INT_GPIOB);
IntMasterDisable();
IntDisable(INT_TIMER0A);
TimerDisable(TIMER0_BASE, TIMER_A);
TimerIntDisable(TIMER0_BASE, TIMER_TIMA_TIMEOUT);
IntDisable(INT_TIMER1A);
TimerDisable(TIMER1_BASE, TIMER_A);
TimerIntDisable(TIMER1_BASE, TIMER_TIMA_TIMEOUT);
dhtSetInactive();
}
}
void PID_Init_Timer(void) {
uint32_t ui32SystemClock;
SysCtlPeripheralEnable(PID_TIMER_PERIPH);
//设置为周期性定时器
TimerConfigure(PID_TIMER, TIMER_CFG_PERIODIC);
//设置为系统时钟 50MHz
TimerClockSourceSet(PID_TIMER, TIMER_CLOCK_SYSTEM);
ui32SystemClock = SysCtlClockGet();
//50,000-1就是1ms, 50-1就是1us
TimerLoadSet(PID_TIMER, TIMER_A, ui32SystemClock / 1000 * PID_DELAY_TIME - 1);
TimerIntRegister(PID_TIMER, TIMER_A, PIDTimerIntHandler);
TimerIntClear(PID_TIMER, TIMER_TIMA_TIMEOUT);
//开始计时
TimerEnable(PID_TIMER, TIMER_A);
//不允许处理中断（开始时开启）
TimerIntDisable(PID_TIMER, TIMER_TIMA_TIMEOUT);
}
/*
* Initializes timer to trigger an overflow interrupt every 1/SHT1X_CLOCK_HZ seconds.
* The function also configures uDMA to trigger timer's interrupt handler.
*
* If uDMA is enabled and its transaction is in progress it blocks normal interrupt
* flow of the timer.
*/
void sht1x_timer_init(void)
{
SysCtlPeripheralEnable(SHT1X_TIMER_PERIPH);
IntDisable(SHT1X_TIMER_INTERRUPT);
TimerIntDisable(SHT1X_TIMER_BASE, TIMER_TIMA_TIMEOUT);
TimerDisable(SHT1X_TIMER_BASE, SHT1X_TIMER);
TimerConfigure(SHT1X_TIMER_BASE, TIMER_CFG_A_PERIODIC);
TimerPrescaleSet(SHT1X_TIMER_BASE, SHT1X_TIMER, 0);
TimerClockSourceSet(SHT1X_TIMER_BASE, TIMER_CLOCK_SYSTEM);
TimerLoadSet(SHT1X_TIMER_BASE, SHT1X_TIMER, SHT1X_CLK_NR);
TimerDMAEventSet(SHT1X_TIMER_BASE, TIMER_DMA_TIMEOUT_A);
TimerIntClear(SHT1X_TIMER_BASE, TIMER_TIMA_TIMEOUT);
IntEnable(SHT1X_TIMER_INTERRUPT);
}
void Timer0BIntHandler(void)
{
TimerIntClear(GPTIMER3_BASE, GPTIMER_TIMA_TIMEOUT);
TimerInterrupt = 1;
IntDisable(INT_TIMER3A);
//
// Turn off Timer0B interrupt.
//
TimerIntDisable(GPTIMER3_BASE, GPTIMER_TIMA_TIMEOUT);
//
// Clear any pending interrupt flag.
//
TimerIntClear(GPTIMER3_BASE, GPTIMER_TIMA_TIMEOUT);
}
/*
** Timer Interrupt Service Routine
*/
static void TimerIsr(void)
{
/* Disable the timer interrupt */
TimerIntDisable(SOC_TMR_2_REGS, TMR_INT_TMR12_NON_CAPT_MODE);
#ifdef _TMS320C6X
/* Clear interrupt status in DSPINTC */
IntEventClear(SYS_INT_T64P2_TINTALL);
#else
/* Clear the interrupt status in AINTC */
IntSystemStatusClear(SYS_INT_TIMR2_ALL);
#endif
TimerIntStatusClear(SOC_TMR_2_REGS, TMR_INT_TMR12_NON_CAPT_MODE);
/* Signal application to print a new character */
flagIsrCnt = 1;
/* Enable the timer interrupt */
TimerIntEnable(SOC_TMR_2_REGS, TMR_INT_TMR12_NON_CAPT_MODE);
}
void CommutationControllerClass::configurePeripherals(uint32_t channel)
{
channel ? initAsTimer1() : initAsTimer0();
// Enable the timer peripheral
SysCtlPeripheralEnable(SYSCTL_PERIPH_TIMER);
// Ensure the timer is disabled
TimerDisable(TIMER_BASE, TIMER_A);
// Configure the timer as a periodic up counter
TimerConfigure(TIMER_BASE, TIMER_CFG_PERIODIC_UP);
// Ensure the timer interrupt is disabled
TimerIntDisable(TIMER_BASE, TIMER_TIMA_TIMEOUT);
// Clear the interrupt now it is disabled
TimerIntClear(TIMER_BASE, TIMER_TIMA_TIMEOUT);
// Register one of the two static interrupt handlers to the peripheral
TimerIntRegister(TIMER_BASE, TIMER_A, channel ? ISR1Static : ISR0Static);
// Set the interrupt priority
IntPrioritySet(INT_TIMERnA_TM4C123, 0); // @TODO - What should this actually be?
}
void CommutationControllerClass::disableTimerInterrupt()
{
TimerIntDisable(TIMER_BASE, TIMER_TIMA_TIMEOUT);
}
// ************ OS_Init ******************
// initialize operating system, disable interrupts until OS_Launch
// initialize OS controlled I/O: serial, ADC, systick, select switch and timer2
// input: none
// output: non
void OS_Init(void) {
int i; // Used for indexing
// Disable interrupts
OS_DisableInterrupts();
// Setting the clock to 50 MHz
SysCtlClockSet(SYSCTL_SYSDIV_4 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_8MHZ);
// Initialze peripherals
UART0_Init();
ADC_Open();
Output_Init();
// Select switch
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);
GPIOPinTypeGPIOInput(GPIO_PORTF_BASE, GPIO_PIN_1);
GPIOPadConfigSet(GPIO_PORTF_BASE, GPIO_PIN_1, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD_WPU);
GPIOIntTypeSet(GPIO_PORTF_BASE, GPIO_PIN_1, GPIO_RISING_EDGE);
GPIOPinIntClear(GPIO_PORTF_BASE, GPIO_PIN_1);
// Down switch
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOE);
GPIOPinTypeGPIOInput(GPIO_PORTE_BASE, GPIO_PIN_1);
GPIOPadConfigSet(GPIO_PORTE_BASE, GPIO_PIN_1, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD_WPU);
GPIOIntTypeSet(GPIO_PORTE_BASE, GPIO_PIN_1, GPIO_RISING_EDGE);
GPIOPinIntClear(GPIO_PORTE_BASE, GPIO_PIN_1);
// Initialize Timer2A and Timer2B: Periodic Background Threads
SysCtlPeripheralEnable(SYSCTL_PERIPH_TIMER2);
TimerDisable(TIMER2_BASE, TIMER_A | TIMER_B);
TimerConfigure(TIMER2_BASE, TIMER_CFG_16_BIT_PAIR | TIMER_CFG_A_PERIODIC | TIMER_CFG_B_PERIODIC);
// Initialize Timer0B: Used for time keeping
TimerDisable(TIMER0_BASE, TIMER_B);
TimerConfigure(TIMER0_BASE, TIMER_CFG_16_BIT_PAIR | TIMER_CFG_A_PERIODIC | TIMER_CFG_B_PERIODIC);
TimerIntDisable(TIMER0_BASE, TIMER_TIMB_TIMEOUT);
TimerLoadSet(TIMER0_BASE, TIMER_B, 65535);
TimerPrescaleSet(TIMER0_BASE, TIMER_B, 5); // One unit is 100ns
TimerEnable(TIMER0_BASE, TIMER_B);
// Initialize Timer1A: Used for sleep decrementing
SysCtlPeripheralEnable(SYSCTL_PERIPH_TIMER1);
TimerDisable(TIMER1_BASE, TIMER_A);
TimerConfigure(TIMER1_BASE, TIMER_CFG_16_BIT_PAIR | TIMER_CFG_A_PERIODIC | TIMER_CFG_B_PERIODIC);
TimerIntDisable(TIMER1_BASE, TIMER_TIMA_TIMEOUT);
TimerLoadSet(TIMER1_BASE, TIMER_A, 50000); // Every interrupt is 1ms
// Setting priorities for all interrupts
// To add more, look up correct names in inc\hw_ints.h
IntPrioritySet(FAULT_PENDSV, (0x07 << 5));
IntPrioritySet(FAULT_SYSTICK, (0x06 << 5));
IntPrioritySet(INT_TIMER1A, (0x02 << 5));
IntPrioritySet(INT_UART0, (0x03 << 5));
IntPrioritySet(INT_ADC0SS0, (0x01 << 5));
IntPrioritySet(INT_ADC0SS3, (0x01 << 5));
// Initializing TCBs
for(i = 0; i < MAXTHREADS; i++) {
tcbs[i].valid = INVALID;
tcbs[i].blockedState = '\0';
}
RunPt = &tcbs[0]; // Thread 0 will run first
}
/******** Timer_IntDisable **************************************************
// Disable timer interrupt
// Input: timer is one of the Timer_T value ( Timer1A, Timer1B... )
// Output: none
// ------------------------------------------------------------------------*/
void Timer_IntDisable ( Timer_T timer )
{
TimerIntDisable ( Timer_Base[timer], Timer_IntFlag[timer]);
IntDisable ( Timer_Int[timer] );
}
//*****************************************************************************
//
//! \brief xtimer 001 test execute main body.
//!
//! \return None.
//
//*****************************************************************************
static void xTimer001Execute(void)
{
unsigned long ulTemp;
unsigned long ulBase;
int i, j, k;
//
// Test the register write and read.
//
for(i = 0; i < 2; i++)
{
ulBase = ulTimerBase[i];
for(j = 0; j < 4; j++)
{
xTimerInitConfig(ulBase, ulTimerChannel[j], xTIMER_MODE_PERIODIC |
xTIMER_COUNT_UP, 100);
ulTemp = xHWREG(ulBase + TIMER_PSCR);
TestAssert(ulTemp == 2,
"xtimer API \"xTimerInitConfig- prescale \" error");
ulTemp = xHWREG(ulBase + TIMER_CRR);
TestAssert(ulTemp == 40000,
"xtimer API \"xTimerInitConfig- CRR \" error");
ulTemp = xHWREG(ulBase + TIMER_CNTCFR) & TIMER_CNTCFR_DIR;
TestAssert(ulTemp == xTIMER_COUNT_UP,
"xtimer API \"xTimerInitConfig- DIR \" error");
xTimerInitConfig(ulBase, ulTimerChannel[j], xTIMER_MODE_TOGGLE |
xTIMER_COUNT_UP, 100);
ulTemp = xHWREG(ulBase + TIMER_CH0OCFR + ulTimerChannel[j] * 4) &
TIMER_CH0OCFR_CH0OM_M;
TestAssert(ulTemp == TIMER_CH0OCFR_CH0OM_TOGGLE,
"xtimer API \"xTimerInitConfig- DIR \" error");
ulTemp = xHWREG(ulBase + TIMER_CH0CCR + ulTimerChannel[j] * 4);
TestAssert(ulTemp == 20000,
"xtimer API \"xTimerInitConfig- DIR \" error");
//
// Prescale set and get test
//
xTimerPrescaleSet(ulBase, ulTimerChannel[j], 1000);
ulTemp = xTimerPrescaleGet(ulBase, ulTimerChannel[j]);
TestAssert(ulTemp == 1000,
"xtimer API \"Prescale set and get test \" error");
//
// Match set and get test
//
xTimerMatchSet(ulBase, ulTimerChannel[j], 1000);
ulTemp = xTimerMatchGet(ulBase, ulTimerChannel[j]);
TestAssert(ulTemp == 1000,
"xtimer API \"Match set and get test \" error");
//
// xINT enable test
//
xTimerIntEnable(ulBase, ulTimerChannel[j], xTIMER_INT_CAP_EVENT);
ulTemp = xHWREG(ulBase + TIMER_ICTR) & (TIMER_CHCTR_CH0CCIE << ulTimerChannel[j]);
TestAssert(ulTemp == TIMER_CHCTR_CH0CCIE << ulTimerChannel[j],
"xtimer API \"xINT enable test \" error");
//
// xINT disable test
//
xTimerIntDisable(ulBase, ulTimerChannel[j], xTIMER_INT_CAP_EVENT);
ulTemp = xHWREG(ulBase + TIMER_ICTR) & (TIMER_CHCTR_CH0CCIE << ulTimerChannel[j]);
TestAssert(ulTemp == 0,
"xtimer API \"xINT disable test \" error");
}
//
// xTimer start test
//
xTimerStart(ulBase, ulTimerChannel[0]);
ulTemp = xHWREG(ulBase + TIMER_CTR) & TIMER_CTR_TME;
TestAssert(ulTemp == TIMER_CTR_TME,
"xtimer API \"xTimer start test \" error");
//
// xTimer stop test
//
xTimerStop(ulBase, ulTimerChannel[0]);
ulTemp = xHWREG(ulBase + TIMER_CTR) & TIMER_CTR_TME;
TestAssert(ulTemp == 0,
"xtimer API \"xTimer stop test \" error");
//*********************************************************************
// Timer base configure test
//*********************************************************************
//
// Counter mode test
//
for(j = 0; j < 5; j++)
{
TimeBaseConfigure(ulBase, ulTimerMode[j], 100, 100, ulTimerReloadMode[0]);
ulTemp = xHWREG(ulBase + TIMER_CNTCFR) & 0xFFFF0000;
TestAssert(ulTemp == ulTimerMode[j],
"xtimer API \"Timer base configure -counter mode \" error");
}
//
// Counter reload set test
//
for(j = 0; j < 3; j++)
{
TimeBaseConfigure(ulBase, ulTimerMode[0], ulTimerCRRData[j],
100, ulTimerReloadMode[0]);
ulTemp = TimerCRRGet(ulBase);
TestAssert(ulTemp == ulTimerCRRData[j],
"xtimer API \"Timer base configure -CRR set \" error");
}
//
// Counter prescale set test
//
for(j = 0; j < 3; j++)
{
TimeBaseConfigure(ulBase, ulTimerMode[0], ulTimerCRRData[0],
ulTimerPrescaleData[j], ulTimerReloadMode[0]);
ulTemp = TimerPerscalerGet(ulBase);
TestAssert(ulTemp == ulTimerPrescaleData[j],
"xtimer API \"Timer base configure -PSC set \" error");
}
//
// Counter reload mode test
//
/*
for(j = 0; j < 2; j++)
{
TimeBaseConfigure(ulBase, ulTimerMode[0], ulTimerCRRData[0],
ulTimerPrescaleData[j], ulTimerReloadMode[j]);
ulTemp = xHWREG(ulBase + TIMER_EVGR) & TIMER_EVGR_UEVG;
TestAssert(ulTemp == ulTimerReloadMode[j],
"xtimer API \"Timer base configure -RM set \" error");
}
*/
for(j = 0; j < 4; j++)
{
//
// Output enable test
//
for(k = 0; k < 2; k++)
{
TimerOutputConfigure(ulBase, ulTimerChannel[j], ulTimerOutputEnable[k],
ulTimeCHPolarity[0], ulTimerOutputMode[0],
ulTimerCmpValue[0]);
ulTemp = xHWREG(ulBase + TIMER_CHCTR) & (1 << (ulTimerChannel[j] * 2));
TestAssert(ulTemp == (ulTimerOutputEnable[k] << (ulTimerChannel[j] * 2)),
"xtimer API \"Output enable set test\" error");
}
//
// Channel polarity
//
for(k = 0; k < 2; k++)
{
TimerOutputConfigure(ulBase, ulTimerChannel[j], ulTimerOutputEnable[0],
ulTimeCHPolarity[k], ulTimerOutputMode[0],
ulTimerCmpValue[0]);
ulTemp = xHWREG(ulBase + TIMER_CHPOLR) & (1 << (ulTimerChannel[j] * 2));
TestAssert(ulTemp == ulTimeCHPolarity[k] << (ulTimerChannel[j] * 2),
"xtimer API \"Channel polarity set test\" error");
}
//
// Output Mode test
//
for(k = 0; k < 6; k++)
{
TimerOutputConfigure(ulBase, ulTimerChannel[j], ulTimerOutputEnable[0],
ulTimeCHPolarity[0], ulTimerOutputMode[k],
ulTimerCmpValue[0]);
ulTemp = xHWREG(ulBase + TIMER_CH0OCFR + ulTimerChannel[j] * 4) &
TIMER_CH0OCFR_CH0OM_M;
TestAssert(ulTemp == ulTimerOutputMode[k],
"xtimer API \"Output Mode set test\" error");
}
//
// Compare value set test
//
for(k = 0; k < 3; k++)
{
TimerOutputConfigure(ulBase, ulTimerChannel[j], ulTimerOutputEnable[0],
ulTimeCHPolarity[0], ulTimerOutputMode[0],
ulTimerCmpValue[k]);
ulTemp = TimerCaptureCompareGet(ulBase, ulTimerChannel[j]);
TestAssert(ulTemp == ulTimerCmpValue[k],
"xtimer API \"Compare value set test\" error");
}
//
// Capture source select test
//
for(k = 0; k < 3; k++)
{
TimerCaptureConfigure(ulBase, ulTimerChannel[j], ulTimeCHPolarity[0],
ulSelect[k], ulPrescaler[0], ucFilter[0]);
ulTemp = xHWREG(ulBase + TIMER_CH0ICFR + ulTimerChannel[j] * 4) &
TIMER_CH0ICFR_CH0CCS_M;
TestAssert(ulTemp == ulSelect[k],
"xtimer API \"Capture source select test\" error");
}
//
// Capture prescale select test
//
for(k = 0; k < 4; k++)
{
TimerCaptureConfigure(ulBase, ulTimerChannel[j], ulTimeCHPolarity[0],
ulSelect[0], ulPrescaler[k], ucFilter[0]);
ulTemp = xHWREG(ulBase + TIMER_CH0ICFR + ulTimerChannel[j] * 4) &
TIMER_CH0ICFR_CH0PSC_M;
TestAssert(ulTemp == ulPrescaler[k],
"xtimer API \"Capture prescale select test\" error");
}
//
// Capture filter select test
//
for(k = 0; k < 3; k++)
{
TimerCaptureConfigure(ulBase, ulTimerChannel[j], ulTimeCHPolarity[0],
ulSelect[0], ulPrescaler[0], ucFilter[k]);
ulTemp = xHWREG(ulBase + TIMER_CH0ICFR + ulTimerChannel[j] * 4) &
TIMER_CH0ICFR_TI0F_M;
TestAssert(ulTemp == ucFilter[k],
"xtimer API \"Capture filter select test\" error");
}
//
// Forces CHxOREF waveform to active or inactive
//
for(k = 0; k < 2; k++)
{
TimerForcedOREF(ulBase, ulTimerChannel[j], ulForcedAction[k]);
ulTemp = xHWREG(ulBase + TIMER_CH0OCFR + ulTimerChannel[j] * 4)
& TIMER_CH0OCFR_CH0OM_M;
TestAssert(ulTemp == ulForcedAction[k],
"xtimer API \"Forces CHxOREF waveform set test\" error");
}
//
// Timer one pulse active configure
//
/*
for(k = 0; k < 2; k++)
{
Timer1PulseActiveConfigure(ulBase, ulTimerChannel[j], ulActive[k]);
ulTemp = xHWREG(ulBase + TIMER_CH0OCFR + ulTimerChannel[j] * 4) &
TIMER_CH0OCFR_CH0IMAE;
TestAssert(ulTemp == ulActive[k],
"xtimer API \" Timer one pulse active configure\" error");
}
*/
//
// Channel enable test
//
for(k = 0; k < 2; k++)
{
TimerCHConfigure(ulBase, ulTimerChannel[j], ulControl[k]);
ulTemp = xHWREG(ulBase + TIMER_CHCTR) & (1 << (ulTimerChannel[j] * 2));
TestAssert(ulTemp == (ulControl[k] << (ulTimerChannel[j] * 2)),
"xtimer API \" Channel enable test\" error");
}
}
//
// Timer start test
//
TimerStart(ulBase);
ulTemp = xHWREG(ulBase + TIMER_CTR) & TIMER_CTR_TME;
TestAssert(ulTemp == TIMER_CTR_TME,
"xtimer API \"Timer start test \" error");
//
// Timer stop test
//
TimerStop(ulBase);
ulTemp = xHWREG(ulBase + TIMER_CTR) & TIMER_CTR_TME;
TestAssert(ulTemp == 0,
"xtimer API \"Timer stop test \" error");
//
// ITI0 as the clock source test
//
TimerITIExtClkConfigure(ulBase, TIMER_TRSEL_ITI0);
ulTemp = xHWREG(ulBase + TIMER_TRCFR) & TIMER_TRCFR_TRSEL_M;
TestAssert(ulTemp == TIMER_TRSEL_ITI0,
"xtimer API \"Timer stop test \" error");
ulTemp = xHWREG(ulBase + TIMER_MDCFR) & TIMER_MDCFR_SMSEL_STIED;
TestAssert(ulTemp == TIMER_MDCFR_SMSEL_STIED,
"xtimer API \"Timer stop test \" error");
//
// ETI prescaler set test
//
for(k = 0; k < 4; k++)
{
TimerETIExtClkConfigure(ulBase, ulEXIPrescaleValue[k],
ulEXIPolarity[0], ucFilter[0]);
ulTemp = xHWREG(ulBase + TIMER_TRCFR) & TIMER_TRCFR_ETIPSC_M;
TestAssert(ulTemp == ulEXIPrescaleValue[k],
"xtimer API \"ETI prescaler set test \" error");
}
//
// ETI polarity set test
//
for(k = 0; k < 2; k++)
{
TimerETIExtClkConfigure(ulBase, ulEXIPrescaleValue[0],
ulEXIPolarity[k], ucFilter[0]);
ulTemp = xHWREG(ulBase + TIMER_TRCFR) & TIMER_TRCFR_ETIPOL;
TestAssert(ulTemp == ulEXIPolarity[k],
"xtimer API \"ETI polarity set test \" error");
}
//
// ETI filter set test
//
for(k = 0; k < 3; k++)
{
TimerETIExtClkConfigure(ulBase, ulEXIPrescaleValue[0],
ulEXIPolarity[0], ucFilter[k]);
ulTemp = xHWREG(ulBase + TIMER_TRCFR) & TIMER_TRCFR_ETF_M;
TestAssert(ulTemp == (ucFilter[k] << 8),
"xtimer API \"ETI filter set test \" error");
}
//
// ETI enable set test
//
ulTemp = xHWREG(ulBase + TIMER_TRCFR) & TIMER_TRCFR_ECME ;
TestAssert(ulTemp == TIMER_TRCFR_ECME,
"xtimer API \" ETI enable set test \" error");
//
// Prescaler update configure
//
/*
for(k = 0; k < 2; k++)
{
TimerPrescalerConfigure(ulBase, ulTimerPrescaleData[0], ulPSCReloadTime[k]);
ulTemp = xHWREG(ulBase + TIMER_EVGR) & TIMER_EVGR_UEVG;
TestAssert(ulTemp == ulPSCReloadTime[k],
"xtimer API \" Prescaler update configure \" error");
}
*/
//
// Decode mode set test
//
for(k = 0; k < 3; k++)
{
TimerDecoderConfigure(ulBase, ulDecodeMode[k], TIMER_CHP_NONINVERTED,
TIMER_CHP_NONINVERTED);
ulTemp = xHWREG(ulBase + TIMER_MDCFR) & TIMER_MDCFR_SMSEL_M;
TestAssert(ulTemp == ulDecodeMode[k],
"xtimer API \" Decode mode set test \" error");
}
//
// CRR preload configure
//
/*
for(k = 0; k < 2; k++)
{
TimerCRRPreloadConfigure(ulBase, ulProload[k]);
ulTemp = xHWREG(ulBase + TIMER_CTR) & TIMER_CTR_CRBE;
TestAssert(ulTemp == ulProload[k],
"xtimer API \" CRR preload configure \" error");
}
*/
//
// One pulse mode test
//
for(k = 0; k < 2; k++)
{
TimerOnePulseModeConfigure(ulBase, ulOnepulseMode[k]);
ulTemp = xHWREG(ulBase + TIMER_MDCFR) & TIMER_MDCFR_SPMSET;
TestAssert(ulTemp == ulOnepulseMode[k],
"xtimer API \" One pulse mode test \" error");
}
//
// Timer master output source select
//
for(k = 0; k < 8; k++)
{
TimerMasterOutputSrcSelect(ulBase, ulMasterOutputSrc[k]);
ulTemp = xHWREG(ulBase + TIMER_MDCFR) & TIMER_MDCFR_MMSEL_M;
TestAssert(ulTemp == ulMasterOutputSrc[k],
"xtimer API \" Timer master output source select \" error");
}
//
// Slave mode set configure
//
for(k = 0; k < 4; k++)
{
TimerSlaveModeConfigure(ulBase, ulSlaveMode[k]);
ulTemp = xHWREG(ulBase + TIMER_MDCFR) & TIMER_MDCFR_SMSEL_M;
TestAssert(ulTemp == ulSlaveMode[k],
"xtimer API \" Slave mode set configure \" error");
}
//
// Counter set and get test
//
for(k = 0; k < 3; k++)
{
TimerCounterSet(ulBase, ulTimerCounter[k]);
ulTemp = TimerCounterGet(ulBase);
TestAssert(ulTemp == ulTimerCounter[k],
"xtimer API \" Counter set and get test \" error");
}
//
// Event generate test
//
for(k = 0; k < 6; k++)
{
TimerEventGenerate(ulBase, ulEvent[k]);
ulTemp = TimerFlagStatusGet(ulBase, ulEvent[k]);
TestAssert(ulTemp == xtrue,
"xtimer API \" Event generate test \" error");
}
//
// Int enable test
//
for(k = 0; k < 6; k++)
{
TimerIntEnable(ulBase, ulInt[k]);
ulTemp = xHWREG(ulBase + TIMER_ICTR) & ulInt[k];
TestAssert(ulTemp == ulInt[k],
"xtimer API \" Int enable test \" error");
}
//
// Int disable test
//
for(k = 0; k < 6; k++)
{
TimerIntDisable(ulBase, ulInt[k]);
ulTemp = xHWREG(ulBase + TIMER_ICTR) & ulInt[k];
TestAssert(ulTemp == 0,
"xtimer API \" Int disable test \" error");
}
}
}
