int
uart_cpu_getdev(int devtype, struct uart_devinfo *di)
{
uint32_t i, ivar, vaddr;
/*
* Scan the hints. The IXP425 only have 2 serial ports, so only
* scan them.
*/
for (i = 0; i < 2; i++) {
if (resource_int_value("uart", i, "flags", &ivar))
continue;
if (devtype == UART_DEV_CONSOLE && !UART_FLAGS_CONSOLE(ivar))
continue;
if (devtype == UART_DEV_DBGPORT && !UART_FLAGS_DBGPORT(ivar))
continue;
/*
* We have a possible device. Make sure it's enabled and
* that we have an I/O port.
*/
if (resource_int_value("uart", i, "disabled", &ivar) == 0 &&
ivar != 0)
continue;
if (resource_int_value("uart", i, "addr", &ivar) != 0 ||
ivar == 0)
continue;
/* Got it. Fill in the instance and return it. */
di->ops = uart_getops(&uart_ns8250_class);
di->bas.chan = 0;
di->bas.bst = &ixp425_a4x_bs_tag;
di->bas.regshft = 0;
di->bas.rclk = IXP425_UART_FREQ;
di->baudrate = 115200;
di->databits = 8;
di->stopbits = 1;
di->parity = UART_PARITY_NONE;
uart_bus_space_io = NULL;
uart_bus_space_mem = &ixp425_a4x_bs_tag;
getvbase(ivar, IXP425_REG_SIZE, &vaddr);
di->bas.bsh = vaddr;
return (0);
}
return (ENXIO);
}
int
uart_cpu_getdev(int devtype, struct uart_devinfo *di)
{
struct dig64_hcdp_table *tbl;
struct dig64_hcdp_entry *ent;
bus_addr_t addr;
unsigned int i, ivar;
/*
* Use the DIG64 HCDP table if present.
*/
if (bootinfo.bi_hcdp != 0) {
tbl = (void*)IA64_PHYS_TO_RR7(bootinfo.bi_hcdp);
for (i = 0; i < tbl->entries; i++) {
ent = tbl->entry + i;
if (devtype == UART_DEV_CONSOLE &&
ent->type != DIG64_HCDP_CONSOLE)
continue;
if (devtype == UART_DEV_DBGPORT &&
ent->type != DIG64_HCDP_DBGPORT)
continue;
addr = ent->address.addr_high;
addr = (addr << 32) + ent->address.addr_low;
di->ops = uart_ns8250_ops;
di->bas.chan = 0;
di->bas.bst = (ent->address.addr_space == 0)
? IA64_BUS_SPACE_MEM : IA64_BUS_SPACE_IO;
if (bus_space_map(di->bas.bst, addr, 8, 0,
&di->bas.bsh) != 0)
continue;
di->bas.regshft = 0;
di->bas.rclk = ent->pclock << 4;
/* We don't deal with 64-bit baud rates. */
di->baudrate = ent->baud_low;
di->databits = ent->databits;
di->stopbits = ent->stopbits;
di->parity = (ent->parity >= 6) ? UART_PARITY_NONE
: dig64_to_uart_parity[ent->parity];
return (0);
}
/* FALLTHROUGH */
}
/*
* Scan the hints for backward compatibility. We only try units
* 0 to 3 (inclusive). This covers the ISA legacy where 4 UARTs
* had their resources predefined.
*/
for (i = 0; i < 4; i++) {
if (resource_int_value("uart", i, "flags", &ivar))
continue;
if (devtype == UART_DEV_CONSOLE && !UART_FLAGS_CONSOLE(ivar))
continue;
if (devtype == UART_DEV_DBGPORT && !UART_FLAGS_DBGPORT(ivar))
continue;
/*
* We have a possible device. Make sure it's enabled and
* that we have an I/O port.
*/
if (resource_int_value("uart", i, "disabled", &ivar) == 0 &&
ivar != 0)
continue;
if (resource_int_value("uart", i, "port", &ivar) != 0 ||
ivar == 0)
continue;
/*
* Got it. Fill in the instance and return it. We only have
* ns8250 and successors on i386.
*/
di->ops = uart_ns8250_ops;
di->bas.chan = 0;
di->bas.bst = IA64_BUS_SPACE_IO;
if (bus_space_map(di->bas.bst, ivar, 8, 0, &di->bas.bsh) != 0)
continue;
di->bas.regshft = 0;
di->bas.rclk = 0;
if (resource_int_value("uart", i, "baud", &ivar) != 0)
ivar = 0;
di->baudrate = ivar;
di->databits = 8;
di->stopbits = 1;
di->parity = UART_PARITY_NONE;
return (0);
}
return (ENXIO);
}
