/*---------------------------------------------------------------------------------------------------------*/
void DrvPMU_DeepSleep(void)
{
UNLOCKREG();
SYSCLK->PWRCON.STOP = 0;
SYSCLK->PWRCON.STANDBY_PD = 0;
SYSCLK->PWRCON.DEEP_PD = 0;
SCB->SCR = SCB_SCR_SLEEPDEEP;
LOCKREG();
__wfi();
}
/*---------------------------------------------------------------------------------------------------------*/
void DrvPMU_StandbyPowerDown(void)
{
UNLOCKREG();
SCB->SCR = SCB_SCR_SLEEPDEEP;
SYSCLK->PWRCON.STANDBY_PD = 1;
SYSCLK->PWRCON.STOP = 0;
SYSCLK->PWRCON.DEEP_PD = 0;
LOCKREG();
__wfi();
}
void WDT_Init()
{
UNLOCKREG();
DrvWDT_Open(E_WDT_LEVEL6);
//看门狗定时器复位使能
DrvWDT_Ioctl(E_WDT_IOC_ENABLE_RESET_FUNC, 0);
//使能看门狗定时器 WTE
DrvWDT_Ioctl(E_WDT_IOC_START_TIMER, 0);
LOCKREG();
//
}
int32_t DrvRTC_Init (void)
{
int32_t i32i =0;
volatile int32_t i32delay=1000;
/*-----------------------------------------------------------------------------------------------------*/
/* Initial time data struct and some parameters. */
/*-----------------------------------------------------------------------------------------------------*/
g_pfnRTCCallBack_Alarm = NULL;
g_pfnRTCCallBack_Tick = NULL;
g_u32RTC_Count = 0;
UNLOCKREG();
/* Enable 32K Clock */
SYSCLK->PWRCON.XTL32K_EN =1;
/* Waiting for 32K stable */
while(i32delay--);
/* Enable RTC Clock */
SYSCLK->APBCLK.RTC_EN =1;
LOCKREG();
/*-----------------------------------------------------------------------------------------------------*/
/* When RTC is power on, write 0xa5eb1357 to RTC_INIR to reset all logic. */
/*-----------------------------------------------------------------------------------------------------*/
RTC->INIR = DRVRTC_INIT_KEY;
for (i32i = 0 ; i32i < DRVRTC_WAIT_COUNT ; i32i++)
{
if(RTC->INIR == 0x1) /* Check RTC_INIR[0] to find out RTC reset signal */
{
break;
}
}
if (i32i == DRVRTC_WAIT_COUNT)
{
RTCDEBUG("\nRTC: RTC_Init, initial RTC FAILED!\n");
return E_DRVRTC_ERR_EIO;
}
return E_SUCCESS;
}
/**
* @brief Enable chip clock source and select CPU clock.
* @param None
* @return None
*/
void SysInit_Clock(void)
{
__IO uint32_t delayCnt;
/* Enable system clock source, HIRC and LIRC are default enabled */
UNLOCKREG();
CLK->PWRCTL |= (CLK_PWRCTL_HXT_EN | CLK_PWRCTL_LXT_EN);
LOCKREG();
/* Enable PLL out to 96MHz */
CLK->PLLCTL = (CLK_PLLCTL_PLLSRC_HXT | PLL_IN_12M_OUT_96M);
/* Waits for PLL clock stable */
for (delayCnt=0; delayCnt<100000; delayCnt++)
if (CLK->CLKSTATUS & CLK_CLKSTATUS_PLL_STB) break;
/* Change HCLK to PLL output */
if (delayCnt < 100000) {
CLK->CLKDIV0 = (CLK->CLKDIV0 & ~CLK_CLKDIV0_HCLK_MASK) | 2; /* divider is 3 */
UNLOCKREG();
CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_HCLK_MASK) | CLK_CLKSEL0_HCLK_PLL; /* HCLK = 32MHz */
LOCKREG();
}
/* Set HCLK back to HIRC if error happens */
if (CLK->CLKSTATUS & CLK_CLKSTATUS_CLK_SW_FAIL) {
CLK->CLKDIV0 &= ~CLK_CLKDIV0_HCLK_MASK; /* divider is 0 */
UNLOCKREG();
CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_HCLK_MASK) | CLK_CLKSEL0_HCLK_HIRC; /* HCLK = 12MHz */
LOCKREG();
}
/* Update CPU Clock Frequency */
SystemCoreClockUpdate();
}
//============================================================================
// u32addr : 0-1024
//============================================================================
uint32_t DATA_FLASH_Read(uint32_t u32add)
{
uint32_t u32data;
#ifdef M451
u32data = FMC_Read(u32add*4+DATA_Flash_Start_ADD);
#else
__set_PRIMASK(1);
UNLOCKREG();
DrvFMC_EnableISP();
DrvFMC_Read(u32add*4+DATA_Flash_Start_ADD, &u32data);
DrvFMC_DisableISP();
LOCKREG();
__set_PRIMASK(0);
#endif
return u32data;
}
void init_timer(void)
{
/* Enable clock source for timer0 */
UNLOCKREG();
CLK->PWRCTL |= CLK_PWRCTL_HIRC_EN;
while (!(CLK->CLKSTATUS & CLK_CLKSTATUS_PLL_STB));
CLK->CLKSEL1 = CLK->CLKSEL1
& ~CLK_CLKSEL1_TMR0_MASK
| CLK_CLKSEL1_TMR0_HIRC;
LOCKREG();
/* Set up timer0 and enable it's interrupt */
TIMER_Init(TIMER0, 10, 1200000, TIMER_CTL_MODESEL_PERIODIC);
TIMER_EnableInt(TIMER0, TIMER_IER_TMRIE);
TIMER_Start(TIMER0);
}
__weak void HardFault_Handler(void)
{
// while(1);
int i;
for(i=0;i<10;i++)
{
printf("HardFault!!!\r\n");
}
// printf("SP:0x%08x\n", get_sp());
delay_ms(10);
UNLOCKREG(0);
DrvSYS_ResetChip();
LOCKREG(0);
return;
}
//*****************************************************************************
//
//! \brief ADCSingleMode
//!
//! \param None
//!
//! \return None
//
//*****************************************************************************
void ADCSingleMode(void)
{
UNLOCKREG();
GCR->P5_MFP = (GCR->P5_MFP & 0x00FFFCFC) | 0x03; /* P5.1 -> XTAL2, P5.0 -> XTAL1 */
CLK->PWRCON_BITS.XTLCLK_EN = 1;
/* Waiting for 12M Xtal stalble */
while (DrvSYS_GetChipClockSourceStatus(XTL_CLK) != 1);
/* ADC sample code */
/* default setting: single end input, single operation mode, all channel disable, ADC clock frequency = 12MHz/(3+1) */
DrvADC_Open(0, EXTERNAL_CLOCK, 3);
AdcSingleModeTest();
DrvADC_Close();
}
bool flash_io_driver_initialize(void)
{
uint32_t desiredConfig0 = 0xF8FFFF7E;
uint32_t desiredConfig1 = APPLICATION_DATA_START;
uint32_t config0;
uint32_t config1;
bool fail = false;
critical_section_enter();
UNLOCKREG();
FMC_Init();
FMC_EnableAPUpdate();
LOCKREG();
if(FMC_Read(CONFIG0, &config0) != E_FMC_OK)
{
fail = true;
}
if(FMC_Read(CONFIG1, &config1) != E_FMC_OK)
{
fail = true;
}
if(fail || (desiredConfig0 != config0) || (desiredConfig1 != config1))
{
FMC_EnableConfigUpdate();
if(FMC_WriteConfig(config0, config1) != E_FMC_OK)
{
fail = true;
}
else
{
fail = false;
}
FMC_DisableConfigUpdate();
}
critical_section_exit();
return fail == false;
}
/**
* @brief Enable chip clock source and select CPU clock.
* @param None
* @return None
*/
void SysInit_Clock(void)
{
__IO uint32_t delayCnt;
/* Enable system clock source, HIRC and LIRC are default enabled */
UNLOCKREG();
CLK->PWRCTL |= (CLK_PWRCTL_HXT_EN | CLK_PWRCTL_LXT_EN);
//LOCKREG();
/* Set HCLK to HIRC*/
CLK->CLKDIV0 &= ~CLK_CLKDIV0_HCLK_MASK; /* divider is 0 */
//UNLOCKREG();
CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_HCLK_MASK) | CLK_CLKSEL0_HCLK_HIRC; /* HCLK = 12MHz */
LOCKREG();
/* Update CPU Clock Frequency */
SystemCoreClockUpdate();
}
int main (void)
{
// uint32_t Temp=0;
//================================配置系统时钟==============//
UNLOCKREG();
SYSCLK->PWRCON.OSC22M_EN = 1;//default is enabled
SYSCLK->PWRCON.XTL12M_EN = 1;
SYSCLK->CLKSEL0.HCLK_S = 0;//using 12M as HCLK src
// DrvSYS_Delay(5000);
Delay(5000) ;
DrvSYS_Open(48000000);
// DSP_INIT_PIN = 0 ;
// LCD_POWER = 1 ;
//
//===================================================================================//
BSP_INIT_UART0(); //init the uart0
GR_DBG_PRINTF("System Is run\n\n");
DrvUART_EnableInt(UART_PORT0,DRVUART_RDAINT | DRVUART_TOUTINT,UART_INT_HANDLE); //
//===================================================================================//
// Vir_Init() ; //初始化环境变量
////===============================读取dataflash存储的系统信息=========================//
//读取flash中数据 第一次运行读写写入默认值
////======================================开始任务=====================================//
OSInit();
CPU_IntDis() ;
// SysTick_Config(120000);
// InitValue();
#ifdef THREAD_TEST
OSTaskCreateExt(Task2, (void *)0, (OS_STK *)&Task2_Stack[STACK2SIZE-1], Task2_Prio,Task2_Prio,Task2_Stack,STACK2SIZE ,NULL,OS_TASK_OPT_STK_CHK);
OSTaskCreateExt(Task1, (void *)0, (OS_STK *)&Task1_Stack[STACK1SIZE-1], Task1_Prio,Task1_Prio,Task1_Stack,STACK1SIZE,NULL,OS_TASK_OPT_STK_CHK);
OSTaskCreateExt(Task3, (void *)0, (OS_STK *)&Task3_Stack[STACK3SIZE-1], Task3_Prio,Task3_Prio,Task3_Stack,STACK3SIZE,NULL,OS_TASK_OPT_STK_CHK);
// OSTaskCreate(SYS_Task, (void *)0, (OS_STK *)&SYS_Task_Stack[STACKSIZE-1],SYS_Task_Prio);
#endif
OSStart();
//===================================================================================//
}
//------------------------------
void bacarfid(){
uint8_t hasiluart[8];
STR_UART_T sParam;
UNLOCKREG();
DrvSYS_Open(50000000);
LOCKREG();
/* Set UART Pin */
DrvGPIO_InitFunction(E_FUNC_UART0);
/* UART Setting */
sParam.u32BaudRate = 9600;
sParam.u8cDataBits = DRVUART_DATABITS_8;
sParam.u8cStopBits = DRVUART_STOPBITS_1;
sParam.u8cParity = DRVUART_PARITY_NONE;
sParam.u8cRxTriggerLevel= DRVUART_FIFO_1BYTES;
DrvUART_Open(UART_PORT0,&sParam);
}
void SystemClockInit(void)
{
UNLOCKREG();
DrvSYS_SetOscCtrl(E_SYS_XTL12M, ENABLE);
DrvSYS_Delay(5000);
DrvSYS_Open(50000000);
/* Enable PLL */
//DrvSYS_SetPLLMode(0);
/* Switch to PLL clock */
// DrvSYS_SelectHCLKSource(2);
/* Update system core clock */
//SystemCoreClockUpdate();
}
bool flash_io_driver_write(__ROM void* address, const void* data, uint16_t length)
{
if(is_range_valid(address) == false)
{
return false;
}
uint32_t _address = (uint32_t)address;
uint32_t* _data = (uint32_t*)data;
length /= sizeof(uint32_t); // number of bytes -> number of whole words
// write
for(uint16_t i = 0; i < length; i++)
{
UNLOCKREG();
if(FMC_Write(_address, *_data++) != E_FMC_OK)
{
LOCKREG();
return false;
}
LOCKREG();
_address += sizeof(uint32_t);
}
// verify
uint32_t* source = (uint32_t*)address;
_data = (uint32_t*)data;
for(uint16_t i = 0; i < length; i++)
{
uint32_t s = *source++;
uint32_t t = *_data++;
if(s != t)
{
return false;
}
}
return true;
}
//============================================================================
// DATA FLASH OPERATION
// u32addr : 0-1024 (For 4KBytes Data Flash)
// u32data : 0-0xFFFFFFFF (4Bytes)
//============================================================================
void DATA_FLASH_Write(uint32_t u32addr,uint32_t u32data)
{
uint32_t i=0;
#ifdef M451
SYS_UnlockReg();
FMC_Open();
for(i=0; i<PAGE_SIZE; i++)
data_buff[i] = FMC_Read(DATA_Flash_Start_ADD+i*4+ u32addr/PAGE_SIZE*2048);
FMC_Erase(DATA_Flash_Start_ADD+u32addr/PAGE_SIZE*2048);
data_buff[u32addr%PAGE_SIZE]=u32data;
for(i=0; i<PAGE_SIZE; i++)
FMC_Write(DATA_Flash_Start_ADD+i*4+ u32addr/PAGE_SIZE*2048, data_buff[i]);
FMC_Close();
SYS_LockReg();
#else
uint32_t data_buff[PAGE_SIZE];
__set_PRIMASK(1);//Avoid interrupt
UNLOCKREG();
DrvFMC_EnableISP();
for(i=0; i<PAGE_SIZE; i++)
DrvFMC_Read(DATA_Flash_Start_ADD+i*4+ u32addr/128*512, &data_buff[i]);
DrvFMC_Erase(DATA_Flash_Start_ADD+u32addr/128*512);
data_buff[u32addr%128]=u32data;
for(i=0; i<PAGE_SIZE; i++)
DrvFMC_Write(DATA_Flash_Start_ADD+i*4+ u32addr/128*512, data_buff[i]);
DrvFMC_DisableISP();
LOCKREG();
__set_PRIMASK(0);
#endif
}
/*20150515 added by michael*/
void Set_AD5259_Potential ( uint8_t word_addr, uint8_t data )
{
Tx_Data0[0] = word_addr;
Tx_Data0[1] = 2;
Tx_Data0[2] = data;
UNLOCKREG();
DrvI2C_InstallCallback(I2C_PORT0, I2CFUNC, I2C0_Callback_Tx);
DrvI2C_InstallCallback(I2C_PORT0, TIMEOUT, I2C0_Timeout);
DrvI2C_EnableTimeoutCount(I2C_PORT0, 1, 1);
/* I2C0 as master sends START signal */
start_I2C = 0;
EndFlag0 = 0;
Active_I2C_Slave_Addr = AD5259_I2C_Slave_Addr;
DrvI2C_Ctrl(I2C_PORT0, 1, 0, 0, 0);
while (EndFlag0 == 0);
DrvI2C_UninstallCallBack(I2C_PORT0, I2CFUNC);
DrvI2C_UninstallCallBack(I2C_PORT0, TIMEOUT);
DrvI2C_EnableTimeoutCount(I2C_PORT0, 0, 0);
LOCKREG();
}
void setupSystemClock()
{
#ifdef M451
SYS_UnlockReg();
/* Enable HIRC clock */
CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk);
/* Waiting for HIRC clock ready */
CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
/* Switch HCLK clock source to HIRC */
CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HIRC, CLK_CLKDIV0_HCLK(1));
/* Set core clock as PLL_CLOCK from PLL and SysTick source to HCLK/2*/
CLK_SetCoreClock(SYSTEM_CLOCK);
CLK_SetSysTickClockSrc(CLK_CLKSEL0_STCLKSEL_HCLK_DIV2);
SYS_LockReg();
#else
uint32_t u32PllCr;
uint16_t i;
UNLOCKREG();
DrvSYS_SetOscCtrl(E_SYS_OSC22M, 1);
while (DrvSYS_GetChipClockSourceStatus(E_SYS_OSC22M) != 1);
DrvSYS_SelectPLLSource(E_SYS_INTERNAL_22M);
u32PllCr = DrvSYS_GetPLLContent(E_SYS_INTERNAL_22M, SYSTEM_CLOCK);
/*Delay for 12M or 22M stable*/
for (i=0;i<10000;i++);
DrvSYS_SetPLLContent(u32PllCr);
SYSCLK->PLLCON.OE = 0;
SYSCLK->PLLCON.PD = 0;
/*Delay for PLL stable*/
for (i=0;i<10000;i++);
/* Change HCLK clock source to be PLL. */
DrvSYS_SelectHCLKSource(2);
LOCKREG(); // Lock the protected registers
#endif
}
/*---------------------------------------------------------------------------------------------------------*/
void DrvPMU_DeepPowerDown(uint32_t u32DPDWakeupMode, uint32_t u32TimerSel)
{
UNLOCKREG();
SCB->SCR = SCB_SCR_SLEEPDEEP;
SYSCLK->PWRCON.DEEP_PD = 1;
SYSCLK->PWRCON.STOP = 0;
SYSCLK->PWRCON.STANDBY_PD = 0;
SYSCLK->PWRCON.PIN_ENB= 0;
SYSCLK->PWRCON.OSC10K_ENB= 0;
SYSCLK->PWRCON.TIMER_SEL = u32TimerSel;
switch(u32DPDWakeupMode)
{
case DPDWAKEUPMODE_PINOSC10KWAKEUP:
break;
case DPDWAKEUPMODE_PINWAKEUP:
SYSCLK->PWRCON.OSC10K_ENB = 1; //Disable OSC10K Wakeup
break;
case DPDWAKEUPMODE_OSC10KWAKEUP:
SYSCLK->PWRCON.PIN_ENB = 1; //Disable PIN Wakeup
break;
case DPDWAKEUPMODE_ONLYPORWAKEUP:
SYSCLK->PWRCON.PIN_ENB = 1; //Disable PIN Wakeup
SYSCLK->PWRCON.OSC10K_ENB = 1; //Disable OSC10K Wakeup
break;
}
LOCKREG();
__wfi();
}
/*************************************************************************//**
* @brief Delay 1 second exactly with timer.
* @param None
* @return None
*****************************************************************************/
void Delay1Sec(void)
{
UNLOCKREG();
SYSCLK->PWRCON.XTL12M_EN = 1;
/* Waiting for 12M Xtal stable */
while (DrvSYS_GetChipClockSourceStatus(E_SYS_XTL12M) != 1);
/*Configure gpio p3.6 as OUTPUT for led*/
DrvGPIO_Open(E_PORT3, E_PIN6, E_IO_OUTPUT);
/* Example code */
DrvTIMER_Init();
DrvTIMER_Open(E_TMR0, 1000, E_PERIODIC_MODE);
DrvTIMER_EnableInt(E_TMR0);
DrvTIMER_Start(E_TMR0); /* Start counting */
while (1)
{
DrvGPIO_SetBit(E_PORT3, E_PIN6);
DrvTIMER_Delay(E_TMR0, 1000); /*Delay 1000/1000 Sec*/
DrvGPIO_ClrBit(E_PORT3, E_PIN6);
DrvTIMER_Delay(E_TMR0, 1000);
}
}
//*****************************************************************************
//
//! \brief Example of ACMP.
//!
//! \param None
//!
//! \return None
//
//*****************************************************************************
void SmplAcmp(void)
{
UNLOCKREG();
//
// P5.1 -> XTAL2, P5.0 -> XTAL1
//
GCR->P5_MFP = (GCR->P5_MFP & 0x00FFFCFC) | 0x03;
CLK->PWRCON_BITS.XTLCLK_EN = 1;
//
// Waiting for 12M Xtal stable
//
while (DrvSYS_GetChipClockSourceStatus(XTL_CLK) != 1);
DrvGPIO_InitFunction(FUNC_ACMP0);
DrvGPIO_InitFunction(FUNC_ACMP1);
//
// Enable ACMP clock source
//
CLK->APBCLK_BITS.ACMP_EN = 1;
//
// Configure ACMP0
//
ACMP->CR0 = 0x13;
//
// Configure ACMP1
//
ACMP->CR1 = 0x13;
NVIC_EnableIRQ(ACMP_IRQn);
}
void DataFlashRead(uint32_t addr, uint32_t size, uint32_t buffer)
{
/* This is low level read function of USB Mass Storage */
int32_t len;
/* Modify the address to MASS_STORAGE_OFFSET */
addr += MASS_STORAGE_OFFSET;
len = (int32_t)size;
UNLOCKREG();
//FMC_Init();
while(len >= FLASH_PAGE_SIZE)
{
FMC_ReadPage(addr, (uint32_t *)buffer);
addr += FLASH_PAGE_SIZE;
buffer += FLASH_PAGE_SIZE;
len -= FLASH_PAGE_SIZE;
}
//FMC_DeInit();
LOCKREG();
}
//*****************************************************************************
//
//! \brief GPIO test.
//!
//! \param None
//!
//! \return None
//
//*****************************************************************************
void GpioTest(void)
{
int32_t i32Err;
UNLOCKREG();
//
// Enable high external clock and use it as system clock (HCLK)
//
DrvSYS_Open(XTL_CLK);
//
// Waiting for 12M Xtal stable
//
while (DrvSYS_GetChipClockSourceStatus(XTL_CLK) != 1);
//
// Configure Bit0 in Port1 to Output pin and Bit4 in Port3 to Input
// pin then close it
//
DrvGPIO_Open(E_PORT1, E_PIN0, E_IO_OUTPUT);
DrvGPIO_Open(E_PORT3, E_PIN4, E_IO_INPUT);
i32Err = 0;
DrvGPIO_ClrBit(E_PORT1, E_PIN0);
if (DrvGPIO_GetBit(E_PORT3, E_PIN4) != 0)
{
i32Err = 1;
}
DrvGPIO_SetBit(E_PORT1, E_PIN0);
if (DrvGPIO_GetBit(E_PORT3, E_PIN4) != 1)
{
i32Err = 1;
}
DrvGPIO_Close(E_PORT1, E_PIN0);
DrvGPIO_Close(E_PORT3, E_PIN4);
//
// GPIO Interrupt Test:P15, P22, P32(INT0) and P52(INT1) are used to test
// interrupt and control LEDs(P30)
//
//
//Configure P30 for LED control
//
DrvGPIO_Open(E_PORT3, E_PIN0, E_IO_OUTPUT);
//
//Configure P15 as general GPIO interrupt
//
DrvGPIO_Open(E_PORT1, E_PIN5, E_IO_INPUT);
//
//The Quasi-bidirection mode could be used as input with pull up enable
//
DrvGPIO_Open(E_PORT2, E_PIN2, E_IO_QUASI);
//
// Configure general interrupt callback function for P0/P1 and P2/P3/P4
//
DrvGPIO_SetIntCallback(P0P1Callback, P2P3P4Callback, P5Callback);
DrvGPIO_EnableInt(E_PORT1, E_PIN5, E_IO_RISING, E_MODE_EDGE);
//
// IO_FALLING means low level trigger if it is in level trigger mode.
//
DrvGPIO_EnableInt(E_PORT2, E_PIN2, E_IO_FALLING, E_MODE_LEVEL);
DrvGPIO_SetDebounceTime(0, E_DBCLKSRC_HCLK);
DrvGPIO_EnableDebounce(E_PORT1, E_PIN5);
DrvGPIO_EnableDebounce(E_PORT2, E_PIN2);
DrvGPIO_EnableDebounce(E_PORT3, E_PIN2);
DrvGPIO_EnableDebounce(E_PORT5, E_PIN2);
//
// Configure external interrupt.
//
DrvGPIO_InitFunction(FUNC_EXTINT0);
DrvGPIO_InitFunction(FUNC_EXTINT1);
DrvGPIO_EnableEINT(E_EINT0_PIN, E_IO_FALLING, E_MODE_EDGE, EINT0Callback);
DrvGPIO_EnableEINT(E_EINT1_PIN, E_IO_BOTH_EDGE, E_MODE_EDGE, EINT1Callback);
}
/*---------------------------------------------------------------------------------------------------------*/
int32_t DrvOSC_TrimOscillator(int32_t i32Target, int32_t i32Index)
{
// Trim index [0,1] to target Hz [nominally 32,768,000 or 49,152,000]
uint8_t u8Coarse, u8Fine, maxFine, minFine;
int32_t i32Freq, i32LastFreq;
SYSCLK->APBCLK.ANA_EN = 1; /* Turn on analog peripheral clock */
// Osc Trim and Measurement test...
ANA->FREQ_CTRL.FM_SEL = 1; // Select reference source as 32kHz XTAL input
ANA->FREQ_CTRL.FM_GO = 0;
UNLOCKREG();
// Set HCLK divide to ensure oscillator does not violate access timing.
SYSCLK->CLKDIV.HCLK_N = DRVOSC_MEAS_HCLK_DIV-1;
// Select TRIM soruce
SYSCLK->CLKSEL0.OSCFSel = i32Index;
SYS->OSCTRIM[i32Index].RANGE = 0;
// Make sure slowest frequency is lower than target
u8Fine = DRVOSC_RESERVE_RANGE;
u8Coarse = 0;
SYS->OSCTRIM[i32Index].TRIM = u8Fine + u8Coarse*(DRVOSC_MAX_FINE+1);
i32Freq = DrvOSC_MeasureOsc(DRVOSC_MEAS_HCLK_DIV,DRVOSC_NUM_CYCLES);
if(i32Freq > i32Target)
SYS->OSCTRIM[i32Index].RANGE = 1;
// There are 32 (DRVOSC_MAX_FINE+1) fine settings and 8 coarse ranges.
// Find suitable coarse range, the range where measured frequency first exceeds target.
u8Fine = DRVOSC_MAX_FINE - DRVOSC_RESERVE_RANGE;
u8Coarse = 0;
do {
SYS->OSCTRIM[i32Index].TRIM = u8Fine + u8Coarse*(DRVOSC_MAX_FINE+1);
i32Freq = DrvOSC_MeasureOsc(DRVOSC_MEAS_HCLK_DIV,DRVOSC_NUM_CYCLES);
u8Coarse++;
} while((i32Freq < i32Target) && (u8Coarse <= DRVOSC_MAX_COARSE) );
u8Coarse--;
// At this point measured frequency should be greater than target and a valid coarse range
// selected. Check for error condition: coarse range overflow
if(i32Freq < i32Target)
return(E_DRVOSC_COARSE_OVF);
#ifdef BINARY_SEARCH
//Now trim to this range using binary search.
maxFine = DRVOSC_MAX_FINE-DRVOSC_RESERVE_RANGE;
minFine = DRVOSC_RESERVE_RANGE;
do {
i32LastFreq = i32Freq; //Store last frequency
u8Fine = ((maxFine+minFine)/2);
SYS->OSCTRIM[i32Index].TRIM = u8Fine + u8Coarse*32;
i32Freq = DrvOSC_MeasureOsc(DRVOSC_MEAS_HCLK_DIV,DRVOSC_NUM_CYCLES);
if (i32Freq < i32Target) { //Check if Freq is greter or less than target, move max and mins accordingly
minFine = u8Fine;
}
else {
maxFine = u8Fine;
}
} while ((maxFine-minFine != 1) && (u8Fine <= DRVOSC_MAX_FINE));
if (i32Freq <= i32Target) {
u8Fine++;
i32LastFreq = i32Freq;
SYS->OSCTRIM[i32Index].TRIM = u8Fine + u8Coarse*32;
i32Freq = DrvOSC_MeasureOsc(DRVOSC_MEAS_HCLK_DIV,DRVOSC_NUM_CYCLES);
}
i32LastFreq = i32Freq;
SYS->OSCTRIM[i32Index].TRIM = u8Fine + u8Coarse*32;
i32Freq = DrvOSC_MeasureOsc(DRVOSC_MEAS_HCLK_DIV,DRVOSC_NUM_CYCLES);
// At this point measured frequency should be greater than target and a valid fine range
// selected. Check for error condition: fine range overflow
if(i32Freq < i32Target)
return(E_DRVOSC_FINE_OVF);
// See which trim has best error.
if(DrvOSC_Absolute(i32Target-i32LastFreq) < DrvOSC_Absolute(i32Freq-i32Target)) {
// LastFreq was closer, decrement fine trim.
u8Fine--;
i32Freq = i32LastFreq;
}
// Set final trim and return clock divider to unity.
SYS->OSCTRIM[i32Index].TRIM = u8Fine + u8Coarse*(DRVOSC_MAX_FINE+1);
SYSCLK->CLKDIV.HCLK_N = 0;
return(i32Freq);
#else
// Now trim to this range. Could do a binary search later, for now linear search.
u8Fine = DRVOSC_RESERVE_RANGE;
i32Freq = 0;
do {
i32LastFreq = i32Freq; // Store last frequency
SYS->OSCTRIM[i32Index].TRIM = u8Fine + u8Coarse*(DRVOSC_MAX_FINE+1);
i32Freq = DrvOSC_MeasureOsc(DRVOSC_MEAS_HCLK_DIV,DRVOSC_NUM_CYCLES);
u8Fine++;
} while((i32Freq < i32Target) && (u8Fine <= DRVOSC_MAX_FINE));
u8Fine--;
// At this point measured frequency should be greater than target and a valid fine range
// selected. Check for error condition: fine range overflow
if(i32Freq < i32Target)
return(E_DRVOSC_FINE_OVF);
// See which trim has best error.
if(DrvOSC_Absolute(i32Target-i32LastFreq) < DrvOSC_Absolute(i32Freq-i32Target)) {
// LastFreq was closer, decrement fine trim.
u8Fine--;
i32Freq = i32LastFreq;
}
// Set final trim and return clock divider to unity.
SYS->OSCTRIM[i32Index].TRIM = u8Fine + u8Coarse*(DRVOSC_MAX_FINE+1);
SYSCLK->CLKDIV.HCLK_N = 0;
return(i32Freq);
#endif
}
/**
* @brief Main funcion
* @param None
* @retval 0: Success; <0: Failed
*/
int32_t main (void)
{
int32_t i32Err;
uint32_t u32Data, i, u32ImageSize, j, *pu32Loader;
uint8_t ch;
UNLOCKREG();
/* Enable FMC ISP function */
FMC_Init();
/* Read Company ID */
u32Data = 0;
FMC_ReadCID(&u32Data);
if (u32Data != 0xda)
{
printf("Wrong CID: 0x%x\n", u32Data);
goto lexit;
}
/* Check the signature to check if Simple LD code is finished or not */
if (inpw(KEY_ADDR) == SIGNATURE)
{
/* Just clear SIGNATURE and finish the sample code if Simple LD code has been executed. */
outpw(KEY_ADDR, 0);
/* Read BS */
printf(" Boot Mode .................................. ");
if (FMC_GetBootSelect() == E_FMC_APROM)
printf("[APROM]\n");
else
{
printf("[LDROM]\n");
printf(" WARNING: The driver sample code must execute in AP mode!\n");
}
goto lexit;
}
printf("\n\n");
printf("+-------------------------------------------------------------------------+\n");
printf("| NANO1xx Flash Memory Controller Driver Sample Code |\n");
printf("+-------------------------------------------------------------------------+\n");
printf(" NOTE: This sample must be applied to NANO1xx series equipped with 16KB RAM.\n");
/* Read BS */
printf(" Boot Mode .................................. ");
if (FMC_GetBootSelect() == E_FMC_APROM)
printf("[APROM]\n");
else
{
printf("[LDROM]\n");
printf(" WARNING: The driver sample code must execute in AP mode!\n");
goto lexit;
}
/* Read Data Flash base address */
u32Data = FMC_ReadDataFlashBaseAddr();
printf(" Data Flash Base Address .................... [0x%08x]\n", u32Data);
/* Check the data in LD ROM to avoid overwrite them */
FMC_Read(LDROM_BASE, &u32Data);
if (u32Data != 0xFFFFFFFF)
{
printf("\n WARNING: There is code in LD ROM.\n If you proceed, the code in LD ROM will be corrupted.\n");
printf(" Continue? [y/n]:");
ch = getchar();
putchar(ch);
if (ch != 'y')
goto lexit;
printf("\n\n");
}
/* Enable LDROM update */
FMC_EnableLDUpdate();
printf(" Erase LD ROM ............................... ");
/* Page Erase LDROM */
for (i = 0; i < 4096; i += PAGE_SIZE)
FMC_Erase(LDROM_BASE + i);
/* Erase Verify */
i32Err = 0;
for (i = LDROM_BASE; i < (LDROM_BASE+4096); i += 4)
{
FMC_Read(i, &u32Data);
if(u32Data != 0xFFFFFFFF)
{
printf(" u32Data = 0x%x\n", u32Data);
i32Err = 1;
}
}
if (i32Err)
printf("[FAIL]\n");
else
printf("[OK]\n");
printf(" Program LD ROM test ........................ ");
/* Program LD ROM and read out data to compare it */
for (i = LDROM_BASE; i < (LDROM_BASE+4096); i += 4)
{
FMC_Write(i, i);
}
i32Err = 0;
for (i = LDROM_BASE; i < (LDROM_BASE+4096); i += 4)
{
FMC_Read(i, &u32Data);
if(u32Data != i)
{
i32Err = 1;
}
}
if (i32Err)
printf("[FAIL]\n");
else
printf("[OK]\n");
/* Check LD image size */
u32ImageSize = (uint32_t)&loaderImageLimit - (uint32_t)&loaderImageBase;
if (u32ImageSize == 0)
{
printf(" ERROR: Loader Image is 0 bytes!\n");
goto lexit;
}
if (u32ImageSize > 4096)
{
printf(" ERROR: Loader Image is larger than 4KBytes!\n");
goto lexit;
}
printf(" Program Simple LD Code ..................... ");
pu32Loader = (uint32_t *)&loaderImageBase;
for (i = 0; i < u32ImageSize; i += PAGE_SIZE)
{
FMC_Erase(LDROM_BASE + i);
for (j = 0; j < PAGE_SIZE; j += 4)
{
FMC_Write(LDROM_BASE + i + j, pu32Loader[(i + j) / 4]);
}
}
/* Verify loader */
i32Err = 0;
for (i = 0; i < u32ImageSize; i += PAGE_SIZE)
{
for(j = 0; j < PAGE_SIZE; j += 4)
{
FMC_Read(LDROM_BASE + i + j, &u32Data);
if (u32Data != pu32Loader[(i+j)/4])
i32Err = 1;
if (i + j >= u32ImageSize)
break;
}
}
if(i32Err)
{
printf("[FAIL]\n");
}
else
{
printf("[OK]\n");
/* Reset CPU to boot to LD mode */
printf("\n >>> Reset to LD mode <<<\n");
FMC_BootSelect(E_FMC_LDROM);
GCR->IPRST_CTL1 = GCR_IPRSTCTL1_CPU;
}
lexit:
/* Disable FMC ISP function */
FMC_DeInit();
/* Lock protected registers */
LOCKREG();
printf("\nFMC Sample Code Completed.\n");
}
/******************************************************************************//**
*@brief A simple FMC example. It Erase the LDROM and Verify ,then Program LDROM
* and read out data to compare.
*@param None
*@return None
**********************************************************************************/
void FMC_LDROM(void)
{
uint32_t u32Data, i;
int32_t i32Err;
// STR_UART_T sParam;
/* Unlock the protected registers */
UNLOCKREG();
/* Enable the 12MHz oscillator oscillation */
SYSCLK->PWRCON.XTL12M_EN = 1;
/* Waiting for 12M Xtal stable */
while (DrvSYS_GetChipClockSourceStatus(E_SYS_XTL12M) != 1);
/* Set UART Pin */
DrvGPIO_InitFunction(E_FUNC_UART0);
/* UART Setting */
/* sParam.u32BaudRate = 115200;
sParam.u8cDataBits = DRVUART_DATABITS_8;
sParam.u8cStopBits = DRVUART_STOPBITS_1;
sParam.u8cParity = DRVUART_PARITY_NONE;
sParam.u8cRxTriggerLevel= DRVUART_FIFO_1BYTES;
*/
/* Select UART Clock Source From 12MHz */
DrvSYS_SelectIPClockSource(E_SYS_UART_CLKSRC, 0);
/* Set UART Configuration */
// DrvUART_Open(UART_PORT0, &sParam);
/* Enable ISP function */
DrvFMC_EnableISP();
/* Enable LDROM update */
DrvFMC_EnableLDUpdate();
/* Page Erase LDROM */
printf("Erase LDROM test...............................");
for(i=0; i<4096; i+=PAGE_SIZE)
DrvFMC_Erase(LDROM_BASE + i);
/* Erase Verify */
i32Err = 0;
for(i = LDROM_BASE; i < (LDROM_BASE+4096); i += 4)
{
DrvFMC_Read(i, &u32Data);
if(u32Data != 0xFFFFFFFF)
{
i32Err = 1;
}
}
if (i32Err)
printf("[FAIL]\n\r");
else
printf("[OK]\n\r");
/* Program LD ROM and read out data to compare */
printf("Program LDROM test.............................");
for(i = LDROM_BASE; i < (LDROM_BASE+4096); i += 4)
{
DrvFMC_Write(i, i);
}
i32Err = 0;
for(i = LDROM_BASE; i < (LDROM_BASE+4096); i += 4)
{
DrvFMC_Read(i, &u32Data);
if(u32Data != i)
{
i32Err = 1;
}
}
if (i32Err)
printf("[FAIL]\n\r");
else
printf("[OK]\n\r");
/* Disable ISP function */
DrvFMC_DisableISP();
/* Lock protected registers */
LOCKREG();
printf("FMC Sample Code Completed!\n\r");
}
int main(void)
{
uint8_t buffer[32] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16};
/* Unlock the protected registers */
UNLOCKREG();
/* Enable the 12MHz oscillator oscillation */
DrvSYS_SetOscCtrl(E_SYS_XTL12M, 1);
/* Waiting for 12MHz Xtal stable */
DrvSYS_Delay(5000);
/* HCLK clock source. 0: external 12MHz. */
DrvSYS_SelectHCLKSource(0);
LOCKREG();
DrvSYS_SetClockDivider(E_SYS_HCLK_DIV, 0); /* HCLK clock frequency = HCLK clock source / (HCLK_N + 1) */
nrf_init();
nrf_detect();
//nrf_rx_mode_no_aa(addr,5,16,40);
//nrf_rx_mode(addr,5,16,40);
nrf_rx_mode_dual(addr,5,40);
nrf_test_reg();
DrvGPIO_Open(E_GPA, 2, E_IO_OUTPUT);
DrvGPIO_Open(E_GPA, 3, E_IO_OUTPUT);
DrvGPIO_Open(E_GPA, 4, E_IO_OUTPUT);
DrvGPIO_Open(E_GPA, 5, E_IO_OUTPUT);
{
uint8_t status = nrf_read_reg(NRF_STATUS);
nrf_write_reg(NRF_WRITE_REG|NRF_STATUS,status); // clear IRQ flags
nrf_write_reg(NRF_FLUSH_RX, 0xff);
nrf_write_reg(NRF_FLUSH_TX, 0xff);
}
while(1) {
uint8_t buffer[32];
if(tx_done) {
static uint8_t yy = 0;
yy++;
if(yy&1) {
DrvGPIO_SetBit(E_GPA,2);
} else {
DrvGPIO_ClrBit(E_GPA,2);
}
if(tx_done == 1) {
} else {
}
buffer[0] = tx_done;
tx_done = 0;
}
if(rx_done) {
static uint8_t xx = 0;
rx_done = 0;
xx++;
if(xx & 1)
DrvGPIO_SetBit(E_GPA,5);
else
DrvGPIO_ClrBit(E_GPA,5);
//nrf_ack_packet(0,buffer, (xx&15) + 1);
nrf_ack_packet(0,rx_buffer, rx_len);
}
}
while(1) {
static uint8_t cnt = 0;
if(cnt&1) {
DrvGPIO_SetBit(E_GPA,2);
} else {
DrvGPIO_ClrBit(E_GPA,2);
}
DrvSYS_Delay(50000*2);
cnt++;
//nrf_tx_packet(buffer, 16);
//buffer[0]++;
if(nrf_rx_packet(buffer,16) == NRF_RX_OK)
{
static uint8_t xx = 0;
xx++;
if(xx & 1)
DrvGPIO_SetBit(E_GPA,5);
else
DrvGPIO_ClrBit(E_GPA,5);
}
}
return 0;
}
/*----------------------------------------------------------------------------*/
int main (void)
{
uint8_t item;
UNLOCKREG();
SYS_Init();
UART0_Init();
/* Set GPD14 to control CAN transceiver for Nuvoton board */
PD14 = 0;
/* Select CAN Multi-Function */
CAN_Init();
Note_Configure();
SelectCANSpeed();
do
{
TestItem();
item = GetChar();
printf("\n");
switch (item)
{
case '0':
{
printf("[0] Transmit a message by basic mode\n\n");
printf("Please confirm receiver is ready.\n");
printf("Press any key to continue ...\n\n");
GetChar();
Test_BasicMode_Tx();
break;
}
case '1':
{
printf("[1] Receive a message by basic mode\n\n");
Test_BasicMode_Rx();
break;
}
case '2':
{
printf("[2] Transmit a message by normal mode\n\n");
printf("Please confirm receiver is ready.\n");
printf("Press any key to continue ...\n\n");
GetChar();
Test_NormalMode_Tx();
break;
}
case '3':
{
printf("[3] Receive a message by normal mode\n\n");
Test_NormalMode_Rx();
break;
}
case '4':
{
printf("[4] Test Mask Filter\n\n");
printf("Please confirm [Set Mask Filter] of receiver is selected.\n");
printf("Press any key to continue ...\n\n");
GetChar();
Test_TestMaskFilter();
break;
}
case '5':
{
printf("[5] Set Mask Filter\n\n");
Test_SetMaskFilter();
break;
}
default:
{
printf("Unknown command!\n\n");
}
}
}while(item != 27);
CAN_Close();
}
void DataFlashWrite(uint32_t addr, uint32_t size, uint32_t buffer)
{
/* This is low level write function of USB Mass Storage */
int32_t len, i, offset;
uint32_t *pu32;
uint32_t alignAddr;
/* Modify the address to MASS_STORAGE_OFFSET */
addr += MASS_STORAGE_OFFSET;
len = (int32_t)size;
UNLOCKREG();
//FMC_Init();
if ( len == FLASH_PAGE_SIZE && ((addr & (FLASH_PAGE_SIZE-1)) == 0) )
{
FMC_Erase(addr);
while (len >= FLASH_PAGE_SIZE)
{
FMC_ProgramPage(addr, (uint32_t *) buffer);
len -= FLASH_PAGE_SIZE;
buffer += FLASH_PAGE_SIZE;
addr += FLASH_PAGE_SIZE;
}
}
else
{
do
{
alignAddr = addr & 0x1FE00;
/* Get the sector offset*/
offset = ( addr & (FLASH_PAGE_SIZE-1) );
if ( offset || (size < FLASH_PAGE_SIZE) )
{
/* Non 4k alignment. Note: It needs to avoid add MASS_STORAGE_OFFSET twice. */
DataFlashRead(alignAddr - MASS_STORAGE_OFFSET, FLASH_PAGE_SIZE, (uint32_t)&g_sectorBuf[0]);
}
/* Update the data */
pu32 = (uint32_t *)buffer;
len = FLASH_PAGE_SIZE - offset;
if (size < len)
len = size;
for (i=0; i<len/4; i++)
{
g_sectorBuf[offset/4 + i] = pu32[i];
}
FMC_Erase(alignAddr);
for(i=0; i<16; i++)
{
FMC_ProgramPage(alignAddr + (i << 8), (uint32_t *) g_sectorBuf + (i << 8));
}
size -= len;
addr += len;
buffer += len;
} while (size > 0);
}
//FMC_DeInit();
LOCKREG();
}
void SystemInit (void)
{
// set init port pin values and types for LDG34+ HW
PORT0->DOUT = 0;
PORT1->DOUT = 0;
PORT2->DOUT = 0;
PORT3->DOUT = BIT5 + BIT4 + BIT1; // inputs and TXD remain high
PORT3->DMASK = BIT7; // reserved for debugging
// open pins are set to QBM to keep them fixed
// PORT0 7:OUT 6:QBM 5:OUT 4:OUT 3:QBM 2:QBM 1:OUT 0:OUT
outpw(&PORT0->PMD, (1<<14)+(3<<12)+(1<<10)+(1<<8)+(3<<6)+(3<<4)+(1<<2)+ 1);
// PORT1 7:QBM 6:QBM 5:IN 4:IN 3:OUT 2:OUT 1:QBM 0:IN
outpw(&PORT1->PMD, (3<<14)+(3<<12)+(0<<10)+(0<<8)+(1<<6)+(1<<4)+(3<<2)+ 0);
// PORT2 7:QBM 6:OUT 5:OUT 4:OUT 3:OUT 2:OUT 1:QBM 0:QBM
outpw(&PORT2->PMD, (3<<14)+(1<<12)+(1<<10)+(1<<8)+(1<<6)+(1<<4)+(3<<2)+ 3);
// PORT3 7:QBM 6:OUT 5:QBM 4:QBM 3:QBM 2:IN 1:QBM 0:QBM
outpw(&PORT3->PMD, (3<<14)+(1<<12)+(3<<10)+(3<<8)+(3<<6)+(0<<4)+(3<<2)+ 3);
/* Unlock proctected registers */
UNLOCKREG();
/* Enable external 12M Crystal */
SYSCLK->PWRCON.XTL12M_EN = 1;
/* Wait until 12M clock is stable. */
while(SYSCLK->CLKSTATUS.XTL12M_STB == 0);
/* switch PLL to fast CPU clock */
outpw(&SYSCLK->PLLCON, (0xC1FE + CPUFREQ));
/* Wait for PLL stable */
while (SYSCLK->CLKSTATUS.PLL_STB == 0);
/* Change HCLK clock source to be PLL. */
SYSCLK->CLKSEL0.HCLK_S = 2;
/* Lock procteted registers */
LOCKREG();
/* enable required clock lines and select 12M clock */
SYSCLK->u32APBCLK = 0xFFFFFFFF;
SYSCLK->u32CLKSEL1 = 0;
SYSCLK->u32CLKSEL2 = 0;
/* initialise configuration data from DataFlah */
Init_CV_area();
/* Select timer0 Operation mode as period mode */
TIMER0->TCSR.MODE = 1;
/* Select Time out period = (Period of timer clock input) * (8-bit Prescale + 1) * (24-bit TCMP)*/
TIMER0->TCSR.PRESCALE = 12-1; // steps of 1 us
TIMER0->TCMPR = 8; // Set TCMPR [0~16777215]
/* Enable timer0 interrupt */
TIMER0->TCSR.IE = 1;
NVIC->ISER[0] = BIT8;
/* Enable Timer0 */
TIMER0->TCSR.CEN = 1;
// set type, alt, mfp for all pins
outpw(&SYS->P0_MFP, 0);
outpw(&SYS->P1_MFP, 0x001 + (0x001<<4) + (0x001<<5)); // analog inputs
outpw(&SYS->P2_MFP, (0x100<<2) + (0x100<<6)); // PWM
outpw(&SYS->P3_MFP, 0xFF0000 + (0x001<<1) + (0x001<<2)); // TXD and INT0, Schmitt Trigger
// outpw(&SYS->P4_MFP, BIT7 + BIT6); // Emulator seem automatically be detected ?
/* int HW for feedback */
InitFeedback();
/* select usable ADC input channels, chan 7 for temperature */
SYS->TEMPCR = 1; // enable temperature sensor
ADC->u32ADCHER = 0x200 + BIT7 + BIT5 + BIT4 + BIT0;
/* set ADC mode and start it */
ADC->u32ADCR = 0xD;
ADC->ADCR.ADST = 1;
// enable rail signal detection via INT0
Init_Rail_detect();
}
