//! Checks Target Vdd - Updates Target Vdd LED & status
//!
//! Updates \ref cable_status
//!
uint8_t bdm_checkTargetVdd(void) {
#if (HW_CAPABILITY&CAP_VDDSENSE)
if (bdm_targetVddMeasure() > VDD_2v) {
redLedOn();
if (bdm_option.targetVdd == BDM_TARGET_VDD_OFF)
cable_status.power = BDM_TARGET_VDD_EXT;
else
cable_status.power = BDM_TARGET_VDD_INT;
}
else {
redLedOff();
if (bdm_option.targetVdd == BDM_TARGET_VDD_OFF)
cable_status.power = BDM_TARGET_VDD_NONE;
else {
// Possible overload
cable_status.power = BDM_TARGET_VDD_ERR;
VDD_OFF();
}
}
#else
// No target Vdd sensing - assume external Vdd is present
cable_status.power = BDM_TARGET_VDD_EXT;
#endif // CAP_VDDSENSE
if ((cable_status.power == BDM_TARGET_VDD_NONE) ||
(cable_status.power == BDM_TARGET_VDD_ERR))
return BDM_RC_VDD_NOT_PRESENT;
return BDM_RC_OK;
}
//! Cycle power OFF to target
//!
//! @return
//! \ref BDM_RC_OK => No error \n
//! \ref BDM_RC_VDD_WRONG_MODE => Target Vdd not controlled by BDM interface \n
//! \ref BDM_RC_VDD_NOT_REMOVED => Target Vdd failed to fall \n
//!
uint8_t bdm_cycleTargetVddOff(void) {
uint8_t rc = BDM_RC_OK;
#if (HW_CAPABILITY&CAP_VDDCONTROL)
(void)bdm_checkTargetVdd();
if (bdm_option.targetVdd == BDM_TARGET_VDD_OFF)
return BDM_RC_VDD_WRONG_MODE;
#if (HW_CAPABILITY&CAP_CFVx_HW)
if (cable_status.target_type == T_CFVx)
bdmcf_interfaceIdle(); // Make sure BDM interface is idle
else
#endif
{
#if (HW_CAPABILITY&CAP_BDM)
bdmHCS_interfaceIdle(); // Make sure BDM interface is idle
#endif
}
#if (DEBUG&CYCLE_DEBUG)
DEBUG_PIN = 0;
DEBUG_PIN = 1;
#endif
// Power off & wait for Vdd to fall to ~5%
VDD_OFF();
WAIT_WITH_TIMEOUT_S( 5 /* s */, (bdm_targetVddMeasure()<10) );
#if (DEBUG&CYCLE_DEBUG)
DEBUG_PIN = 1;
DEBUG_PIN = 0;
#endif
if (bdm_targetVddMeasure()>=15) // Vdd didn't turn off!
rc = BDM_RC_VDD_NOT_REMOVED;
#if (DEBUG&CYCLE_DEBUG)
DEBUG_PIN = 0;
DEBUG_PIN = 1;
#endif
(void)bdm_checkTargetVdd(); // Update Target Vdd LED
// Wait a while with power off
WAIT_US(RESET_SETTLEms);
// Clear Vdd monitoring interrupt
#if (HW_CAPABILITY&CAP_VDDSENSE)
CLEAR_VDD_SENSE_FLAG(); // Clear Vdd monitoring flag
#endif
(void)bdm_checkTargetVdd(); // Update Target Vdd LED
#endif // CAP_VDDCONTROL
return(rc);
}
//! Turns on Target Vdd if enabled.
//!
//! @return
//! \ref BDM_RC_OK => Target Vdd confirmed on target \n
//! \ref BDM_RC_VDD_NOT_PRESENT => Target Vdd not present
//!
uint8_t bdm_setTargetVdd( void ) {
uint8_t rc = BDM_RC_OK;
#if (HW_CAPABILITY&CAP_VDDSENSE)
DISABLE_VDD_SENSE_INT();
#endif
switch (bdm_option.targetVdd) {
case BDM_TARGET_VDD_OFF :
VDD_OFF();
// Check for externally supplied target Vdd (> 2 V)
WAIT_US(VDD_RISE_TIMEus); // Wait for Vdd to rise & stabilise
if (bdm_targetVddMeasure()<VDD_2v)
rc = BDM_RC_VDD_NOT_PRESENT;
break;
case BDM_TARGET_VDD_3V3 :
VDD3_ON();
// Wait for Vdd to rise to 90% of 3V
WAIT_WITH_TIMEOUT_MS( 100 /* ms */, (bdm_targetVddMeasure()>VDD_3v3));
WAIT_US(VDD_RISE_TIMEus); // Wait for Vdd to rise & stabilise
if (bdm_targetVddMeasure()<VDD_3v3) {
VDD_OFF(); // In case of Vdd overload
rc = BDM_RC_VDD_NOT_PRESENT;
}
break;
case BDM_TARGET_VDD_5V :
VDD5_ON();
// Wait for Vdd to rise to 90% of 5V
WAIT_WITH_TIMEOUT_MS( 100 /* ms */, (bdm_targetVddMeasure()>VDD_5v));
WAIT_US(VDD_RISE_TIMEus); // Wait for Vdd to rise & stabilise
if (bdm_targetVddMeasure()<VDD_5v) {
VDD_OFF(); // In case of Vdd overload
rc = BDM_RC_VDD_NOT_PRESENT;
}
break;
}
#if (HW_CAPABILITY&CAP_VDDSENSE)
CLEAR_VDD_SENSE_FLAG(); // Clear Vdd Change Event
ENABLE_VDD_SENSE_INT();
#endif
(void)bdm_checkTargetVdd(); // Update Target Vdd LED & status
return (rc);
}
//! Once off initialisation
//!
void bdm_init(void) {
// Turn off important things
#if (HW_CAPABILITY&CAP_FLASH)
(void)bdmSetVpp(BDM_TARGET_VPP_OFF);
#endif
VDD_OFF();
(void)bdm_clearStatus();
// Update power status
(void)bdm_checkTargetVdd();
}
/*! \brief Initialise the system.
*
* Initialisation of the following:
* \li Watchdog (off),
* \li Stack,
* \li BDM interface,
* \li USB interface.
*/
void init(void) {
/* disable part reset on USB reset, enable STOP instruction & disable COP */
CONFIG = CONFIG_URSTD_MASK | CONFIG_STOP_MASK | CONFIG_COPD_MASK;
// Turn off important things
VPP_OFF();
VDD_OFF();
FLASH12V_OFF();
clearStack();
// Make unused pins 'safe' (not floating)
// These settings may be overridden later
POCR = POCR_PAP_MASK|POCR_PCP_MASK|POCR_PTE20P_MASK;
/* acknowledge IRQ interrupt and disable it */
ISCR = ISCR_ACK_MASK | ISCR_IMASK_MASK;
(void)bdm_init(); // Do early as possible
usb_init();
EnableInterrupts;
}
//! Interrupt function servicing the IC interrupt from Vdd changes
//! This routine has several purposes:
//! - Triggers POR into Debug mode on RS08/HCS08/CFV1 targets\n
//! - Turns off Target power on overload\n
//! - Updates Target power status\n
//!
void bdm_targetVddSense(void) {
#if (HW_CAPABILITY&CAP_VDDSENSE)
CLEAR_VDD_SENSE_FLAG(); // Clear Vdd Change Event
if (VDD_SENSE) { // Vdd rising
// Needs to be done on non-interrupt thread?
switch (cable_status.target_type) {
#if (HW_CAPABILITY&CAP_BDM)
case T_HC12:
case T_HCS08:
case T_RS08:
case T_CFV1:
(void)bdmHCS_powerOnReset();
break;
#endif
#if (HW_CAPABILITY&CAP_CFVx_HW)
case T_CFVx:
(void)bdmCF_powerOnReset();
break;
#endif
case T_JTAG:
case T_EZFLASH:
case T_MC56F80xx:
case T_ARM_JTAG:
case T_OFF:
default:
break;
}
}
else { // Vdd falling
VDD_OFF(); // Turn off Vdd in case it's an overload
}
// Update power status
(void)bdm_checkTargetVdd();
#endif // CAP_VDDSENSE
}
//! Sets the BDM interface to a suspended state
//!
//! - All signals idle \n
//! - All voltages off.
//!
void bdmCF_suspend(void) {
VDD_OFF();
bdmcf_interfaceIdle();
}
//! Turns off the BDM interface
//!
//! Depending upon settings, may leave target power on.
//!
void bdm_off( void ) {
bdm_interfaceOff();
if (!bdm_option.leaveTargetPowered) {
VDD_OFF();
}
}
/*! \brief Detect In-Circuit Programming (ICP) mode.
*
* This routine is called DIRECTLY from the ICP boot code - minimal C setup (stack only)!
*
* @return 0 => ICP not required, \n
* 1 => ICP required
*/
U8 userDetectICP(void) {
VDD_OFF(); // Turn off Vdd as early as possible
return 0; // ICP not required (rely on bootstrap in ICP code)
}
/*! \brief Initialise the system.
*
* Initialisation of the following:
* \li Default port values
* \li Watchdog (off),
* \li Stack,
* \li BDM interface,
* \li USB interface.
* \li Configure Clock for 48MHz operation
*/
static void init(void) {
// Default ports to inputs
PTADD = 0x00;
PTBDD = 0x00;
#if (CPU==JMxx)
PTCDD = 0x00;
PTDDD = 0x00;
PTEDD = 0x00;
PTFDD = 0x00;
PTGDD = 0x00;
#endif
// Turn off important things
#if ((HW_CAPABILITY & CAP_FLASH) != 0)
(void)bdmSetVpp(BDM_TARGET_VPP_OFF);
#endif
VDD_OFF();
// Default to Ports have PUPs
// Note - this doesn't affect outputs
PTAPE = 0xFF;
PTBPE = 0xFF;
#if (CPU==JMxx)
PTCPE = 0xFF;
PTDPE = 0xFF;
PTEPE = 0xFF;
PTFPE = 0xFF;
PTGPE = 0xFF;
#endif
EnableInterrupts;
#ifndef SOPT1_BKGDPE_MASK
#define SOPT1_BKGDPE_MASK (0)
#endif
SOPT1 = SOPT1_STOPE_MASK|SOPT1_BKGDPE_MASK; // Disable COP, enable STOP instr. & BKGD pin
#if (HW_CAPABILITY&CAP_VDDSENSE)
SPMSC1_BGBE = 1; // Enable Bandgap Reference
#endif
LED_INIT();
clearStack();
initUSB(); // Assumes clock already done
(void)bdm_init();
(void)bdm_off();
#ifdef VDD_ON_INITIALLY
// For compatibility with original board s/w
// The board is powered when initially plugged in
#if (VDD_ON_INITIALLY == 3)
bdm_option.targetVdd = BDM_TARGET_VDD_3V3;
#elif (VDD_ON_INITIALLY == 5)
bdm_option.targetVdd = BDM_TARGET_VDD_5;
#else
#error "Illegal VDD_ON_INITIALLY value"
#endif
(void)bdm_interfaceOff();
(void)bdm_setTargetVdd();
#endif
#if (DEBUG&SCI_DEBUG) != 0)
debugSCIInit();
#endif
}
