void vidc_sm_set_pand_b_frame_qp(struct ddl_buf_addr *shared_mem,
u32 b_frame_qp, u32 p_frame_qp)
{
u32 nP_B_frame_qp;
nP_B_frame_qp = VIDC_SETFIELD(b_frame_qp,
VIDC_SM_P_B_FRAME_QP_B_FRAME_QP_SHFT,
VIDC_SM_P_B_FRAME_QP_B_FRAME_QP_BMASK);
nP_B_frame_qp |= VIDC_SETFIELD(p_frame_qp,
VIDC_SM_P_B_FRAME_QP_P_FRAME_QP_SHFT,
VIDC_SM_P_B_FRAME_QP_P_FRAME_QP_BMASK);
DDL_MEM_WRITE_32(shared_mem , VIDC_SM_P_B_FRAME_QP_ADDR,
nP_B_frame_qp);
}
void vidc_sm_set_metadata_enable(struct ddl_buf_addr *shared_mem,
u32 extradata_enable, u32 qp_enable, u32 concealed_mb_enable,
u32 vc1Param_enable, u32 sei_nal_enable, u32 vui_enable,
u32 enc_slice_size_enable, u32 mp2_data_dump_enable)
{
u32 metadata_enable;
metadata_enable = VIDC_SETFIELD((mp2_data_dump_enable) ? 1 : 0,
VIDC_SM_METADATA_ENABLE_MP2_DATADUMP_SHFT,
VIDC_SM_METADATA_ENABLE_MP2_DATADUMP_BMSK) |
VIDC_SETFIELD((extradata_enable) ? 1 : 0,
VIDC_SM_METADATA_ENABLE_EXTRADATA_SHFT,
VIDC_SM_METADATA_ENABLE_EXTRADATA_BMSK) |
VIDC_SETFIELD((enc_slice_size_enable) ? 1 : 0,
VIDC_SM_METADATA_ENABLE_ENC_SLICE_SIZE_SHFT,
VIDC_SM_METADATA_ENABLE_ENC_SLICE_SIZE_BMSK) |
VIDC_SETFIELD((vui_enable) ? 1 : 0,
VIDC_SM_METADATA_ENABLE_VUI_SHFT,
VIDC_SM_METADATA_ENABLE_VUI_BMSK) |
VIDC_SETFIELD((sei_nal_enable) ? 1 : 0,
VIDC_SM_METADATA_ENABLE_SEI_VIDC_SHFT,
VIDC_SM_METADATA_ENABLE_SEI_VIDC_BMSK) |
VIDC_SETFIELD((vc1Param_enable) ? 1 : 0,
VIDC_SM_METADATA_ENABLE_VC1_PARAM_SHFT,
VIDC_SM_METADATA_ENABLE_VC1_PARAM_BMSK) |
VIDC_SETFIELD((concealed_mb_enable) ? 1 : 0,
VIDC_SM_METADATA_ENABLE_CONCEALED_MB_SHFT,
VIDC_SM_METADATA_ENABLE_CONCEALED_MB_BMSK) |
VIDC_SETFIELD((qp_enable) ? 1 : 0,
VIDC_SM_METADATA_ENABLE_QP_SHFT,
VIDC_SM_METADATA_ENABLE_QP_BMSK);
DDL_MEM_WRITE_32(shared_mem, VIDC_SM_METADATA_ENABLE_ADDR,
metadata_enable);
}
void vidc_sm_set_i_frame_qp(struct ddl_buf_addr *shared_mem,
u32 nMaxQP, u32 nMinQP)
{
u32 nQbound;
nQbound = VIDC_SETFIELD(nMaxQP,
VIDC_SM_I_FRAME_QBOUND_MAX_QP_IFRAME_SHFT,
VIDC_SM_I_FRAME_QBOUND_MAX_QP_IFRAME_BMSK) |
VIDC_SETFIELD(nMinQP,
VIDC_SM_I_FRAME_QBOUND_MIN_QP_IFRAME_SHFT,
VIDC_SM_I_FRAME_QBOUND_MIN_QP_IFRAME_BMSK);
DDL_MEM_WRITE_32 (shared_mem, VIDC_SM_I_FRAME_QBOUND_IFRAME_ADDR,
nQbound);
}
void vidc_pix_cache_init_config(
struct vidc_1080P_pix_cache_config *config)
{
u32 cfg_reg = 0;
if (config->cache_enable)
cfg_reg |= HWIO_REG_22756_CACHE_EN_BMSK;
else
cfg_reg &= (~HWIO_REG_22756_CACHE_EN_BMSK);
if (config->port_select == VIDC_1080P_PIX_CACHE_PORT_A)
cfg_reg &=
(~HWIO_REG_22756_CACHE_PORT_SELECT_BMSK);
else
cfg_reg |= HWIO_REG_22756_CACHE_PORT_SELECT_BMSK;
if (!config->statistics_off)
cfg_reg |= HWIO_REG_22756_STATISTICS_OFF_BMSK;
else
cfg_reg &= (~HWIO_REG_22756_STATISTICS_OFF_BMSK);
if (config->prefetch_en)
cfg_reg |= HWIO_REG_22756_PREFETCH_EN_BMSK;
else
cfg_reg &= (~HWIO_REG_22756_PREFETCH_EN_BMSK);
cfg_reg &= (~HWIO_REG_22756_PAGE_SIZE_BMSK);
cfg_reg |= VIDC_SETFIELD(config->page_size,
HWIO_REG_22756_PAGE_SIZE_SHFT,
HWIO_REG_22756_PAGE_SIZE_BMSK);
VIDC_HWIO_OUT(REG_22756, cfg_reg);
}
void vidc_sm_set_encoder_vop_time(struct ddl_buf_addr *shared_mem,
u32 vop_time_enable, u32 time_resolution, u32 frame_delta)
{
u32 vop_time;
vop_time = VIDC_SETFIELD((vop_time_enable) ? 1 : 0,
VIDC_SM_ENC_VOP_TIMING_ENABLE_SHFT ,
VIDC_SM_ENC_VOP_TIMING_ENABLE_BMSK) |
VIDC_SETFIELD(time_resolution ,
VIDC_SM_ENC_VOP_TIMING_TIME_RESOLUTION_SHFT,
VIDC_SM_ENC_VOP_TIMING_TIME_RESOLUTION_BMSK) |
VIDC_SETFIELD(frame_delta,
VIDC_SM_ENC_VOP_TIMING_FRAME_DELTA_SHFT,
VIDC_SM_ENC_VOP_TIMING_FRAME_DELTA_BMSK);
DDL_MEM_WRITE_32(shared_mem, VIDC_SM_ENC_VOP_TIMING_ADDR, vop_time);
}
void vidc_sm_set_encoder_param_change(struct ddl_buf_addr *shared_mem,
u32 bit_rate_chg, u32 frame_rate_chg, u32 i_period_chg)
{
u32 enc_param_chg;
enc_param_chg = VIDC_SETFIELD((bit_rate_chg) ? 1 : 0,
VIDC_SM_ENC_PARAM_CHANGE_RC_BIT_RATE_SHFT,
VIDC_SM_ENC_PARAM_CHANGE_RC_BIT_RATE_BMSK) |
VIDC_SETFIELD((frame_rate_chg) ? 1 : 0,
VIDC_SM_ENC_PARAM_CHANGE_RC_FRAME_RATE_SHFT,
VIDC_SM_ENC_PARAM_CHANGE_RC_FRAME_RATE_BMSK) |
VIDC_SETFIELD((i_period_chg) ? 1 : 0,
VIDC_SM_ENC_PARAM_CHANGE_I_PERIOD_SHFT,
VIDC_SM_ENC_PARAM_CHANGE_I_PERIOD_BMSK);
DDL_MEM_WRITE_32(shared_mem, VIDC_SM_ENC_PARAM_CHANGE_ADDR,
enc_param_chg);
}
void vidc_sm_set_extended_encoder_control(struct ddl_buf_addr
*shared_mem, u32 hec_enable,
enum VIDC_SM_frame_skip frame_skip_mode,
u32 seq_hdr_in_band, u32 vbv_buffer_size, u32 cpcfc_enable,
u32 sps_pps_control, u32 closed_gop_enable)
{
u32 enc_ctrl;
enc_ctrl = VIDC_SETFIELD((hec_enable) ? 1 : 0,
VIDC_SM_ENC_EXT_CTRL_HEC_ENABLE_SHFT,
VIDC_SM_ENC_EXT_CTRL_HEC_ENABLE_BMSK) |
VIDC_SETFIELD((u32) frame_skip_mode,
VIDC_SM_ENC_EXT_CTRL_FRAME_SKIP_ENABLE_SHFT,
VIDC_SM_ENC_EXT_CTRL_FRAME_SKIP_ENABLE_BMSK) |
VIDC_SETFIELD((seq_hdr_in_band) ? 1 : 0 ,
VIDC_SM_ENC_EXT_CTRL_SEQ_HDR_CTRL_SHFT ,
VIDC_SM_ENC_EXT_CTRL_SEQ_HDR_CTRL_BMSK) |
VIDC_SETFIELD(vbv_buffer_size,
VIDC_SM_ENC_EXT_CTRL_VBV_BUFFER_SIZE_SHFT,
VIDC_SM_ENC_EXT_CTRL_VBV_BUFFER_SIZE_BMSK) |
VIDC_SETFIELD((cpcfc_enable) ? 1 : 0,
VIDC_SM_ENC_EXT_CTRL_H263_CPCFC_ENABLE_SHFT,
VIDC_SM_ENC_EXT_CTRL_H263_CPCFC_ENABLE_BMSK) |
VIDC_SETFIELD((sps_pps_control) ? 1 : 0,
VIDC_SM_ENC_EXT_CTRL_SPS_PPS_CONTROL_SHFT,
VIDC_SM_ENC_EXT_CTRL_SPS_PPS_CONTROL_BMSK) |
VIDC_SETFIELD(closed_gop_enable,
VIDC_SM_ENC_EXT_CTRL_CLOSED_GOP_ENABLE_SHFT,
VIDC_SM_ENC_EXT_CTRL_CLOSED_GOP_ENABLE_BMSK);
DDL_MEM_WRITE_32(shared_mem, VIDC_SM_ENC_EXT_CTRL_ADDR, enc_ctrl);
}
void vidc_sm_set_metadata_enable(struct ddl_buf_addr_type *p_shared_mem,
u32 b_extradata_enable, u32 b_qp_enable, u32 b_concealed_mb_enable,
u32 b_vc1Param_enable, u32 b_sei_nal_enable, u32 b_vui_enable,
u32 b_enc_slice_size_enable)
{
u32 n_metadata_enable;
n_metadata_enable = VIDC_SETFIELD((b_extradata_enable) ? 1 : 0,
VIDC_SM_METADATA_ENABLE_EXTRADATA_SHFT,
VIDC_SM_METADATA_ENABLE_EXTRADATA_BMSK) |
VIDC_SETFIELD((b_enc_slice_size_enable) ? 1 : 0,
VIDC_SM_METADATA_ENABLE_ENC_SLICE_SIZE_SHFT,
VIDC_SM_METADATA_ENABLE_ENC_SLICE_SIZE_BMSK) |
VIDC_SETFIELD((b_vui_enable) ? 1 : 0,
VIDC_SM_METADATA_ENABLE_VUI_SHFT,
VIDC_SM_METADATA_ENABLE_VUI_BMSK) |
VIDC_SETFIELD((b_sei_nal_enable) ? 1 : 0,
VIDC_SM_METADATA_ENABLE_SEI_VIDC_SHFT,
VIDC_SM_METADATA_ENABLE_SEI_VIDC_BMSK) |
VIDC_SETFIELD((b_vc1Param_enable) ? 1 : 0,
VIDC_SM_METADATA_ENABLE_VC1_PARAM_SHFT,
VIDC_SM_METADATA_ENABLE_VC1_PARAM_BMSK) |
VIDC_SETFIELD((b_concealed_mb_enable) ? 1 : 0,
VIDC_SM_METADATA_ENABLE_CONCEALED_MB_SHFT,
VIDC_SM_METADATA_ENABLE_CONCEALED_MB_BMSK) |
VIDC_SETFIELD((b_qp_enable) ? 1 : 0,
VIDC_SM_METADATA_ENABLE_QP_SHFT,
VIDC_SM_METADATA_ENABLE_QP_BMSK);
DDL_MEM_WRITE_32(p_shared_mem, VIDC_SM_METADATA_ENABLE_ADDR,
n_metadata_enable);
}
void vidc_sm_set_idr_decode_only(struct ddl_buf_addr *shared_mem,
u32 enable)
{
u32 idr_decode_only = VIDC_SETFIELD((enable) ? 1 : 0,
VIDC_SM_IDR_DECODING_ONLY_SHIFT,
VIDC_SM_IDR_DECODING_ONLY_BMSK
);
DDL_MEM_WRITE_32(shared_mem, VIDC_SM_IDR_DECODING_ONLY_ADDR,
idr_decode_only);
}
void vidc_sm_set_chroma_addr_change(struct ddl_buf_addr *shared_mem,
u32 addr_change)
{
u32 chroma_addr_change = VIDC_SETFIELD((addr_change) ? 1 : 0,
VIDC_SM_CHROMA_ADDR_CHANGE_SHFT,
VIDC_SM_CHROMA_ADDR_CHANGE_BMASK);
DDL_MEM_WRITE_32(shared_mem, VIDC_SM_CHROMA_ADDR_CHANGE_ADDR,
chroma_addr_change);
}
void vidc_pix_cache_set_misr_filter_trans(u32 no_of_trans)
{
u32 misr_cfg_reg = 0;
VIDC_HWIO_IN(REG_883784, &misr_cfg_reg);
misr_cfg_reg &= (~HWIO_REG_883784_COUNTER_BMSK);
misr_cfg_reg |= VIDC_SETFIELD(no_of_trans,
HWIO_REG_883784_COUNTER_SHFT,
HWIO_REG_883784_COUNTER_BMSK);
VIDC_HWIO_OUT(REG_261029, misr_cfg_reg);
}
void vidc_pix_cache_set_misr_interface(u32 input_select)
{
u32 misr_cfg_reg = 0;
VIDC_HWIO_IN(REG_883784, &misr_cfg_reg);
misr_cfg_reg &= (~HWIO_REG_883784_INPUT_SEL_BMSK);
misr_cfg_reg |= VIDC_SETFIELD(input_select,
HWIO_REG_883784_INPUT_SEL_SHFT,
HWIO_REG_883784_INPUT_SEL_BMSK);
VIDC_HWIO_OUT(REG_261029, misr_cfg_reg);
}
void vidc_sm_set_extradata_presence(struct ddl_buf_addr *shared_mem,
u32 extradata_present)
{
u32 put_extradata;
put_extradata = VIDC_SETFIELD((extradata_present) ? 1 : 0,
VIDC_SM_PUT_EXTRADATA_PUT_SHFT,
VIDC_SM_PUT_EXTRADATA_PUT_BMSK);
DDL_MEM_WRITE_32(shared_mem, VIDC_SM_PUT_EXTRADATA_ADDR,
put_extradata);
}
void vidc_pix_cache_set_prefetch_page_limit(u32 page_size_limit)
{
u32 cfg_reg = 0;
VIDC_HWIO_IN(REG_22756, &cfg_reg);
cfg_reg &= (~HWIO_REG_22756_PAGE_SIZE_BMSK);
cfg_reg |= VIDC_SETFIELD(page_size_limit,
HWIO_REG_22756_PAGE_SIZE_SHFT,
HWIO_REG_22756_PAGE_SIZE_BMSK);
VIDC_HWIO_OUT(REG_22756, cfg_reg);
}
void vidc_sm_set_error_concealment_config(struct ddl_buf_addr *shared_mem,
u32 inter_slice, u32 intra_slice, u32 conceal_config_enable)
{
u32 error_conceal_config = 0;
error_conceal_config = VIDC_SETFIELD(inter_slice,
VIDC_SM_ERROR_CONCEALMENT_CONFIG_INTER_SLICE_SHFT,
VIDC_SM_ERROR_CONCEALMENT_CONFIG_INTER_SLICE_BMSK);
error_conceal_config |= VIDC_SETFIELD(intra_slice,
VIDC_SM_ERROR_CONCEALMENT_CONFIG_INTRA_SLICE_SHFT,
VIDC_SM_ERROR_CONCEALMENT_CONFIG_INTRA_SLICE_BMSK);
error_conceal_config |= VIDC_SETFIELD(conceal_config_enable,
VIDC_SM_ERROR_CONCEALMENT_CONFIG_CONCEAL_ENABLE_SHFT,
VIDC_SM_ERROR_CONCEALMENT_CONFIG_CONCEAL_ENABLE_BMSK);
DDL_MEM_WRITE_32(shared_mem, VIDC_SM_ERROR_CONCEALMENT_CONFIG_ADDR,
error_conceal_config);
}
void vidc_sm_set_extradata_presence(struct ddl_buf_addr_type *p_shared_mem,
u32 b_extradata_present)
{
u32 n_put_extradata;
n_put_extradata = VIDC_SETFIELD((b_extradata_present) ? 1 : 0,
VIDC_SM_PUT_EXTRADATA_PUT_SHFT,
VIDC_SM_PUT_EXTRADATA_PUT_BMSK);
DDL_MEM_WRITE_32(p_shared_mem, VIDC_SM_PUT_EXTRADATA_ADDR,
n_put_extradata);
}
void vidc_pix_cache_set_ram(u32 ram_select)
{
u32 dmi_cfg_reg = 0;
VIDC_HWIO_IN(REG_261029, &dmi_cfg_reg);
dmi_cfg_reg &= (~HWIO_REG_261029_DMI_RAM_SEL_BMSK);
dmi_cfg_reg |= VIDC_SETFIELD(ram_select,
HWIO_REG_261029_AUTO_INC_EN_SHFT,
HWIO_REG_261029_DMI_RAM_SEL_BMSK);
VIDC_HWIO_OUT(REG_261029, dmi_cfg_reg);
}
void vidc_sm_set_encoder_slice_batch_int_ctrl(struct ddl_buf_addr *shared_mem,
u32 slice_batch_int_enable)
{
u32 slice_batch_int_ctrl = VIDC_SETFIELD((slice_batch_int_enable) ?
1 : 0,
VIDC_SM_ENC_EXT_CTRL_HEC_ENABLE_SHFT,
VIDC_SM_ENC_EXT_CTRL_HEC_ENABLE_BMSK);
DDL_MEM_WRITE_32(shared_mem,
VIDC_SM_ENC_SLICE_BATCH_INT_CTRL_ADDR,
slice_batch_int_ctrl);
}
void vidc_sm_set_extended_encoder_control(struct ddl_buf_addr_type
*p_shared_mem, u32 b_hec_enable,
enum VIDC_SM_frame_skip_type e_frame_skip_mode,
u32 b_seq_hdr_in_band, u32 n_vbv_buffer_size)
{
u32 n_enc_ctrl;
n_enc_ctrl = VIDC_SETFIELD((b_hec_enable) ? 1 : 0,
VIDC_SM_ENC_EXT_CTRL_HEC_ENABLE_SHFT,
VIDC_SM_ENC_EXT_CTRL_HEC_ENABLE_BMSK) |
VIDC_SETFIELD((u32) e_frame_skip_mode,
VIDC_SM_ENC_EXT_CTRL_FRAME_SKIP_ENABLE_SHFT,
VIDC_SM_ENC_EXT_CTRL_FRAME_SKIP_ENABLE_BMSK) |
VIDC_SETFIELD((b_seq_hdr_in_band) ? 1 : 0 ,
VIDC_SM_ENC_EXT_CTRL_SEQ_HDR_CTRL_SHFT ,
VIDC_SM_ENC_EXT_CTRL_SEQ_HDR_CTRL_BMSK) |
VIDC_SETFIELD(n_vbv_buffer_size,
VIDC_SM_ENC_EXT_CTRL_VBV_BUFFER_SIZE_SHFT,
VIDC_SM_ENC_EXT_CTRL_VBV_BUFFER_SIZE_BMSK);
DDL_MEM_WRITE_32(p_shared_mem, VIDC_SM_ENC_EXT_CTRL_ADDR, n_enc_ctrl);
}
void vidc_sm_set_mp2datadump_enable(struct ddl_buf_addr *shared_mem,
struct ddl_mp2_datadumpenabletype *ddl_mp2_datadump_enable)
{
u32 mp2_datadump_enable = 0;
mp2_datadump_enable = VIDC_SETFIELD(
ddl_mp2_datadump_enable->userdatadump_enable,
VIDC_SM_MP2_USERDATA_DUMP_ENABLE_SHFT,
VIDC_SM_MP2_USERDATA_DUMP_ENABLE_BMSK) |
VIDC_SETFIELD(ddl_mp2_datadump_enable->
pictempscalable_extdump_enable ? 1 : 0,
VIDC_SM_MP2_PICT_TEMP_DUMP_ENABLE_SHFT,
VIDC_SM_MP2_PICT_TEMP_DUMP_ENABLE_BMSK) |
VIDC_SETFIELD(ddl_mp2_datadump_enable->
picspat_extdump_enable ? 1 : 0,
VIDC_SM_MP2_PICT_SPAT_EXT_DUMP_ENABLE_SHFT,
VIDC_SM_MP2_PICT_SPAT_EXT_DUMP_ENABLE_BMSK) |
VIDC_SETFIELD(ddl_mp2_datadump_enable->
picdisp_extdump_enable ? 1 : 0,
VIDC_SM_MP2_PICT_DISP_EXT_DUMP_ENABLE_SHFT,
VIDC_SM_MP2_PICT_DISP_EXT_DUMP_ENABLE_BMSK) |
VIDC_SETFIELD(ddl_mp2_datadump_enable->
copyright_extdump_enable ? 1 : 0,
VIDC_SM_MP2_COPYRIGHT_EXT_DUMP_ENABLE_SHFT,
VIDC_SM_MP2_COPYRIGHT_EXT_DUMP_ENABLE_BMSK) |
VIDC_SETFIELD(ddl_mp2_datadump_enable->
quantmatrix_extdump_enable ? 1 : 0,
VIDC_SM_MP2_QMATRIX_EXT_DUMP_ENABLE_SHFT,
VIDC_SM_MP2_QMATRIX_EXT_DUMP_ENABLE_BMSK) |
VIDC_SETFIELD(ddl_mp2_datadump_enable->
seqscalable_extdump_enable ? 1 : 0,
VIDC_SM_MP2_SCAL_EXT_DUMP_ENABLE_SHFT,
VIDC_SM_MP2_SCAL_EXT_DUMP_ENABLE_BMSK) |
VIDC_SETFIELD(ddl_mp2_datadump_enable->
seqdisp_extdump_enable ? 1 : 0,
VIDC_SM_MP2_SEQ_DISP_EXT_DUMP_ENABLE_SHFT,
VIDC_SM_MP2_SEQ_DISP_EXT_DUMP_ENABLE_BMSK) |
VIDC_SETFIELD(ddl_mp2_datadump_enable->
seq_extdump_enable ? 1 : 0,
VIDC_SM_MP2_SEQ_EXT_DUMP_ENABLE_SHFT,
VIDC_SM_MP2_SEQ_EXT_DUMP_ENABLE_BMSK);
DDL_MEM_WRITE_32(shared_mem, VIDC_SM_MP2_DATA_DUMP_CONTROL_ADDR,
mp2_datadump_enable);
}
void vidc_pix_cache_set_misr_id_filtering(
struct vidc_1080P_pix_cache_misr_id_filtering *filter_id)
{
u32 misr_cfg_reg = 0;
VIDC_HWIO_IN(REG_883784, &misr_cfg_reg);
if (filter_id->ignore_id)
misr_cfg_reg |=
HWIO_REG_883784_IGNORE_ID_BMSK;
else
misr_cfg_reg &=
(~HWIO_REG_883784_IGNORE_ID_BMSK);
misr_cfg_reg &= (~HWIO_REG_883784_ID_BMSK);
misr_cfg_reg |= VIDC_SETFIELD(filter_id->id,
HWIO_REG_883784_ID_SHFT,
HWIO_REG_883784_ID_BMSK);
VIDC_HWIO_OUT(REG_261029, misr_cfg_reg);
}
VIDC_SM_DEC_CROP_INFO2_BOTTOM_OFFSET_SHFT);
}
void vidc_sm_set_extended_encoder_control(struct ddl_buf_addr
*shared_mem, u32 hec_enable,
enum VIDC_SM_frame_skip frame_skip_mode,
#if 0 //ksnr QC Patch for H263-Non-PlusType Encoding
u32 seq_hdr_in_band, u32 vbv_buffer_size)
#else
u32 seq_hdr_in_band, u32 vbv_buffer_size, u32 cpcfc_enable)
#endif
{
u32 enc_ctrl;
enc_ctrl = VIDC_SETFIELD((hec_enable) ? 1 : 0,
VIDC_SM_ENC_EXT_CTRL_HEC_ENABLE_SHFT,
VIDC_SM_ENC_EXT_CTRL_HEC_ENABLE_BMSK) |
VIDC_SETFIELD((u32) frame_skip_mode,
VIDC_SM_ENC_EXT_CTRL_FRAME_SKIP_ENABLE_SHFT,
VIDC_SM_ENC_EXT_CTRL_FRAME_SKIP_ENABLE_BMSK) |
VIDC_SETFIELD((seq_hdr_in_band) ? 1 : 0 ,
VIDC_SM_ENC_EXT_CTRL_SEQ_HDR_CTRL_SHFT ,
VIDC_SM_ENC_EXT_CTRL_SEQ_HDR_CTRL_BMSK) |
VIDC_SETFIELD(vbv_buffer_size,
VIDC_SM_ENC_EXT_CTRL_VBV_BUFFER_SIZE_SHFT,
#if 0 //ksnr QC Patch for H263-Non-PlusType Encoding
VIDC_SM_ENC_EXT_CTRL_VBV_BUFFER_SIZE_BMSK);
#else
VIDC_SM_ENC_EXT_CTRL_VBV_BUFFER_SIZE_BMSK) |
VIDC_SETFIELD((cpcfc_enable) ? 1 : 0,
VIDC_SM_ENC_EXT_CTRL_H263_CPCFC_ENABLE_SHFT,
void vidc_sm_set_extended_encoder_control(struct ddl_buf_addr
*shared_mem, u32 hec_enable,
enum VIDC_SM_frame_skip frame_skip_mode,
u32 seq_hdr_in_band, u32 vbv_buffer_size, u32 cpcfc_enable,
u32 sps_pps_control, u32 pic_order_count, u32 closed_gop_enable,
u32 au_delim_enable, u32 vui_timing_info_enable,
u32 restrict_bitstream_enable, u32 ltr_enable)
{
u32 enc_ctrl;
enc_ctrl = VIDC_SETFIELD((hec_enable) ? 1 : 0,
VIDC_SM_ENC_EXT_CTRL_HEC_ENABLE_SHFT,
VIDC_SM_ENC_EXT_CTRL_HEC_ENABLE_BMSK) |
VIDC_SETFIELD((u32) frame_skip_mode,
VIDC_SM_ENC_EXT_CTRL_FRAME_SKIP_ENABLE_SHFT,
VIDC_SM_ENC_EXT_CTRL_FRAME_SKIP_ENABLE_BMSK) |
VIDC_SETFIELD((seq_hdr_in_band) ? 1 : 0 ,
VIDC_SM_ENC_EXT_CTRL_SEQ_HDR_CTRL_SHFT ,
VIDC_SM_ENC_EXT_CTRL_SEQ_HDR_CTRL_BMSK) |
VIDC_SETFIELD(vbv_buffer_size,
VIDC_SM_ENC_EXT_CTRL_VBV_BUFFER_SIZE_SHFT,
VIDC_SM_ENC_EXT_CTRL_VBV_BUFFER_SIZE_BMSK) |
VIDC_SETFIELD((cpcfc_enable) ? 1 : 0,
VIDC_SM_ENC_EXT_CTRL_H263_CPCFC_ENABLE_SHFT,
VIDC_SM_ENC_EXT_CTRL_H263_CPCFC_ENABLE_BMSK) |
VIDC_SETFIELD((sps_pps_control) ? 1 : 0,
VIDC_SM_ENC_EXT_CTRL_SPS_PPS_CONTROL_SHFT,
VIDC_SM_ENC_EXT_CTRL_SPS_PPS_CONTROL_BMSK) |
VIDC_SETFIELD((pic_order_count) ? 1 : 0,
VIDC_SM_ENC_EXT_CTRL_PIC_ORDER_ENABLE_SHFT,
VIDC_SM_ENC_EXT_CTRL_PIC_ORDER_ENABLE_BMSK) |
VIDC_SETFIELD(closed_gop_enable,
VIDC_SM_ENC_EXT_CTRL_CLOSED_GOP_ENABLE_SHFT,
VIDC_SM_ENC_EXT_CTRL_CLOSED_GOP_ENABLE_BMSK) |
VIDC_SETFIELD((au_delim_enable) ? 1 : 0,
VIDC_SM_ENC_EXT_CTRL_AU_DELIMITER_EN_SHFT,
VIDC_SM_ENC_EXT_CTRL_AU_DELIMITER_EN_BMSK) |
VIDC_SETFIELD((vui_timing_info_enable) ? 1 : 0,
VIDC_SM_ENC_EXT_CTRL_TIMING_INFO_EN_SHFT,
VIDC_SM_ENC_EXT_CTRL_TIMING_INFO_EN_BMSK) |
VIDC_SETFIELD((restrict_bitstream_enable) ? 1 : 0,
VIDC_SM_ENC_EXT_CTRL_STREAM_RESTRICT_EN_SHFT,
VIDC_SM_ENC_EXT_CTRL_STREAM_RESTRICT_EN_BMSK) |
VIDC_SETFIELD((ltr_enable) ? 1 : 0,
VIDC_SM_ENC_EXT_CTRL_LONG_TERM_REF_ENABLE_SHFT,
VIDC_SM_ENC_EXT_CTRL_LONG_TERM_REF_ENABLE_BMSK);
DDL_MEM_WRITE_32(shared_mem, VIDC_SM_ENC_EXT_CTRL_ADDR, enc_ctrl);
}
