static void *
etna_create_sampler_state(struct pipe_context *pipe,
const struct pipe_sampler_state *ss)
{
struct etna_sampler_state *cs = CALLOC_STRUCT(etna_sampler_state);
if (!cs)
return NULL;
cs->TE_SAMPLER_CONFIG0 =
VIVS_TE_SAMPLER_CONFIG0_UWRAP(translate_texture_wrapmode(ss->wrap_s)) |
VIVS_TE_SAMPLER_CONFIG0_VWRAP(translate_texture_wrapmode(ss->wrap_t)) |
VIVS_TE_SAMPLER_CONFIG0_MIN(translate_texture_filter(ss->min_img_filter)) |
VIVS_TE_SAMPLER_CONFIG0_MIP(translate_texture_mipfilter(ss->min_mip_filter)) |
VIVS_TE_SAMPLER_CONFIG0_MAG(translate_texture_filter(ss->mag_img_filter)) |
COND(ss->normalized_coords, VIVS_TE_SAMPLER_CONFIG0_ROUND_UV);
cs->TE_SAMPLER_CONFIG1 = 0; /* VIVS_TE_SAMPLER_CONFIG1 (swizzle, extended
format) fully determined by sampler view */
cs->TE_SAMPLER_LOD_CONFIG =
COND(ss->lod_bias != 0.0, VIVS_TE_SAMPLER_LOD_CONFIG_BIAS_ENABLE) |
VIVS_TE_SAMPLER_LOD_CONFIG_BIAS(etna_float_to_fixp55(ss->lod_bias));
if (ss->min_mip_filter != PIPE_TEX_MIPFILTER_NONE) {
cs->min_lod = etna_float_to_fixp55(ss->min_lod);
cs->max_lod = etna_float_to_fixp55(ss->max_lod);
} else {
/* when not mipmapping, we need to set max/min lod so that always
* lowest LOD is selected */
cs->min_lod = cs->max_lod = etna_float_to_fixp55(ss->min_lod);
}
return cs;
}
static void *etna_pipe_create_sampler_state(struct pipe_context *pipe,
const struct pipe_sampler_state *ss)
{
//struct etna_pipe_context *priv = etna_pipe_context(pipe);
struct compiled_sampler_state *cs = CALLOC_STRUCT(compiled_sampler_state);
cs->TE_SAMPLER_CONFIG0 =
/* XXX get from sampler view: VIVS_TE_SAMPLER_CONFIG0_TYPE(TEXTURE_TYPE_2D)| */
VIVS_TE_SAMPLER_CONFIG0_UWRAP(translate_texture_wrapmode(ss->wrap_s))|
VIVS_TE_SAMPLER_CONFIG0_VWRAP(translate_texture_wrapmode(ss->wrap_t))|
VIVS_TE_SAMPLER_CONFIG0_MIN(translate_texture_filter(ss->min_img_filter))|
VIVS_TE_SAMPLER_CONFIG0_MIP(translate_texture_mipfilter(ss->min_mip_filter))|
VIVS_TE_SAMPLER_CONFIG0_MAG(translate_texture_filter(ss->mag_img_filter));
/* XXX get from sampler view: VIVS_TE_SAMPLER_CONFIG0_FORMAT(tex_format) */
cs->TE_SAMPLER_CONFIG1 = 0; /* VIVS_TE_SAMPLER_CONFIG1 (swizzle, extended format) fully determined by sampler view */
cs->TE_SAMPLER_LOD_CONFIG =
(ss->lod_bias != 0.0 ? VIVS_TE_SAMPLER_LOD_CONFIG_BIAS_ENABLE : 0) |
VIVS_TE_SAMPLER_LOD_CONFIG_BIAS(float_to_fixp55(ss->lod_bias));
if(ss->min_mip_filter != PIPE_TEX_MIPFILTER_NONE)
{
cs->min_lod = float_to_fixp55(ss->min_lod);
cs->max_lod = float_to_fixp55(ss->max_lod);
} else { /* when not mipmapping, we need to set max/min lod so that always lowest LOD is selected */
cs->min_lod = cs->max_lod = float_to_fixp55(ss->min_lod);
}
return cs;
}
static struct pipe_sampler_view *etna_pipe_create_sampler_view(struct pipe_context *pipe,
struct pipe_resource *texture,
const struct pipe_sampler_view *templat)
{
struct etna_pipe_context *priv = etna_pipe_context(pipe);
struct etna_sampler_view *sv = CALLOC_STRUCT(etna_sampler_view);
sv->base = *templat;
sv->base.context = pipe;
sv->base.texture = 0;
pipe_resource_reference(&sv->base.texture, texture);
sv->base.texture = texture;
assert(sv->base.texture);
struct compiled_sampler_view *cs = CALLOC_STRUCT(compiled_sampler_view);
struct etna_resource *res = etna_resource(sv->base.texture);
assert(res != NULL);
cs->TE_SAMPLER_CONFIG0 =
VIVS_TE_SAMPLER_CONFIG0_TYPE(translate_texture_target(res->base.target, false)) |
VIVS_TE_SAMPLER_CONFIG0_FORMAT(translate_texture_format(sv->base.format, false));
/* merged with sampler state */
cs->TE_SAMPLER_CONFIG0_MASK = 0xffffffff;
cs->TE_SAMPLER_CONFIG1 =
VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_R(templat->swizzle_r) |
VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_G(templat->swizzle_g) |
VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_B(templat->swizzle_b) |
VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_A(templat->swizzle_a) |
VIVS_TE_SAMPLER_CONFIG1_HALIGN(res->halign);
cs->TE_SAMPLER_SIZE =
VIVS_TE_SAMPLER_SIZE_WIDTH(res->base.width0)|
VIVS_TE_SAMPLER_SIZE_HEIGHT(res->base.height0);
cs->TE_SAMPLER_LOG_SIZE =
VIVS_TE_SAMPLER_LOG_SIZE_WIDTH(etna_log2_fixp55(res->base.width0)) |
VIVS_TE_SAMPLER_LOG_SIZE_HEIGHT(etna_log2_fixp55(res->base.height0));
/* Set up levels-of-detail */
for(int lod=0; lod<=res->base.last_level; ++lod)
{
cs->TE_SAMPLER_LOD_ADDR[lod] = etna_bo_gpu_address(res->bo) + res->levels[lod].offset;
}
cs->min_lod = sv->base.u.tex.first_level << 5;
cs->max_lod = MIN2(sv->base.u.tex.last_level, res->base.last_level) << 5;
/* Workaround for npot textures -- it appears that only CLAMP_TO_EDGE is supported when the
* appropriate capability is not set. */
if(!priv->specs.npot_tex_any_wrap &&
(!util_is_power_of_two(res->base.width0) || !util_is_power_of_two(res->base.height0)))
{
cs->TE_SAMPLER_CONFIG0_MASK = ~(VIVS_TE_SAMPLER_CONFIG0_UWRAP__MASK |
VIVS_TE_SAMPLER_CONFIG0_VWRAP__MASK);
cs->TE_SAMPLER_CONFIG0 |= VIVS_TE_SAMPLER_CONFIG0_UWRAP(TEXTURE_WRAPMODE_CLAMP_TO_EDGE) |
VIVS_TE_SAMPLER_CONFIG0_VWRAP(TEXTURE_WRAPMODE_CLAMP_TO_EDGE);
}
sv->internal = cs;
pipe_reference_init(&sv->base.reference, 1);
return &sv->base;
}
int main(int argc, char **argv)
{
int rv;
int width, height;
int width_s, height_s;
int padded_width, padded_height;
int backbuffer = 0;
int supersample_x = 2; // 1 or 2
int supersample_y = 2; // 1 or 2
int extra_ps_inputs = 0;
fb_info fb;
rv = fb_open(0, &fb);
if(rv!=0)
{
exit(1);
}
width = fb.fb_var.xres;
height = fb.fb_var.yres;
width_s = width * supersample_x;
height_s = height * supersample_y;
padded_width = etna_align_up(width_s, 64);
padded_height = etna_align_up(height_s, 64);
extra_ps_inputs = (supersample_x > 1 || supersample_y > 1); // in case of supersample, there is an extra input to PS
printf("padded_width %i padded_height %i\n", padded_width, padded_height);
rv = viv_open();
if(rv!=0)
{
fprintf(stderr, "Error opening device\n");
exit(1);
}
printf("Succesfully opened device\n");
etna_vidmem *rt = 0; /* main render target */
etna_vidmem *rt_ts = 0; /* tile status for main render target */
etna_vidmem *z = 0; /* depth for main render target */
etna_vidmem *z_ts = 0; /* depth ts for main render target */
etna_vidmem *vtx = 0; /* vertex buffer */
etna_vidmem *idx = 0; /* index buffer */
etna_vidmem *aux_rt = 0; /* auxilary render target */
etna_vidmem *aux_rt_ts = 0; /* tile status for auxilary render target */
etna_vidmem *tex = 0; /* texture */
etna_vidmem *bmp = 0; /* bitmap */
/* TODO: anti aliasing (doubles width/height) */
size_t rt_size = padded_width * padded_height * 4;
size_t rt_ts_size = etna_align_up((padded_width * padded_height * 4)/0x100, 0x100);
size_t z_size = padded_width * padded_height * 2;
size_t z_ts_size = etna_align_up((padded_width * padded_height * 2)/0x100, 0x100);
size_t bmp_size = width * height * 4;
if(etna_vidmem_alloc_linear(&rt, rt_size, gcvSURF_RENDER_TARGET, gcvPOOL_DEFAULT, true)!=ETNA_OK ||
etna_vidmem_alloc_linear(&rt_ts, rt_ts_size, gcvSURF_TILE_STATUS, gcvPOOL_DEFAULT, true)!=ETNA_OK ||
etna_vidmem_alloc_linear(&z, z_size, gcvSURF_DEPTH, gcvPOOL_DEFAULT, true)!=ETNA_OK ||
etna_vidmem_alloc_linear(&z_ts, z_ts_size, gcvSURF_TILE_STATUS, gcvPOOL_DEFAULT, true)!=ETNA_OK ||
etna_vidmem_alloc_linear(&vtx, VERTEX_BUFFER_SIZE, gcvSURF_VERTEX, gcvPOOL_DEFAULT, true)!=ETNA_OK ||
etna_vidmem_alloc_linear(&idx, INDEX_BUFFER_SIZE, gcvSURF_INDEX, gcvPOOL_DEFAULT, true)!=ETNA_OK ||
etna_vidmem_alloc_linear(&aux_rt, 0x4000, gcvSURF_RENDER_TARGET, gcvPOOL_SYSTEM, true)!=ETNA_OK ||
etna_vidmem_alloc_linear(&aux_rt_ts, 0x100, gcvSURF_TILE_STATUS, gcvPOOL_DEFAULT, true)!=ETNA_OK ||
etna_vidmem_alloc_linear(&tex, 0x100000, gcvSURF_TEXTURE, gcvPOOL_DEFAULT, true)!=ETNA_OK ||
etna_vidmem_alloc_linear(&bmp, bmp_size, gcvSURF_BITMAP, gcvPOOL_DEFAULT, true)!=ETNA_OK
)
{
fprintf(stderr, "Error allocating video memory\n");
exit(1);
}
/* Phew, now we got all the memory we need.
* Write interleaved attribute vertex stream.
* Unlike the GL example we only do this once, not every time glDrawArrays is called, the same would be accomplished
* from GL by using a vertex buffer object.
*/
memset(vtx->logical, 0, 0x5ef80);
#ifndef INDEXED
printf("Interleaving vertices...\n");
float *vertices_array = companion_vertices_array();
float *texture_coordinates_array =
companion_texture_coordinates_array();
float *normals_array = companion_normals_array();
assert(COMPANION_ARRAY_COUNT*(3+3+2)*sizeof(float) < VERTEX_BUFFER_SIZE);
for(int vert=0; vert<COMPANION_ARRAY_COUNT; ++vert)
{
int dest_idx = vert * (3 + 3 + 2);
for(int comp=0; comp<3; ++comp)
((float*)vtx->logical)[dest_idx+comp+0] = vertices_array[vert*3 + comp]; /* 0 */
for(int comp=0; comp<3; ++comp)
((float*)vtx->logical)[dest_idx+comp+3] = normals_array[vert*3 + comp]; /* 1 */
for(int comp=0; comp<2; ++comp)
((float*)vtx->logical)[dest_idx+comp+6] = texture_coordinates_array[vert*2 + comp]; /* 2 */
}
#else
printf("Interleaving vertices and copying index buffer...\n");
assert(COMPANION_VERTEX_COUNT*(3+3+2)*sizeof(float) < VERTEX_BUFFER_SIZE);
for(int vert=0; vert<COMPANION_VERTEX_COUNT; ++vert)
{
int dest_idx = vert * (3 + 3 + 2);
for(int comp=0; comp<3; ++comp)
((float*)vtx->logical)[dest_idx+comp+0] = companion_vertices[vert][comp]; /* 0 */
for(int comp=0; comp<3; ++comp)
((float*)vtx->logical)[dest_idx+comp+3] = companion_normals[vert][comp]; /* 1 */
for(int comp=0; comp<2; ++comp)
((float*)vtx->logical)[dest_idx+comp+6] = companion_texture_coordinates[vert][comp]; /* 2 */
}
assert(COMPANION_TRIANGLE_COUNT*3*sizeof(unsigned short) < INDEX_BUFFER_SIZE);
memcpy(idx->logical, &companion_triangles[0][0], COMPANION_TRIANGLE_COUNT*3*sizeof(unsigned short));
#endif
/* Fill in texture (convert from RGB linear to tiled) */
#define TILE_WIDTH (4)
#define TILE_HEIGHT (4)
#define TILE_WORDS (TILE_WIDTH*TILE_HEIGHT)
unsigned ytiles = COMPANION_TEXTURE_HEIGHT / TILE_HEIGHT;
unsigned xtiles = COMPANION_TEXTURE_WIDTH / TILE_WIDTH;
unsigned dst_stride = xtiles * TILE_WORDS;
for(unsigned ty=0; ty<ytiles; ++ty)
{
for(unsigned tx=0; tx<xtiles; ++tx)
{
unsigned ofs = ty * dst_stride + tx * TILE_WORDS;
for(unsigned y=0; y<TILE_HEIGHT; ++y)
{
for(unsigned x=0; x<TILE_WIDTH; ++x)
{
unsigned srcy = ty*TILE_HEIGHT + y;
unsigned srcx = tx*TILE_WIDTH + x;
unsigned src_ofs = (srcy*COMPANION_TEXTURE_WIDTH+srcx)*3;
unsigned r,g,b,a;
#ifndef TEST_PATTERN /* actual texture */
r = ((uint8_t*)companion_texture)[src_ofs+0];
g = ((uint8_t*)companion_texture)[src_ofs+1];
b = ((uint8_t*)companion_texture)[src_ofs+2];
#else /* test pattern */
r = srcx; g = srcy; b = 0;
#endif
a = 255;
((uint32_t*)tex->logical)[ofs] = ((a&0xFF) << 24) | ((b&0xFF) << 16) | ((g&0xFF) << 8) | (r&0xFF);
ofs += 1;
}
}
}
}
etna_ctx *ctx = 0;
if(etna_create(&ctx) != ETNA_OK)
{
printf("Unable to create context\n");
exit(1);
}
for(int frame=0; frame<1000; ++frame)
{
printf("*** FRAME %i ****\n", frame);
/* XXX part of this can be put outside the loop, but until we have usable context management
* this is safest.
*/
etna_set_state(ctx, VIVS_GL_VERTEX_ELEMENT_CONFIG, 0x1);
etna_set_state(ctx, VIVS_RA_CONTROL, 0x1);
etna_set_state(ctx, VIVS_PA_W_CLIP_LIMIT, 0x34000001);
etna_set_state(ctx, VIVS_PA_SYSTEM_MODE, 0x11);
etna_set_state(ctx, VIVS_PA_CONFIG, ETNA_MASKED_BIT(VIVS_PA_CONFIG_UNK22, 0));
etna_set_state(ctx, VIVS_SE_CONFIG, 0x0);
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR);
etna_set_state(ctx, VIVS_PE_ALPHA_CONFIG,
ETNA_MASKED_BIT(VIVS_PE_ALPHA_CONFIG_BLEND_ENABLE_COLOR, 0) &
ETNA_MASKED_BIT(VIVS_PE_ALPHA_CONFIG_BLEND_ENABLE_ALPHA, 0) &
ETNA_MASKED(VIVS_PE_ALPHA_CONFIG_SRC_FUNC_COLOR, BLEND_FUNC_ONE) &
ETNA_MASKED(VIVS_PE_ALPHA_CONFIG_SRC_FUNC_ALPHA, BLEND_FUNC_ONE) &
ETNA_MASKED(VIVS_PE_ALPHA_CONFIG_DST_FUNC_COLOR, BLEND_FUNC_ZERO) &
ETNA_MASKED(VIVS_PE_ALPHA_CONFIG_DST_FUNC_ALPHA, BLEND_FUNC_ZERO) &
ETNA_MASKED(VIVS_PE_ALPHA_CONFIG_EQ_COLOR, BLEND_EQ_ADD) &
ETNA_MASKED(VIVS_PE_ALPHA_CONFIG_EQ_ALPHA, BLEND_EQ_ADD));
etna_set_state(ctx, VIVS_PE_ALPHA_BLEND_COLOR,
VIVS_PE_ALPHA_BLEND_COLOR_B(0) |
VIVS_PE_ALPHA_BLEND_COLOR_G(0) |
VIVS_PE_ALPHA_BLEND_COLOR_R(0) |
VIVS_PE_ALPHA_BLEND_COLOR_A(0));
etna_set_state(ctx, VIVS_PE_ALPHA_OP, ETNA_MASKED_BIT(VIVS_PE_ALPHA_OP_ALPHA_TEST, 0));
etna_set_state(ctx, VIVS_PA_CONFIG, ETNA_MASKED_INL(VIVS_PA_CONFIG_CULL_FACE_MODE, CCW));
etna_set_state(ctx, VIVS_PE_STENCIL_CONFIG, ETNA_MASKED(VIVS_PE_STENCIL_CONFIG_REF_FRONT, 0) &
ETNA_MASKED(VIVS_PE_STENCIL_CONFIG_MASK_FRONT, 0xff) &
ETNA_MASKED(VIVS_PE_STENCIL_CONFIG_WRITE_MASK, 0xff) &
ETNA_MASKED_INL(VIVS_PE_STENCIL_CONFIG_MODE, DISABLED));
etna_set_state(ctx, VIVS_PE_STENCIL_OP, ETNA_MASKED(VIVS_PE_STENCIL_OP_FUNC_FRONT, COMPARE_FUNC_ALWAYS) &
ETNA_MASKED(VIVS_PE_STENCIL_OP_FUNC_BACK, COMPARE_FUNC_ALWAYS) &
ETNA_MASKED(VIVS_PE_STENCIL_OP_FAIL_FRONT, STENCIL_OP_KEEP) &
ETNA_MASKED(VIVS_PE_STENCIL_OP_FAIL_BACK, STENCIL_OP_KEEP) &
ETNA_MASKED(VIVS_PE_STENCIL_OP_DEPTH_FAIL_FRONT, STENCIL_OP_KEEP) &
ETNA_MASKED(VIVS_PE_STENCIL_OP_DEPTH_FAIL_BACK, STENCIL_OP_KEEP) &
ETNA_MASKED(VIVS_PE_STENCIL_OP_PASS_FRONT, STENCIL_OP_KEEP) &
ETNA_MASKED(VIVS_PE_STENCIL_OP_PASS_BACK, STENCIL_OP_KEEP));
etna_set_state(ctx, VIVS_SE_DEPTH_SCALE, 0x0);
etna_set_state(ctx, VIVS_SE_DEPTH_BIAS, 0x0);
etna_set_state(ctx, VIVS_PA_CONFIG, ETNA_MASKED_INL(VIVS_PA_CONFIG_FILL_MODE, SOLID) &
ETNA_MASKED_INL(VIVS_PA_CONFIG_SHADE_MODEL, SMOOTH));
etna_set_state(ctx, VIVS_PE_COLOR_FORMAT,
ETNA_MASKED_BIT(VIVS_PE_COLOR_FORMAT_PARTIAL, 0) &
ETNA_MASKED(VIVS_PE_COLOR_FORMAT_COMPONENTS, 0xf) &
ETNA_MASKED(VIVS_PE_COLOR_FORMAT_FORMAT, RS_FORMAT_X8R8G8B8) &
ETNA_MASKED_BIT(VIVS_PE_COLOR_FORMAT_SUPER_TILED, 1));
etna_set_state(ctx, VIVS_PE_COLOR_ADDR, rt->address);
etna_set_state(ctx, VIVS_PE_COLOR_STRIDE, padded_width * 4);
uint32_t ts_msaa_config;
if(supersample_x == 2 && supersample_y == 2)
{
// 4X MSAA
etna_set_state(ctx, VIVS_GL_MULTI_SAMPLE_CONFIG,
ETNA_MASKED_INL(VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES, 4X) &
ETNA_MASKED(VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES, 0xf) &
ETNA_MASKED(VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12, 0x0) &
ETNA_MASKED(VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16, 0x0)
);
etna_set_state(ctx, VIVS_RA_MULTISAMPLE_UNK00E04, 0x0);
etna_set_state(ctx, VIVS_RA_MULTISAMPLE_UNK00E10(2), 0xaaa22a22);
etna_set_state(ctx, VIVS_RA_CENTROID_TABLE(8), 0x262a2288);
etna_set_state(ctx, VIVS_RA_CENTROID_TABLE(9), 0x886688a2);
etna_set_state(ctx, VIVS_RA_CENTROID_TABLE(10), 0x888866aa);
etna_set_state(ctx, VIVS_RA_CENTROID_TABLE(11), 0x668888a6);
etna_set_state(ctx, VIVS_RA_MULTISAMPLE_UNK00E10(1), 0xe6ae622a);
etna_set_state(ctx, VIVS_RA_CENTROID_TABLE(4), 0x46622a88);
etna_set_state(ctx, VIVS_RA_CENTROID_TABLE(5), 0x888888ae);
etna_set_state(ctx, VIVS_RA_CENTROID_TABLE(6), 0x888888e6);
etna_set_state(ctx, VIVS_RA_CENTROID_TABLE(7), 0x888888ca);
etna_set_state(ctx, VIVS_RA_MULTISAMPLE_UNK00E10(0), 0xeaa26e26);
etna_set_state(ctx, VIVS_RA_CENTROID_TABLE(0), 0x4a6e2688);
etna_set_state(ctx, VIVS_RA_CENTROID_TABLE(1), 0x888888a2);
etna_set_state(ctx, VIVS_RA_CENTROID_TABLE(2), 0x888888ea);
etna_set_state(ctx, VIVS_RA_CENTROID_TABLE(3), 0x888888c6);
ts_msaa_config = VIVS_TS_MEM_CONFIG_MSAA | VIVS_TS_MEM_CONFIG_MSAA_FORMAT_A8R8G8B8;
} else if(supersample_x == 2 && supersample_y == 1)
{
// 2X MSAA
etna_set_state(ctx, VIVS_GL_MULTI_SAMPLE_CONFIG,
ETNA_MASKED_INL(VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES, 2X) &
ETNA_MASKED(VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES, 0xf) &
ETNA_MASKED(VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12, 0x0) &
ETNA_MASKED(VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16, 0x0)
);
etna_set_state(ctx, VIVS_RA_MULTISAMPLE_UNK00E04, 0x0);
etna_set_state(ctx, VIVS_RA_MULTISAMPLE_UNK00E10(0), 0xaa22);
etna_set_state(ctx, VIVS_RA_CENTROID_TABLE(0), 0x66aa2288);
etna_set_state(ctx, VIVS_RA_CENTROID_TABLE(1), 0x88558800);
etna_set_state(ctx, VIVS_RA_CENTROID_TABLE(2), 0x88881100);
etna_set_state(ctx, VIVS_RA_CENTROID_TABLE(3), 0x33888800);
ts_msaa_config = VIVS_TS_MEM_CONFIG_MSAA | VIVS_TS_MEM_CONFIG_MSAA_FORMAT_A8R8G8B8;
} else { // No multisampling
etna_set_state(ctx, VIVS_GL_MULTI_SAMPLE_CONFIG,
ETNA_MASKED_INL(VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES, NONE) &
ETNA_MASKED(VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES, 0xf) &
ETNA_MASKED(VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12, 0x0) &
ETNA_MASKED(VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16, 0x0)
);
ts_msaa_config = 0;
}
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR);
etna_set_state(ctx, VIVS_TS_COLOR_CLEAR_VALUE, 0);
etna_set_state(ctx, VIVS_TS_COLOR_STATUS_BASE, rt_ts->address);
etna_set_state(ctx, VIVS_TS_COLOR_SURFACE_BASE, rt->address);
etna_set_state(ctx, VIVS_PE_DEPTH_CONFIG,
ETNA_MASKED_BIT(VIVS_PE_DEPTH_CONFIG_WRITE_ENABLE, 0) &
ETNA_MASKED_INL(VIVS_PE_DEPTH_CONFIG_DEPTH_FORMAT, D16) &
ETNA_MASKED_BIT(VIVS_PE_DEPTH_CONFIG_SUPER_TILED, 1) &
ETNA_MASKED_BIT(VIVS_PE_DEPTH_CONFIG_EARLY_Z, 1));
etna_set_state(ctx, VIVS_PE_DEPTH_ADDR, z->address);
etna_set_state(ctx, VIVS_PE_DEPTH_STRIDE, padded_width * 2);
etna_set_state(ctx, VIVS_PE_HDEPTH_CONTROL, VIVS_PE_HDEPTH_CONTROL_FORMAT_DISABLED);
etna_set_state_f32(ctx, VIVS_PE_DEPTH_NORMALIZE, 65535.0);
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_DEPTH);
etna_set_state(ctx, VIVS_TS_DEPTH_CLEAR_VALUE, 0xffffffff);
etna_set_state(ctx, VIVS_TS_DEPTH_STATUS_BASE, z_ts->address);
etna_set_state(ctx, VIVS_TS_DEPTH_SURFACE_BASE, z->address);
etna_set_state(ctx, VIVS_TS_MEM_CONFIG,
VIVS_TS_MEM_CONFIG_DEPTH_FAST_CLEAR |
VIVS_TS_MEM_CONFIG_COLOR_FAST_CLEAR |
VIVS_TS_MEM_CONFIG_DEPTH_16BPP |
VIVS_TS_MEM_CONFIG_DEPTH_COMPRESSION |
ts_msaa_config);
#ifdef EXTRA_DELAYS
/* Warm up RS on aux render target (is this needed?) */
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
etna_warm_up_rs(ctx, aux_rt->address, aux_rt_ts->address);
etna_set_state(ctx, VIVS_TS_COLOR_STATUS_BASE, rt_ts_physical);
etna_set_state(ctx, VIVS_TS_COLOR_SURFACE_BASE, rt_physical);
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
etna_warm_up_rs(ctx, aux_rt_physical, aux_rt_ts_physical);
etna_set_state(ctx, VIVS_TS_COLOR_STATUS_BASE, rt_ts_physical);
etna_set_state(ctx, VIVS_TS_COLOR_SURFACE_BASE, rt_physical);
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
etna_warm_up_rs(ctx, aux_rt_physical, aux_rt_ts_physical);
etna_set_state(ctx, VIVS_TS_COLOR_STATUS_BASE, rt_ts_physical);
etna_set_state(ctx, VIVS_TS_COLOR_SURFACE_BASE, rt_physical);
#endif
/* sync rasterizer to pixel engine after changes to PE config */
etna_stall(ctx, SYNC_RECIPIENT_RA, SYNC_RECIPIENT_PE);
/* Set up the resolve to clear tile status for main render target and depth
* Regard the TS as an image of width 16 with 4 bytes per pixel (64 bytes per row)
* */
etna_set_state(ctx, VIVS_RS_CONFIG,
VIVS_RS_CONFIG_SOURCE_FORMAT(RS_FORMAT_A8R8G8B8) |
VIVS_RS_CONFIG_DEST_FORMAT(RS_FORMAT_A8R8G8B8)
);
etna_set_state_multi(ctx, VIVS_RS_DITHER(0), 2, (uint32_t[]){0xffffffff, 0xffffffff});
etna_set_state(ctx, VIVS_RS_FILL_VALUE(0), 0x55555555);
etna_set_state(ctx, VIVS_RS_CLEAR_CONTROL,
VIVS_RS_CLEAR_CONTROL_MODE_ENABLED1 |
(0xffff << VIVS_RS_CLEAR_CONTROL_BITS__SHIFT));
etna_set_state(ctx, VIVS_RS_EXTRA_CONFIG, 0);
/* clear color ts */
etna_set_state(ctx, VIVS_RS_DEST_ADDR, rt_ts->address);
etna_set_state(ctx, VIVS_RS_DEST_STRIDE, 0x40);
etna_set_state(ctx, VIVS_RS_WINDOW_SIZE,
((rt_ts_size/0x40) << VIVS_RS_WINDOW_SIZE_HEIGHT__SHIFT) |
(16 << VIVS_RS_WINDOW_SIZE_WIDTH__SHIFT));
etna_set_state(ctx, VIVS_RS_KICKER, 0xbeebbeeb);
/* clear depth ts */
etna_set_state(ctx, VIVS_RS_DEST_ADDR, z_ts->address);
etna_set_state(ctx, VIVS_RS_DEST_STRIDE, 0x40);
etna_set_state(ctx, VIVS_RS_WINDOW_SIZE,
((z_ts_size/0x40) << VIVS_RS_WINDOW_SIZE_HEIGHT__SHIFT) |
(16 << VIVS_RS_WINDOW_SIZE_WIDTH__SHIFT));
etna_set_state(ctx, VIVS_RS_KICKER, 0xbeebbeeb);
/** Done */
etna_set_state(ctx, VIVS_TS_COLOR_CLEAR_VALUE, 0xff7f7f7f);
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR);
etna_set_state(ctx, VIVS_TS_COLOR_STATUS_BASE, rt_ts->address);
etna_set_state(ctx, VIVS_TS_COLOR_SURFACE_BASE, rt->address);
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
/* depth setup */
etna_set_state(ctx, VIVS_PE_DEPTH_CONFIG, ETNA_MASKED_BIT(VIVS_PE_DEPTH_CONFIG_WRITE_ENABLE, 1) &
ETNA_MASKED(VIVS_PE_DEPTH_CONFIG_DEPTH_FUNC, COMPARE_FUNC_LESS) &
ETNA_MASKED_INL(VIVS_PE_DEPTH_CONFIG_DEPTH_MODE, Z) &
ETNA_MASKED_BIT(VIVS_PE_DEPTH_CONFIG_ONLY_DEPTH, 0));
etna_set_state_f32(ctx, VIVS_PE_DEPTH_NEAR, 0.0);
etna_set_state_f32(ctx, VIVS_PE_DEPTH_FAR, 1.0);
etna_set_state_f32(ctx, VIVS_PE_DEPTH_NORMALIZE, 65535.0);
/* set up primitive assembly and setup engine */
etna_set_state_f32(ctx, VIVS_PA_VIEWPORT_OFFSET_Z, 0.0);
etna_set_state_f32(ctx, VIVS_PA_VIEWPORT_SCALE_Z, 1.0);
etna_set_state_fixp(ctx, VIVS_PA_VIEWPORT_OFFSET_X, width << 15);
etna_set_state_fixp(ctx, VIVS_PA_VIEWPORT_OFFSET_Y, height << 15);
etna_set_state_fixp(ctx, VIVS_PA_VIEWPORT_SCALE_X, width << 15);
etna_set_state_fixp(ctx, VIVS_PA_VIEWPORT_SCALE_Y, height << 15);
etna_set_state_fixp(ctx, VIVS_SE_SCISSOR_LEFT, 0);
etna_set_state_fixp(ctx, VIVS_SE_SCISSOR_TOP, 0);
etna_set_state_fixp(ctx, VIVS_SE_SCISSOR_RIGHT, (width << 16) | 5);
etna_set_state_fixp(ctx, VIVS_SE_SCISSOR_BOTTOM, (height << 16) | 5);
/* set up texture unit */
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_TEXTURE);
etna_set_state(ctx, VIVS_TE_SAMPLER_SIZE(0),
VIVS_TE_SAMPLER_SIZE_WIDTH(512)|VIVS_TE_SAMPLER_SIZE_HEIGHT(512));
etna_set_state(ctx, VIVS_TE_SAMPLER_LOG_SIZE(0),
VIVS_TE_SAMPLER_LOG_SIZE_WIDTH(9<<5) |
VIVS_TE_SAMPLER_LOG_SIZE_HEIGHT(9<<5));
etna_set_state(ctx, VIVS_TE_SAMPLER_LOD_ADDR(0,0), tex->address);
etna_set_state(ctx, VIVS_TE_SAMPLER_CONFIG0(0),
VIVS_TE_SAMPLER_CONFIG0_TYPE(TEXTURE_TYPE_2D)|
VIVS_TE_SAMPLER_CONFIG0_UWRAP(TEXTURE_WRAPMODE_CLAMP_TO_EDGE)|
VIVS_TE_SAMPLER_CONFIG0_VWRAP(TEXTURE_WRAPMODE_CLAMP_TO_EDGE)|
VIVS_TE_SAMPLER_CONFIG0_MIN(TEXTURE_FILTER_LINEAR)|
VIVS_TE_SAMPLER_CONFIG0_MIP(TEXTURE_FILTER_NONE)|
VIVS_TE_SAMPLER_CONFIG0_MAG(TEXTURE_FILTER_LINEAR)|
VIVS_TE_SAMPLER_CONFIG0_FORMAT(TEXTURE_FORMAT_X8R8G8B8));
etna_set_state(ctx, VIVS_TE_SAMPLER_LOD_CONFIG(0), 0x00000000); /* TE.SAMPLER[0].LOD_CONFIG := 0x0 */
/* shader setup */
etna_set_state(ctx, VIVS_VS_END_PC, vs_size/16);
etna_set_state_multi(ctx, VIVS_VS_INPUT_COUNT, 3, (uint32_t[]){
/* VIVS_VS_INPUT_COUNT */ VIVS_VS_INPUT_COUNT_UNK8(1) | VIVS_VS_INPUT_COUNT_COUNT(3),
/* VIVS_VS_TEMP_REGISTER_CONTROL */ VIVS_VS_TEMP_REGISTER_CONTROL_NUM_TEMPS(6),
/* VIVS_VS_OUTPUT(0) */ 0x10004});
etna_set_state(ctx, VIVS_VS_START_PC, 0x0);
etna_set_state_f32(ctx, VIVS_VS_UNIFORMS(45), 0.5); /* u11.y */
etna_set_state_f32(ctx, VIVS_VS_UNIFORMS(44), 1.0); /* u11.x */
etna_set_state_f32(ctx, VIVS_VS_UNIFORMS(27), 0.0); /* u6.w */
etna_set_state_f32(ctx, VIVS_VS_UNIFORMS(23), 20.0); /* u5.w */
etna_set_state_f32(ctx, VIVS_VS_UNIFORMS(19), 2.0); /* u4.w */
/* Now load the shader itself */
etna_set_state_multi(ctx, VIVS_VS_INST_MEM(0), vs_size/4, vs);
etna_set_state(ctx, VIVS_RA_CONTROL, 0x3);
etna_set_state_f32(ctx, VIVS_PS_UNIFORMS(0), 1.0); /* u0.x */
etna_set_state_multi(ctx, VIVS_PS_END_PC, 2, (uint32_t[]){
/* VIVS_PS_END_PC */ ps_size/16,
/* VIVS_PS_OUTPUT_REG */ 0x1});
etna_set_state(ctx, VIVS_PS_START_PC, 0x0);
etna_set_state(ctx, VIVS_PA_ATTRIBUTE_ELEMENT_COUNT, 0x200);
etna_set_state(ctx, VIVS_PA_SHADER_ATTRIBUTES(0), 0x200);
etna_set_state(ctx, VIVS_PA_SHADER_ATTRIBUTES(1), 0x200);
etna_set_state(ctx, VIVS_GL_VARYING_NUM_COMPONENTS,
VIVS_GL_VARYING_NUM_COMPONENTS_VAR0(4)| /* position */
VIVS_GL_VARYING_NUM_COMPONENTS_VAR1(2) /* texture coordinate */
);
etna_set_state_multi(ctx, VIVS_GL_VARYING_COMPONENT_USE(0), 2, (uint32_t[]){
VIVS_GL_VARYING_COMPONENT_USE_COMP0(VARYING_COMPONENT_USE_USED) |
VIVS_GL_VARYING_COMPONENT_USE_COMP1(VARYING_COMPONENT_USE_USED) |
VIVS_GL_VARYING_COMPONENT_USE_COMP2(VARYING_COMPONENT_USE_USED) |
VIVS_GL_VARYING_COMPONENT_USE_COMP3(VARYING_COMPONENT_USE_USED) |
VIVS_GL_VARYING_COMPONENT_USE_COMP4(VARYING_COMPONENT_USE_USED) |
VIVS_GL_VARYING_COMPONENT_USE_COMP5(VARYING_COMPONENT_USE_USED)
, 0
});
etna_set_state_multi(ctx, VIVS_PS_INST_MEM(0), ps_size/4, ps);
etna_set_state(ctx, VIVS_PS_INPUT_COUNT,
VIVS_PS_INPUT_COUNT_UNK8(31)| VIVS_PS_INPUT_COUNT_COUNT(3 + extra_ps_inputs));
etna_set_state(ctx, VIVS_PS_TEMP_REGISTER_CONTROL,
VIVS_PS_TEMP_REGISTER_CONTROL_NUM_TEMPS(3 + extra_ps_inputs));
etna_set_state(ctx, VIVS_PS_CONTROL, VIVS_PS_CONTROL_UNK1);
etna_set_state(ctx, VIVS_GL_VARYING_TOTAL_COMPONENTS,
VIVS_GL_VARYING_TOTAL_COMPONENTS_NUM(6)); /* 4+2=6 total varying components */
etna_set_state(ctx, VIVS_VS_LOAD_BALANCING, 0xf3f0542); /* depends on number of inputs/outputs/varyings? XXX how exactly */
etna_set_state(ctx, VIVS_VS_OUTPUT_COUNT, 3);
etna_set_state(ctx, VIVS_PA_CONFIG, ETNA_MASKED_BIT(VIVS_PA_CONFIG_POINT_SIZE_ENABLE, 0));
/* Compute transform matrices in the same way as cube egl demo */
ESMatrix modelview;
esMatrixLoadIdentity(&modelview);
esTranslate(&modelview, 0.0f, 0.0f, -9.0f);
esRotate(&modelview, 45.0f, 1.0f, 0.0f, 0.0f);
esRotate(&modelview, 45.0f, 0.0f, 1.0f, 0.0f);
esRotate(&modelview, frame*0.5f, 0.0f, 0.0f, 1.0f);
esScale(&modelview, 0.475f, 0.475f, 0.475f);
GLfloat aspect = (GLfloat)(height) / (GLfloat)(width);
ESMatrix projection;
esMatrixLoadIdentity(&projection);
esFrustum(&projection, -2.8f, +2.8f, -2.8f * aspect, +2.8f * aspect, 6.0f, 10.0f);
ESMatrix modelviewprojection;
esMatrixLoadIdentity(&modelviewprojection);
esMatrixMultiply(&modelviewprojection, &modelview, &projection);
ESMatrix inverse, normal; /* compute inverse transpose normal transformation matrix */
esMatrixInverse3x3(&inverse, &modelview);
esMatrixTranspose(&normal, &inverse);
etna_set_state_multi(ctx, VIVS_VS_UNIFORMS(0), 16, (uint32_t*)&modelviewprojection.m[0][0]);
etna_set_state_multi(ctx, VIVS_VS_UNIFORMS(16), 3, (uint32_t*)&normal.m[0][0]); /* u4.xyz */
etna_set_state_multi(ctx, VIVS_VS_UNIFORMS(20), 3, (uint32_t*)&normal.m[1][0]); /* u5.xyz */
etna_set_state_multi(ctx, VIVS_VS_UNIFORMS(24), 3, (uint32_t*)&normal.m[2][0]); /* u6.xyz */
etna_set_state_multi(ctx, VIVS_VS_UNIFORMS(28), 16, (uint32_t*)&modelview.m[0][0]);
#ifdef INDEXED
etna_set_state(ctx, VIVS_FE_INDEX_STREAM_BASE_ADDR, idx->address);
etna_set_state(ctx, VIVS_FE_INDEX_STREAM_CONTROL, VIVS_FE_INDEX_STREAM_CONTROL_TYPE_UNSIGNED_SHORT);
#endif
etna_set_state(ctx, VIVS_FE_VERTEX_STREAM_BASE_ADDR, vtx->address);
etna_set_state(ctx, VIVS_FE_VERTEX_STREAM_CONTROL,
VIVS_FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE((3 + 3 + 2)*4));
etna_set_state(ctx, VIVS_FE_VERTEX_ELEMENT_CONFIG(0),
VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_FLOAT |
(ENDIAN_MODE_NO_SWAP << VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__SHIFT) |
VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM(0) |
VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM_3 |
VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE_OFF |
VIVS_FE_VERTEX_ELEMENT_CONFIG_START(0x0) |
VIVS_FE_VERTEX_ELEMENT_CONFIG_END(0xc));
etna_set_state(ctx, VIVS_FE_VERTEX_ELEMENT_CONFIG(1),
VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_FLOAT |
(ENDIAN_MODE_NO_SWAP << VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__SHIFT) |
VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM(0) |
VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM_3 |
VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE_OFF |
VIVS_FE_VERTEX_ELEMENT_CONFIG_START(0xc) |
VIVS_FE_VERTEX_ELEMENT_CONFIG_END(0x18));
etna_set_state(ctx, VIVS_FE_VERTEX_ELEMENT_CONFIG(2),
VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_FLOAT |
(ENDIAN_MODE_NO_SWAP << VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__SHIFT) |
VIVS_FE_VERTEX_ELEMENT_CONFIG_NONCONSECUTIVE |
VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM(0) |
VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM_2 |
VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE_OFF |
VIVS_FE_VERTEX_ELEMENT_CONFIG_START(0x18) |
VIVS_FE_VERTEX_ELEMENT_CONFIG_END(0x20));
etna_set_state(ctx, VIVS_VS_INPUT(0), 0x20100);
etna_set_state(ctx, VIVS_PA_CONFIG, ETNA_MASKED_BIT(VIVS_PA_CONFIG_POINT_SPRITE_ENABLE, 0));
#ifdef INDEXED
etna_draw_indexed_primitives(ctx, PRIMITIVE_TYPE_TRIANGLES, 0, COMPANION_TRIANGLE_COUNT, 0);
#else
etna_draw_primitives(ctx, PRIMITIVE_TYPE_TRIANGLES, 0, COMPANION_TRIANGLE_COUNT);
#endif
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
#ifdef EXTRA_DELAYS
etna_flush(ctx);
#endif
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
etna_set_state(ctx, VIVS_RS_CONFIG,
VIVS_RS_CONFIG_SOURCE_FORMAT(RS_FORMAT_A8R8G8B8) |
VIVS_RS_CONFIG_SOURCE_TILED |
VIVS_RS_CONFIG_DEST_FORMAT(RS_FORMAT_A8R8G8B8) |
VIVS_RS_CONFIG_DEST_TILED);
etna_set_state(ctx, VIVS_RS_SOURCE_STRIDE, (padded_width * 4 * 4) | VIVS_RS_SOURCE_STRIDE_TILING);
etna_set_state(ctx, VIVS_RS_DEST_STRIDE, (padded_width * 4 * 4) | VIVS_RS_DEST_STRIDE_TILING);
etna_set_state(ctx, VIVS_RS_DITHER(0), 0xffffffff);
etna_set_state(ctx, VIVS_RS_DITHER(1), 0xffffffff);
etna_set_state(ctx, VIVS_RS_CLEAR_CONTROL, VIVS_RS_CLEAR_CONTROL_MODE_DISABLED);
etna_set_state(ctx, VIVS_RS_EXTRA_CONFIG, 0);
etna_set_state(ctx, VIVS_RS_SOURCE_ADDR, rt->address);
etna_set_state(ctx, VIVS_RS_DEST_ADDR, rt->address);
etna_set_state(ctx, VIVS_RS_WINDOW_SIZE,
VIVS_RS_WINDOW_SIZE_HEIGHT(padded_height) |
VIVS_RS_WINDOW_SIZE_WIDTH(padded_width));
etna_set_state(ctx, VIVS_RS_KICKER, 0xbeebbeeb);
#ifdef EXTRA_DELAYS
etna_flush(ctx);
etna_warm_up_rs(ctx, aux_rt->address, aux_rt_ts->address);
#endif
etna_set_state(ctx, VIVS_TS_COLOR_STATUS_BASE, rt_ts->address);
etna_set_state(ctx, VIVS_TS_COLOR_SURFACE_BASE, rt->address);
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR);
etna_set_state(ctx, VIVS_TS_MEM_CONFIG,
VIVS_TS_MEM_CONFIG_DEPTH_FAST_CLEAR |
VIVS_TS_MEM_CONFIG_DEPTH_16BPP |
VIVS_TS_MEM_CONFIG_DEPTH_COMPRESSION);
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR);
/* Wait for pixel engine to finish */
#ifdef EXTRA_DELAYS
etna_finish(ctx);
#else
etna_stall(ctx, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
#endif
/* Copy result to framebuffer */
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
etna_set_state(ctx, VIVS_RS_CONFIG,
VIVS_RS_CONFIG_SOURCE_FORMAT(RS_FORMAT_A8R8G8B8) |
VIVS_RS_CONFIG_SOURCE_TILED |
((supersample_x>1)?VIVS_RS_CONFIG_DOWNSAMPLE_X:0) |
((supersample_y>1)?VIVS_RS_CONFIG_DOWNSAMPLE_Y:0) |
VIVS_RS_CONFIG_DEST_FORMAT(RS_FORMAT_A8R8G8B8) |
VIVS_RS_CONFIG_SWAP_RB);
etna_set_state(ctx, VIVS_RS_SOURCE_STRIDE, (padded_width * 4 * 4) | VIVS_RS_SOURCE_STRIDE_TILING);
etna_set_state(ctx, VIVS_RS_DEST_STRIDE, fb.fb_fix.line_length);
etna_set_state(ctx, VIVS_RS_DITHER(0), 0xffffffff);
etna_set_state(ctx, VIVS_RS_DITHER(1), 0xffffffff);
etna_set_state(ctx, VIVS_RS_CLEAR_CONTROL, VIVS_RS_CLEAR_CONTROL_MODE_DISABLED);
etna_set_state(ctx, VIVS_RS_EXTRA_CONFIG, 0);
etna_set_state(ctx, VIVS_RS_SOURCE_ADDR, rt->address);
etna_set_state(ctx, VIVS_RS_DEST_ADDR, fb.physical[backbuffer]);
etna_set_state(ctx, VIVS_RS_WINDOW_SIZE,
VIVS_RS_WINDOW_SIZE_HEIGHT(height * supersample_y) |
VIVS_RS_WINDOW_SIZE_WIDTH(width * supersample_x));
etna_set_state(ctx, VIVS_RS_KICKER, 0xbeebbeeb);
etna_finish(ctx);
/* switch buffers */
fb_set_buffer(&fb, backbuffer);
backbuffer = 1-backbuffer;
}
etna_free(ctx);
viv_close();
return 0;
}
static struct pipe_sampler_view *
etna_create_sampler_view(struct pipe_context *pctx, struct pipe_resource *prsc,
const struct pipe_sampler_view *so)
{
struct etna_sampler_view *sv = CALLOC_STRUCT(etna_sampler_view);
struct etna_resource *res = etna_resource(prsc);
struct etna_context *ctx = etna_context(pctx);
const uint32_t format = translate_texture_format(so->format);
const bool ext = !!(format & EXT_FORMAT);
const uint32_t swiz = get_texture_swiz(so->format, so->swizzle_r,
so->swizzle_g, so->swizzle_b,
so->swizzle_a);
if (!sv)
return NULL;
if (!etna_resource_sampler_compatible(res)) {
/* The original resource is not compatible with the sampler.
* Allocate an appropriately tiled texture. */
if (!res->texture) {
struct pipe_resource templat = *prsc;
templat.bind &= ~(PIPE_BIND_DEPTH_STENCIL | PIPE_BIND_RENDER_TARGET |
PIPE_BIND_BLENDABLE);
res->texture =
etna_resource_alloc(pctx->screen, ETNA_LAYOUT_TILED,
DRM_FORMAT_MOD_LINEAR, &templat);
}
if (!res->texture) {
free(sv);
return NULL;
}
res = etna_resource(res->texture);
}
sv->base = *so;
pipe_reference_init(&sv->base.reference, 1);
sv->base.texture = NULL;
pipe_resource_reference(&sv->base.texture, prsc);
sv->base.context = pctx;
/* merged with sampler state */
sv->TE_SAMPLER_CONFIG0 = COND(!ext, VIVS_TE_SAMPLER_CONFIG0_FORMAT(format));
sv->TE_SAMPLER_CONFIG0_MASK = 0xffffffff;
switch (sv->base.target) {
case PIPE_TEXTURE_1D:
/* For 1D textures, we will have a height of 1, so we can use 2D
* but set T wrap to repeat */
sv->TE_SAMPLER_CONFIG0_MASK = ~VIVS_TE_SAMPLER_CONFIG0_VWRAP__MASK;
sv->TE_SAMPLER_CONFIG0 |= VIVS_TE_SAMPLER_CONFIG0_VWRAP(TEXTURE_WRAPMODE_REPEAT);
/* fallthrough */
case PIPE_TEXTURE_2D:
case PIPE_TEXTURE_RECT:
sv->TE_SAMPLER_CONFIG0 |= VIVS_TE_SAMPLER_CONFIG0_TYPE(TEXTURE_TYPE_2D);
break;
case PIPE_TEXTURE_CUBE:
sv->TE_SAMPLER_CONFIG0 |= VIVS_TE_SAMPLER_CONFIG0_TYPE(TEXTURE_TYPE_CUBE_MAP);
break;
default:
BUG("Unhandled texture target");
free(sv);
return NULL;
}
sv->TE_SAMPLER_CONFIG1 = COND(ext, VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT(format)) |
VIVS_TE_SAMPLER_CONFIG1_HALIGN(res->halign) | swiz;
sv->TE_SAMPLER_SIZE = VIVS_TE_SAMPLER_SIZE_WIDTH(res->base.width0) |
VIVS_TE_SAMPLER_SIZE_HEIGHT(res->base.height0);
sv->TE_SAMPLER_LOG_SIZE =
VIVS_TE_SAMPLER_LOG_SIZE_WIDTH(etna_log2_fixp55(res->base.width0)) |
VIVS_TE_SAMPLER_LOG_SIZE_HEIGHT(etna_log2_fixp55(res->base.height0));
/* Set up levels-of-detail */
for (int lod = 0; lod <= res->base.last_level; ++lod) {
sv->TE_SAMPLER_LOD_ADDR[lod].bo = res->bo;
sv->TE_SAMPLER_LOD_ADDR[lod].offset = res->levels[lod].offset;
sv->TE_SAMPLER_LOD_ADDR[lod].flags = ETNA_RELOC_READ;
}
sv->min_lod = sv->base.u.tex.first_level << 5;
sv->max_lod = MIN2(sv->base.u.tex.last_level, res->base.last_level) << 5;
/* Workaround for npot textures -- it appears that only CLAMP_TO_EDGE is
* supported when the appropriate capability is not set. */
if (!ctx->specs.npot_tex_any_wrap &&
(!util_is_power_of_two(res->base.width0) || !util_is_power_of_two(res->base.height0))) {
sv->TE_SAMPLER_CONFIG0_MASK = ~(VIVS_TE_SAMPLER_CONFIG0_UWRAP__MASK |
VIVS_TE_SAMPLER_CONFIG0_VWRAP__MASK);
sv->TE_SAMPLER_CONFIG0 |=
VIVS_TE_SAMPLER_CONFIG0_UWRAP(TEXTURE_WRAPMODE_CLAMP_TO_EDGE) |
VIVS_TE_SAMPLER_CONFIG0_VWRAP(TEXTURE_WRAPMODE_CLAMP_TO_EDGE);
}
return &sv->base;
}
int main(int argc, char **argv)
{
int rv;
int width = 256;
int height = 256;
int padded_width, padded_height;
fb_info fb;
rv = fb_open(0, &fb);
if(rv!=0)
{
exit(1);
}
width = fb.fb_var.xres;
height = fb.fb_var.yres;
padded_width = etna_align_up(width, 64);
padded_height = etna_align_up(height, 64);
printf("padded_width %i padded_height %i\n", padded_width, padded_height);
rv = viv_open();
if(rv!=0)
{
fprintf(stderr, "Error opening device\n");
exit(1);
}
printf("Succesfully opened device\n");
etna_ctx *ctx = 0;
if(etna_create(&ctx) != ETNA_OK)
{
printf("Unable to create context\n");
exit(1);
}
/* Initialize buffers synchronization structure */
etna_bswap_buffers *buffers = 0;
if(etna_bswap_create(ctx, &buffers, (int (*)(void *, int))&fb_set_buffer, NULL, &fb) < 0)
{
fprintf(stderr, "Error creating buffer swapper\n");
exit(1);
}
/* Allocate video memory */
etna_vidmem *rt = 0; /* main render target */
etna_vidmem *rt_ts = 0; /* tile status for main render target */
etna_vidmem *z = 0; /* depth for main render target */
etna_vidmem *z_ts = 0; /* depth ts for main render target */
etna_vidmem *vtx = 0; /* vertex buffer */
etna_vidmem *aux_rt = 0; /* auxilary render target */
etna_vidmem *aux_rt_ts = 0; /* tile status for auxilary render target */
etna_vidmem *tex = 0; /* texture */
size_t rt_size = padded_width * padded_height * 4;
size_t rt_ts_size = etna_align_up((padded_width * padded_height * 4)/0x100, 0x100);
size_t z_size = padded_width * padded_height * 2;
size_t z_ts_size = etna_align_up((padded_width * padded_height * 2)/0x100, 0x100);
dds_texture *dds = 0;
if(argc<2 || !dds_load(argv[1], &dds))
{
printf("Error loading texture\n");
exit(1);
}
if(etna_vidmem_alloc_linear(&rt, rt_size, gcvSURF_RENDER_TARGET, gcvPOOL_DEFAULT, true)!=ETNA_OK ||
etna_vidmem_alloc_linear(&rt_ts, rt_ts_size, gcvSURF_TILE_STATUS, gcvPOOL_DEFAULT, true)!=ETNA_OK ||
etna_vidmem_alloc_linear(&z, z_size, gcvSURF_DEPTH, gcvPOOL_DEFAULT, true)!=ETNA_OK ||
etna_vidmem_alloc_linear(&z_ts, z_ts_size, gcvSURF_TILE_STATUS, gcvPOOL_DEFAULT, true)!=ETNA_OK ||
etna_vidmem_alloc_linear(&vtx, VERTEX_BUFFER_SIZE, gcvSURF_VERTEX, gcvPOOL_DEFAULT, true)!=ETNA_OK ||
etna_vidmem_alloc_linear(&aux_rt, 0x4000, gcvSURF_RENDER_TARGET, gcvPOOL_SYSTEM, true)!=ETNA_OK ||
etna_vidmem_alloc_linear(&aux_rt_ts, 0x100, gcvSURF_TILE_STATUS, gcvPOOL_DEFAULT, true)!=ETNA_OK ||
etna_vidmem_alloc_linear(&tex, dds->size, gcvSURF_TEXTURE, gcvPOOL_DEFAULT, true)!=ETNA_OK
)
{
fprintf(stderr, "Error allocating video memory\n");
exit(1);
}
uint32_t tex_format = 0;
uint32_t tex_base_width = dds->slices[0][0].width;
uint32_t tex_base_height = dds->slices[0][0].height;
uint32_t tex_base_log_width = (int)(logf(tex_base_width) * RCPLOG2 * 32.0f + 0.5f);
uint32_t tex_base_log_height = (int)(logf(tex_base_height) * RCPLOG2 * 32.0f + 0.5f);
printf("Loading compressed texture (format %i, %ix%i) log_width=%i log_height=%i\n", dds->fmt, tex_base_width, tex_base_height, tex_base_log_width, tex_base_log_height);
if(dds->fmt == FMT_X8R8G8B8 || dds->fmt == FMT_A8R8G8B8)
{
for(int ix=0; ix<dds->num_mipmaps; ++ix)
{
printf("%08x: Tiling mipmap %i (%ix%i)\n", dds->slices[0][ix].offset, ix, dds->slices[0][ix].width, dds->slices[0][ix].height);
etna_texture_tile((void*)((size_t)tex->logical + dds->slices[0][ix].offset),
dds->slices[0][ix].data, dds->slices[0][ix].width, dds->slices[0][ix].height, dds->slices[0][ix].stride, 4);
}
tex_format = TEXTURE_FORMAT_X8R8G8B8;
} else if(dds->fmt == FMT_DXT1 || dds->fmt == FMT_DXT3 || dds->fmt == FMT_DXT5 || dds->fmt == FMT_ETC1)
{
printf("Uploading compressed texture\n");
memcpy(tex->logical, dds->data, dds->size);
switch(dds->fmt)
{
case FMT_DXT1: tex_format = TEXTURE_FORMAT_DXT1; break;
case FMT_DXT3: tex_format = TEXTURE_FORMAT_DXT2_DXT3; break;
case FMT_DXT5: tex_format = TEXTURE_FORMAT_DXT4_DXT5; break;
case FMT_ETC1: tex_format = TEXTURE_FORMAT_ETC1; break;
}
} else
{
printf("Unknown texture format\n");
exit(1);
}
/* Phew, now we got all the memory we need.
* Write interleaved attribute vertex stream.
* Unlike the GL example we only do this once, not every time glDrawArrays is called, the same would be accomplished
* from GL by using a vertex buffer object.
*/
for(int vert=0; vert<NUM_VERTICES; ++vert)
{
int dest_idx = vert * (3 + 3 + 2);
for(int comp=0; comp<3; ++comp)
((float*)vtx->logical)[dest_idx+comp+0] = vVertices[vert*3 + comp]; /* 0 */
for(int comp=0; comp<3; ++comp)
((float*)vtx->logical)[dest_idx+comp+3] = vNormals[vert*3 + comp]; /* 1 */
for(int comp=0; comp<2; ++comp)
((float*)vtx->logical)[dest_idx+comp+6] = vTexCoords[vert*2 + comp]; /* 2 */
}
for(int frame=0; frame<1000; ++frame)
{
if(frame%50 == 0)
printf("*** FRAME %i ****\n", frame);
/* Compute transform matrices in the same way as cube egl demo */
ESMatrix modelview, projection, modelviewprojection;
ESMatrix inverse, normal;
esMatrixLoadIdentity(&modelview);
esTranslate(&modelview, 0.0f, 0.0f, -8.0f);
esRotate(&modelview, 45.0f, 1.0f, 0.0f, 0.0f);
esRotate(&modelview, 45.0f, 0.0f, 1.0f, 0.0f);
esRotate(&modelview, frame*0.5f, 0.0f, 0.0f, 1.0f);
GLfloat aspect = (GLfloat)(height) / (GLfloat)(width);
esMatrixLoadIdentity(&projection);
esFrustum(&projection, -2.8f, +2.8f, -2.8f * aspect, +2.8f * aspect, 6.0f, 10.0f);
esMatrixLoadIdentity(&modelviewprojection);
esMatrixMultiply(&modelviewprojection, &modelview, &projection);
esMatrixInverse3x3(&inverse, &modelview);
esMatrixTranspose(&normal, &inverse);
/* XXX part of this can be put outside the loop, but until we have usable context management
* this is safest.
*/
etna_set_state(ctx, VIVS_RA_CONTROL, 0x3);
etna_set_state(ctx, VIVS_GL_MULTI_SAMPLE_CONFIG,
VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_NONE |
VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES(0xf) /*|
VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12 |
VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16 */
);
etna_set_state(ctx, VIVS_GL_VERTEX_ELEMENT_CONFIG, 0x1);
etna_set_state(ctx, VIVS_GL_VARYING_NUM_COMPONENTS,
VIVS_GL_VARYING_NUM_COMPONENTS_VAR0(4)| /* position */
VIVS_GL_VARYING_NUM_COMPONENTS_VAR1(2) /* texture coordinate */
);
etna_set_state(ctx, VIVS_GL_VARYING_TOTAL_COMPONENTS,
VIVS_GL_VARYING_TOTAL_COMPONENTS_NUM(4 + 2)
);
etna_set_state_multi(ctx, VIVS_GL_VARYING_COMPONENT_USE(0), 2, (uint32_t[]){
VIVS_GL_VARYING_COMPONENT_USE_COMP0(VARYING_COMPONENT_USE_USED) |
VIVS_GL_VARYING_COMPONENT_USE_COMP1(VARYING_COMPONENT_USE_USED) |
VIVS_GL_VARYING_COMPONENT_USE_COMP2(VARYING_COMPONENT_USE_USED) |
VIVS_GL_VARYING_COMPONENT_USE_COMP3(VARYING_COMPONENT_USE_USED) |
VIVS_GL_VARYING_COMPONENT_USE_COMP4(VARYING_COMPONENT_USE_USED) |
VIVS_GL_VARYING_COMPONENT_USE_COMP5(VARYING_COMPONENT_USE_USED)
, 0
});
etna_set_state(ctx, VIVS_PA_W_CLIP_LIMIT, 0x34000001);
etna_set_state(ctx, VIVS_PA_SYSTEM_MODE, 0x11);
etna_set_state(ctx, VIVS_PA_CONFIG, /* VIVS_PA_CONFIG_UNK22 | */
VIVS_PA_CONFIG_CULL_FACE_MODE_CCW |
VIVS_PA_CONFIG_FILL_MODE_SOLID |
VIVS_PA_CONFIG_SHADE_MODEL_SMOOTH /* |
VIVS_PA_CONFIG_POINT_SIZE_ENABLE |
VIVS_PA_CONFIG_POINT_SPRITE_ENABLE*/);
etna_set_state_f32(ctx, VIVS_PA_VIEWPORT_OFFSET_Z, 0.0);
etna_set_state_f32(ctx, VIVS_PA_VIEWPORT_SCALE_Z, 1.0);
etna_set_state_fixp(ctx, VIVS_PA_VIEWPORT_OFFSET_X, width << 15);
etna_set_state_fixp(ctx, VIVS_PA_VIEWPORT_OFFSET_Y, height << 15);
etna_set_state_fixp(ctx, VIVS_PA_VIEWPORT_SCALE_X, width << 15);
etna_set_state_fixp(ctx, VIVS_PA_VIEWPORT_SCALE_Y, height << 15);
etna_set_state(ctx, VIVS_PA_ATTRIBUTE_ELEMENT_COUNT, 0x200);
etna_set_state(ctx, VIVS_PA_SHADER_ATTRIBUTES(0), 0x200);
etna_set_state(ctx, VIVS_PA_SHADER_ATTRIBUTES(1), 0x200);
etna_set_state(ctx, VIVS_SE_CONFIG, 0x0);
etna_set_state(ctx, VIVS_SE_DEPTH_SCALE, 0x0);
etna_set_state(ctx, VIVS_SE_DEPTH_BIAS, 0x0);
etna_set_state_fixp(ctx, VIVS_SE_SCISSOR_LEFT, 0);
etna_set_state_fixp(ctx, VIVS_SE_SCISSOR_TOP, 0);
etna_set_state_fixp(ctx, VIVS_SE_SCISSOR_RIGHT, (width << 16) | 5);
etna_set_state_fixp(ctx, VIVS_SE_SCISSOR_BOTTOM, (height << 16) | 5);
etna_set_state(ctx, VIVS_PE_ALPHA_CONFIG,
/* VIVS_PE_ALPHA_CONFIG_BLEND_ENABLE_COLOR | */
/* VIVS_PE_ALPHA_CONFIG_BLEND_ENABLE_ALPHA | */
VIVS_PE_ALPHA_CONFIG_SRC_FUNC_COLOR(BLEND_FUNC_ONE) |
VIVS_PE_ALPHA_CONFIG_SRC_FUNC_ALPHA(BLEND_FUNC_ONE) |
VIVS_PE_ALPHA_CONFIG_DST_FUNC_COLOR(BLEND_FUNC_ZERO) |
VIVS_PE_ALPHA_CONFIG_DST_FUNC_ALPHA(BLEND_FUNC_ZERO) |
VIVS_PE_ALPHA_CONFIG_EQ_COLOR(BLEND_EQ_ADD) |
VIVS_PE_ALPHA_CONFIG_EQ_ALPHA(BLEND_EQ_ADD));
etna_set_state(ctx, VIVS_PE_ALPHA_BLEND_COLOR,
VIVS_PE_ALPHA_BLEND_COLOR_B(0) |
VIVS_PE_ALPHA_BLEND_COLOR_G(0) |
VIVS_PE_ALPHA_BLEND_COLOR_R(0) |
VIVS_PE_ALPHA_BLEND_COLOR_A(0));
etna_set_state(ctx, VIVS_PE_ALPHA_OP, /* VIVS_PE_ALPHA_OP_ALPHA_TEST */ 0);
etna_set_state(ctx, VIVS_PE_STENCIL_CONFIG, VIVS_PE_STENCIL_CONFIG_REF_FRONT(0) |
VIVS_PE_STENCIL_CONFIG_MASK_FRONT(0xff) |
VIVS_PE_STENCIL_CONFIG_WRITE_MASK(0xff) |
VIVS_PE_STENCIL_CONFIG_MODE_DISABLED);
etna_set_state(ctx, VIVS_PE_STENCIL_OP, VIVS_PE_STENCIL_OP_FUNC_FRONT(COMPARE_FUNC_ALWAYS) |
VIVS_PE_STENCIL_OP_FUNC_BACK(COMPARE_FUNC_ALWAYS) |
VIVS_PE_STENCIL_OP_FAIL_FRONT(STENCIL_OP_KEEP) |
VIVS_PE_STENCIL_OP_FAIL_BACK(STENCIL_OP_KEEP) |
VIVS_PE_STENCIL_OP_DEPTH_FAIL_FRONT(STENCIL_OP_KEEP) |
VIVS_PE_STENCIL_OP_DEPTH_FAIL_BACK(STENCIL_OP_KEEP) |
VIVS_PE_STENCIL_OP_PASS_FRONT(STENCIL_OP_KEEP) |
VIVS_PE_STENCIL_OP_PASS_BACK(STENCIL_OP_KEEP));
etna_set_state(ctx, VIVS_PE_COLOR_FORMAT,
VIVS_PE_COLOR_FORMAT_COMPONENTS(0xf) |
VIVS_PE_COLOR_FORMAT_FORMAT(RS_FORMAT_X8R8G8B8) |
VIVS_PE_COLOR_FORMAT_SUPER_TILED |
VIVS_PE_COLOR_FORMAT_OVERWRITE);
etna_set_state(ctx, VIVS_PE_DEPTH_CONFIG,
VIVS_PE_DEPTH_CONFIG_DEPTH_FORMAT_D16 |
VIVS_PE_DEPTH_CONFIG_SUPER_TILED |
VIVS_PE_DEPTH_CONFIG_EARLY_Z |
/* VIVS_PE_DEPTH_CONFIG_WRITE_ENABLE | */
VIVS_PE_DEPTH_CONFIG_DEPTH_FUNC(COMPARE_FUNC_ALWAYS) |
VIVS_PE_DEPTH_CONFIG_DEPTH_MODE_Z
/* VIVS_PE_DEPTH_CONFIG_ONLY_DEPTH */
);
etna_set_state(ctx, VIVS_PE_DEPTH_ADDR, z->address);
etna_set_state(ctx, VIVS_PE_DEPTH_STRIDE, padded_width * 2);
etna_set_state(ctx, VIVS_PE_HDEPTH_CONTROL, VIVS_PE_HDEPTH_CONTROL_FORMAT_DISABLED);
etna_set_state_f32(ctx, VIVS_PE_DEPTH_NORMALIZE, 65535.0);
etna_set_state(ctx, VIVS_PE_COLOR_ADDR, rt->address);
etna_set_state(ctx, VIVS_PE_COLOR_STRIDE, padded_width * 4);
etna_set_state_f32(ctx, VIVS_PE_DEPTH_NEAR, 0.0);
etna_set_state_f32(ctx, VIVS_PE_DEPTH_FAR, 1.0);
etna_set_state_f32(ctx, VIVS_PE_DEPTH_NORMALIZE, 65535.0);
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
etna_set_state(ctx, VIVS_RS_FLUSH_CACHE, VIVS_RS_FLUSH_CACHE_FLUSH);
etna_stall(ctx, SYNC_RECIPIENT_RA, SYNC_RECIPIENT_PE);
/* Set up the resolve to clear tile status for main render target
* Regard the TS plane as an image of width 16 with 4 bytes per pixel (64 bytes per row)
* XXX need to clear the depth ts too? we don't really use depth buffer in this sample
* */
etna_set_state(ctx, VIVS_TS_MEM_CONFIG, 0);
etna_set_state(ctx, VIVS_RS_CONFIG,
VIVS_RS_CONFIG_SOURCE_FORMAT(RS_FORMAT_X8R8G8B8) |
VIVS_RS_CONFIG_DEST_FORMAT(RS_FORMAT_X8R8G8B8)
);
etna_set_state_multi(ctx, VIVS_RS_DITHER(0), 2, (uint32_t[]){0xffffffff, 0xffffffff});
etna_set_state(ctx, VIVS_RS_DEST_ADDR, rt_ts->address); /* ADDR_B */
etna_set_state(ctx, VIVS_RS_DEST_STRIDE, 0x40);
etna_set_state(ctx, VIVS_RS_WINDOW_SIZE,
((rt_ts_size/0x40) << VIVS_RS_WINDOW_SIZE_HEIGHT__SHIFT) |
(16 << VIVS_RS_WINDOW_SIZE_WIDTH__SHIFT));
etna_set_state(ctx, VIVS_RS_FILL_VALUE(0), 0x55555555);
etna_set_state(ctx, VIVS_RS_CLEAR_CONTROL,
VIVS_RS_CLEAR_CONTROL_MODE_ENABLED1 |
(0xffff << VIVS_RS_CLEAR_CONTROL_BITS__SHIFT));
etna_set_state(ctx, VIVS_RS_EXTRA_CONFIG, 0);
etna_set_state(ctx, VIVS_RS_KICKER, 0xbeebbeeb);
/** Done */
/* Now set up TS */
etna_set_state(ctx, VIVS_TS_MEM_CONFIG,
VIVS_TS_MEM_CONFIG_DEPTH_FAST_CLEAR |
VIVS_TS_MEM_CONFIG_COLOR_FAST_CLEAR |
VIVS_TS_MEM_CONFIG_DEPTH_16BPP |
VIVS_TS_MEM_CONFIG_DEPTH_COMPRESSION);
etna_set_state(ctx, VIVS_TS_DEPTH_CLEAR_VALUE, 0xffffffff);
etna_set_state(ctx, VIVS_TS_DEPTH_STATUS_BASE, z_ts->address);
etna_set_state(ctx, VIVS_TS_DEPTH_SURFACE_BASE, z->address);
etna_set_state(ctx, VIVS_TS_COLOR_CLEAR_VALUE, 0xff303030);
etna_set_state(ctx, VIVS_TS_COLOR_STATUS_BASE, rt_ts->address);
etna_set_state(ctx, VIVS_TS_COLOR_SURFACE_BASE, rt->address);
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
/* set up texture unit */
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_TEXTURE);
etna_set_state(ctx, VIVS_TE_SAMPLER_SIZE(0),
VIVS_TE_SAMPLER_SIZE_WIDTH(tex_base_width)|
VIVS_TE_SAMPLER_SIZE_HEIGHT(tex_base_height));
etna_set_state(ctx, VIVS_TE_SAMPLER_LOG_SIZE(0),
VIVS_TE_SAMPLER_LOG_SIZE_WIDTH(tex_base_log_width) |
VIVS_TE_SAMPLER_LOG_SIZE_HEIGHT(tex_base_log_height));
for(int ix=0; ix<dds->num_mipmaps; ++ix)
{
etna_set_state(ctx, VIVS_TE_SAMPLER_LOD_ADDR(0,ix), tex->address + dds->slices[0][ix].offset);
}
etna_set_state(ctx, VIVS_TE_SAMPLER_CONFIG0(0),
VIVS_TE_SAMPLER_CONFIG0_TYPE(TEXTURE_TYPE_2D)|
VIVS_TE_SAMPLER_CONFIG0_UWRAP(TEXTURE_WRAPMODE_CLAMP_TO_EDGE)|
VIVS_TE_SAMPLER_CONFIG0_VWRAP(TEXTURE_WRAPMODE_CLAMP_TO_EDGE)|
VIVS_TE_SAMPLER_CONFIG0_MIN(TEXTURE_FILTER_LINEAR)|
VIVS_TE_SAMPLER_CONFIG0_MIP(TEXTURE_FILTER_LINEAR)|
VIVS_TE_SAMPLER_CONFIG0_MAG(TEXTURE_FILTER_LINEAR)|
VIVS_TE_SAMPLER_CONFIG0_FORMAT(tex_format));
etna_set_state(ctx, VIVS_TE_SAMPLER_LOD_CONFIG(0),
VIVS_TE_SAMPLER_LOD_CONFIG_MAX((dds->num_mipmaps - 1)<<5) | VIVS_TE_SAMPLER_LOD_CONFIG_MIN(0));
//etna_set_state(ctx, VIVS_TE_SAMPLER_UNK2100(0), 0);
//etna_set_state(ctx, VIVS_TE_SAMPLER_UNK2140(0), 0);
/* shader setup */
etna_set_state(ctx, VIVS_VS_START_PC, 0x0);
etna_set_state(ctx, VIVS_VS_END_PC, vs_size/16);
etna_set_state_multi(ctx, VIVS_VS_INPUT_COUNT, 3, (uint32_t[]){
/* VIVS_VS_INPUT_COUNT */ VIVS_VS_INPUT_COUNT_UNK8(1) | VIVS_VS_INPUT_COUNT_COUNT(3),
/* VIVS_VS_TEMP_REGISTER_CONTROL */ VIVS_VS_TEMP_REGISTER_CONTROL_NUM_TEMPS(6),
/* VIVS_VS_OUTPUT(0) */ VIVS_VS_OUTPUT_O0(4) |
VIVS_VS_OUTPUT_O1(0) |
VIVS_VS_OUTPUT_O2(1)});
etna_set_state_multi(ctx, VIVS_VS_INST_MEM(0), vs_size/4, vs);
etna_set_state(ctx, VIVS_VS_OUTPUT_COUNT, 3);
etna_set_state(ctx, VIVS_VS_LOAD_BALANCING, 0xf3f0542); /* depends on number of inputs/outputs/varyings? XXX how exactly */
etna_set_state_multi(ctx, VIVS_VS_UNIFORMS(0), 16, (uint32_t*)&modelviewprojection.m[0][0]);
etna_set_state_multi(ctx, VIVS_VS_UNIFORMS(16), 3, (uint32_t*)&normal.m[0][0]); /* u4.xyz */
etna_set_state_multi(ctx, VIVS_VS_UNIFORMS(20), 3, (uint32_t*)&normal.m[1][0]); /* u5.xyz */
etna_set_state_multi(ctx, VIVS_VS_UNIFORMS(24), 3, (uint32_t*)&normal.m[2][0]); /* u6.xyz */
etna_set_state_multi(ctx, VIVS_VS_UNIFORMS(28), 16, (uint32_t*)&modelview.m[0][0]);
etna_set_state_f32(ctx, VIVS_VS_UNIFORMS(19), 2.0); /* u4.w */
etna_set_state_f32(ctx, VIVS_VS_UNIFORMS(23), 20.0); /* u5.w */
etna_set_state_f32(ctx, VIVS_VS_UNIFORMS(27), 0.0); /* u6.w */
etna_set_state_f32(ctx, VIVS_VS_UNIFORMS(45), 0.5); /* u11.y */
etna_set_state_f32(ctx, VIVS_VS_UNIFORMS(44), 1.0); /* u11.x */
etna_set_state(ctx, VIVS_VS_INPUT(0), VIVS_VS_INPUT_I0(0) |
VIVS_VS_INPUT_I1(1) |
VIVS_VS_INPUT_I2(2));
etna_set_state(ctx, VIVS_PS_START_PC, 0x0);
etna_set_state_multi(ctx, VIVS_PS_END_PC, 2, (uint32_t[]){
/* VIVS_PS_END_PC */ ps_size/16,
/* VIVS_PS_OUTPUT_REG */ 0x1});
etna_set_state_multi(ctx, VIVS_PS_INST_MEM(0), ps_size/4, ps);
etna_set_state(ctx, VIVS_PS_INPUT_COUNT, VIVS_PS_INPUT_COUNT_UNK8(31) | VIVS_PS_INPUT_COUNT_COUNT(3));
etna_set_state(ctx, VIVS_PS_TEMP_REGISTER_CONTROL, VIVS_PS_TEMP_REGISTER_CONTROL_NUM_TEMPS(3));
etna_set_state(ctx, VIVS_PS_CONTROL, VIVS_PS_CONTROL_UNK1);
etna_set_state_f32(ctx, VIVS_PS_UNIFORMS(0), 1.0); /* u0.x */
etna_set_state(ctx, VIVS_FE_VERTEX_STREAM_BASE_ADDR, vtx->address); /* ADDR_E */
etna_set_state(ctx, VIVS_FE_VERTEX_STREAM_CONTROL,
VIVS_FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE((3 + 3 + 2)*4));
etna_set_state(ctx, VIVS_FE_VERTEX_ELEMENT_CONFIG(0),
VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_FLOAT |
(ENDIAN_MODE_NO_SWAP << VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__SHIFT) |
VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM(0) |
VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM(3) |
VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE_OFF |
VIVS_FE_VERTEX_ELEMENT_CONFIG_START(0x0) |
VIVS_FE_VERTEX_ELEMENT_CONFIG_END(0xc));
etna_set_state(ctx, VIVS_FE_VERTEX_ELEMENT_CONFIG(1),
VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_FLOAT |
(ENDIAN_MODE_NO_SWAP << VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__SHIFT) |
VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM(0) |
VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM(3) |
VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE_OFF |
VIVS_FE_VERTEX_ELEMENT_CONFIG_START(0xc) |
VIVS_FE_VERTEX_ELEMENT_CONFIG_END(0x18));
etna_set_state(ctx, VIVS_FE_VERTEX_ELEMENT_CONFIG(2),
VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_FLOAT |
(ENDIAN_MODE_NO_SWAP << VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__SHIFT) |
VIVS_FE_VERTEX_ELEMENT_CONFIG_NONCONSECUTIVE |
VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM(0) |
VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM(2) |
VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE_OFF |
VIVS_FE_VERTEX_ELEMENT_CONFIG_START(0x18) |
VIVS_FE_VERTEX_ELEMENT_CONFIG_END(0x20));
for(int prim=0; prim<6; ++prim)
{
etna_draw_primitives(ctx, PRIMITIVE_TYPE_TRIANGLE_STRIP, prim*4, 2);
}
#if 0
/* resolve to self */
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
etna_set_state(ctx, VIVS_RS_CONFIG,
VIVS_RS_CONFIG_SOURCE_FORMAT(RS_FORMAT_X8R8G8B8) |
VIVS_RS_CONFIG_SOURCE_TILED |
VIVS_RS_CONFIG_DEST_FORMAT(RS_FORMAT_X8R8G8B8) |
VIVS_RS_CONFIG_DEST_TILED);
etna_set_state(ctx, VIVS_RS_SOURCE_STRIDE, (padded_width * 4 * 4) | VIVS_RS_SOURCE_STRIDE_TILING);
etna_set_state(ctx, VIVS_RS_DEST_STRIDE, (padded_width * 4 * 4) | VIVS_RS_DEST_STRIDE_TILING);
etna_set_state(ctx, VIVS_RS_DITHER(0), 0xffffffff);
etna_set_state(ctx, VIVS_RS_DITHER(1), 0xffffffff);
etna_set_state(ctx, VIVS_RS_CLEAR_CONTROL, VIVS_RS_CLEAR_CONTROL_MODE_DISABLED);
etna_set_state(ctx, VIVS_RS_EXTRA_CONFIG, 0); /* no AA, no endian switch */
etna_set_state(ctx, VIVS_RS_SOURCE_ADDR, rt->address); /* ADDR_A */
etna_set_state(ctx, VIVS_RS_DEST_ADDR, rt->address); /* ADDR_A */
etna_set_state(ctx, VIVS_RS_WINDOW_SIZE,
VIVS_RS_WINDOW_SIZE_HEIGHT(padded_height) |
VIVS_RS_WINDOW_SIZE_WIDTH(padded_width));
etna_set_state(ctx, VIVS_RS_KICKER, 0xbeebbeeb);
etna_set_state(ctx, VIVS_RS_FLUSH_CACHE, VIVS_RS_FLUSH_CACHE_FLUSH);
etna_set_state(ctx, VIVS_TS_COLOR_STATUS_BASE, rt_ts->address); /* ADDR_B */
etna_set_state(ctx, VIVS_TS_COLOR_SURFACE_BASE, rt->address); /* ADDR_A */
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR);
etna_set_state(ctx, VIVS_TS_MEM_CONFIG,
VIVS_TS_MEM_CONFIG_DEPTH_FAST_CLEAR |
VIVS_TS_MEM_CONFIG_DEPTH_16BPP |
VIVS_TS_MEM_CONFIG_DEPTH_COMPRESSION);
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR);
#endif
etna_stall(ctx, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
/* copy to screen */
etna_bswap_wait_available(buffers);
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
etna_set_state(ctx, VIVS_RS_CONFIG,
VIVS_RS_CONFIG_SOURCE_FORMAT(RS_FORMAT_X8R8G8B8) |
VIVS_RS_CONFIG_SOURCE_TILED |
VIVS_RS_CONFIG_DEST_FORMAT(RS_FORMAT_X8R8G8B8) |
VIVS_RS_CONFIG_SWAP_RB);
etna_set_state(ctx, VIVS_RS_SOURCE_STRIDE, (padded_width * 4 * 4) | VIVS_RS_SOURCE_STRIDE_TILING);
etna_set_state(ctx, VIVS_RS_DEST_STRIDE, fb.fb_fix.line_length);
etna_set_state(ctx, VIVS_RS_DITHER(0), 0xffffffff);
etna_set_state(ctx, VIVS_RS_DITHER(1), 0xffffffff);
etna_set_state(ctx, VIVS_RS_CLEAR_CONTROL, VIVS_RS_CLEAR_CONTROL_MODE_DISABLED);
etna_set_state(ctx, VIVS_RS_EXTRA_CONFIG,
0); /* no AA, no endian switch */
etna_set_state(ctx, VIVS_RS_SOURCE_ADDR, rt->address); /* ADDR_A */
etna_set_state(ctx, VIVS_RS_DEST_ADDR, fb.physical[buffers->backbuffer]); /* ADDR_J */
etna_set_state(ctx, VIVS_RS_WINDOW_SIZE,
VIVS_RS_WINDOW_SIZE_HEIGHT(height) |
VIVS_RS_WINDOW_SIZE_WIDTH(width));
etna_set_state(ctx, VIVS_RS_KICKER, 0xbeebbeeb);
etna_flush(ctx);
etna_bswap_queue_swap(buffers);
}
#ifdef DUMP
bmp_dump32(fb.logical[1-backbuffer], width, height, false, "/mnt/sdcard/fb.bmp");
printf("Dump complete\n");
#endif
etna_bswap_free(buffers);
etna_free(ctx);
viv_close();
return 0;
}