static int init_fb1_first(const struct vinfo_s *vinfo) { struct osd_ctl_s osd_ctl; const struct color_bit_define_s *color; u32 reg = 0, data32 = 0; osd_ctl.index = 1; color = &default_color_format_array[31]; osd_ctl.addr = get_fb_rmem_paddr(osd_ctl.index); osd_ctl.xres = vinfo->width; osd_ctl.yres = vinfo->height; osd_ctl.xres_virtual = osd_ctl.xres; osd_ctl.yres_virtual = osd_ctl.yres; osd_ctl.disp_start_x = 0; osd_ctl.disp_end_x = osd_ctl.xres - 1; osd_ctl.disp_start_y = 0; osd_ctl.disp_end_y = osd_ctl.yres - 1; reg = osd_ctl.index == 0 ? VIU_OSD1_BLK0_CFG_W0 : VIU_OSD2_BLK0_CFG_W0; data32 = VSYNCOSD_RD_MPEG_REG(reg) & (~(0xf<<8)); data32 |= color->hw_blkmode << 8; /* osd_blk_mode */ VSYNCOSD_WR_MPEG_REG(reg, data32); pr_debug("addr is 0x%08x, xres is %d, yres is %d\n", osd_ctl.addr, osd_ctl.xres, osd_ctl.yres); osd_setup_hw(osd_ctl.index, &osd_ctl, 0, 0, osd_ctl.xres, osd_ctl.yres, osd_ctl.xres_virtual, osd_ctl.yres_virtual, osd_ctl.disp_start_x, osd_ctl.disp_start_y, osd_ctl.disp_end_x, osd_ctl.disp_end_y, osd_ctl.addr, color); return 0; }
int osd_set_prot(unsigned char x_rev, unsigned char y_rev, unsigned char bytes_per_pixel, unsigned char conv_422to444, unsigned char little_endian, unsigned int hold_lines, unsigned int x_start, unsigned int x_end, unsigned int y_start, unsigned int y_end, unsigned int y_len_m1, unsigned char y_step, unsigned char pat_start_ptr, unsigned char pat_end_ptr, unsigned long pat_val, unsigned int canv_addr, unsigned int cid_val, unsigned char cid_mode, unsigned char cugt, unsigned char req_onoff_en, unsigned int req_on_max, unsigned int req_off_min, unsigned char osd_index, unsigned char on) { unsigned long data32; if(!on){ VSYNCOSD_CLR_MPEG_REG_MASK(VPU_PROT1_MMC_CTRL,0xf<<12); //no one use prot1. VSYNCOSD_CLR_MPEG_REG_MASK(VPU_PROT1_CLK_GATE, 1<<0); if(osd_index==OSD1){ VSYNCOSD_WR_MPEG_REG_BITS (VIU_OSD1_BLK0_CFG_W0, 1, 15, 1);//switch back to little endian VSYNCOSD_WR_MPEG_REG(VIU_OSD1_PROT_CTRL,0); }else if(osd_index==OSD2){ VSYNCOSD_WR_MPEG_REG_BITS (VIU_OSD2_BLK0_CFG_W0, 1, 15, 1);//switch back to little endian VSYNCOSD_WR_MPEG_REG(VIU_OSD2_PROT_CTRL,0); } return 0; } if(osd_index==OSD1){ VSYNCOSD_WR_MPEG_REG_BITS (VPU_PROT1_MMC_CTRL, 1, 12, 4);//bit[12..15] OSD1 OSD2 OSD3 OSD4 VSYNCOSD_WR_MPEG_REG(VIU_OSD1_PROT_CTRL,1<<15|y_len_m1); VSYNCOSD_CLR_MPEG_REG_MASK(VIU_OSD1_BLK0_CFG_W0, 1<<15); //before rotate set big endian }else if(osd_index==OSD2){ VSYNCOSD_WR_MPEG_REG_BITS (VPU_PROT1_MMC_CTRL, 2, 12, 4);//bit[12..15] OSD1 OSD2 OSD3 OSD4 VSYNCOSD_WR_MPEG_REG(VIU_OSD2_PROT_CTRL,1<<15|y_len_m1); VSYNCOSD_CLR_MPEG_REG_MASK(VIU_OSD2_BLK0_CFG_W0, 1<<15); //before rotate set big endian } data32 = (x_end << 16) | (x_start << 0); VSYNCOSD_WR_MPEG_REG(VPU_PROT1_X_START_END, data32); data32 = (y_end << 16) | (y_start << 0); VSYNCOSD_WR_MPEG_REG(VPU_PROT1_Y_START_END, data32); data32 = (y_step << 16) | (y_len_m1 << 0); VSYNCOSD_WR_MPEG_REG(VPU_PROT1_Y_LEN_STEP, data32); data32 = (pat_start_ptr << 4) | (pat_end_ptr << 0); VSYNCOSD_WR_MPEG_REG(VPU_PROT1_RPT_LOOP, data32); VSYNCOSD_WR_MPEG_REG(VPU_PROT1_RPT_PAT, pat_val); data32 = (cugt << 20) | (cid_mode << 16) | (cid_val << 8) | (canv_addr << 0); VSYNCOSD_WR_MPEG_REG(VPU_PROT1_DDR, data32); data32 = (hold_lines << 8) | (little_endian << 7) | (conv_422to444 << 6) | (bytes_per_pixel << 4) | (y_rev << 3) | (x_rev << 2) | (1 << 0); // [1:0] req_en: 0=Idle; 1=Rotate mode; 2=FIFO mode. VSYNCOSD_WR_MPEG_REG(VPU_PROT1_GEN_CNTL, data32); data32 = (req_onoff_en << 31) | (req_off_min << 16) | (req_on_max << 0); VSYNCOSD_WR_MPEG_REG(VPU_PROT1_REQ_ONOFF, data32); VSYNCOSD_WR_MPEG_REG(VPU_PROT1_CLK_GATE, 1); // Enable clock return 0; }