C++ (Cpp) VS_DCS_DISABLE Examples

Example #1

File: vs.c Project: Bob4ik888/WebRadio

void vs_stopstream(void)
{
  unsigned int i, timeout;

  vs_pause();

  vs_ssi_wait(); //wait for transfer complete
  VS_DCS_DISABLE();
  VS_CS_DISABLE();

  //cancel playback
  vs_write_reg(VS_MODE, SM_SDINEW | SM_CANCEL);
  for(timeout=100; (timeout!=0) && (vs_read_reg(VS_MODE) & SM_CANCEL); timeout--)
  {
    VS_DCS_ENABLE();
    for(i=32; i!=0; i--)
    {
      vs_ssi_write(vs_bufgetc());
    }
    vs_ssi_wait();
    VS_DCS_DISABLE();
  }

  //flush buffer
  if(vs_read_reg(VS_HDAT0) || vs_read_reg(VS_HDAT1))
  {
    for(timeout=12288/32; timeout!=0; timeout--) //for FLAC 12288 otherwise 2052
    {
      VS_DCS_ENABLE();
      for(i=32; i!=0; i--)
      {
        vs_ssi_write(0x00);
      }
      vs_ssi_wait();
      VS_DCS_DISABLE();
    }
  }

  //reset
  if(vs_read_reg(VS_HDAT0) || vs_read_reg(VS_HDAT1))
  {
    vs_write_reg(VS_MODE, SM_SDINEW | SM_RESET); //soft-reset
    delay_ms(10);
    if(vs_read_reg(VS_HDAT0) || vs_read_reg(VS_HDAT1))
    {
      vs_setvolume(0); //0 -> analog power off
      vs_reset(); //hard-reset
    }
  }

  return;
}

Example #2

File: vs.c Project: Bob4ik888/WebRadio

void vs_requesthandler(void)
{
  unsigned int len, tail;

  GPIOPinIntClear(GPIO_PORTA_BASE, GPIO_PIN_1);

  len = vs_buflen();
  if(len != 0)
  {
    if(len > 16)
    {
      len = 16;
    }
    vs_ssi_writewait(); //ssi transmit fifo full?
    VS_DCS_DISABLE();
    tail = vs_buftail;
    VS_DCS_ENABLE();
    for(; len!=0; len--)
    {
      vs_ssi_write(vs_buf.b8[tail]);
      if(++tail == VS_BUFSIZE)
      {
        tail = 0;
      }
    }
    vs_buftail = tail;
  }
  else
  {
    vs_pause();
  }

  return;
}

Example #3

File: vs_module.c Project: niroren22/testFAT

void vs_reset(int unit)
{
  unsigned long i;

  //ssi speed down
  vs_ssi_wait(); //wait for transfer complete
  vs_ssi_speed(2000000); //2 MHz

  //hard reset
  VS_CS_DISABLE(unit);
  VS_DCS_DISABLE(unit);
  VS_RST_ENABLE(unit);
  delay_ms(5);
  VS_RST_DISABLE(unit);
  delay_ms(10);

  //set registers
  vs_write_reg(unit, VS_MODE, SM_SDINEW);
  //set clock multiplier and load patch - VS1033
  vs_write_reg(unit, VS_CLOCKF, 0x1800|VS1033_SC_MUL_4X);
  //Load Patch disabled
  //vs_write_plugin(vs1033d_patch, VS1033D_PATCHLEN);

  //ssi speed up
  vs_ssi_speed(0); //0 = default speed

  return;
}

Example #4

File: vs.c Project: Bob4ik888/WebRadio

void vs_data(unsigned int c)
{
  VS_DCS_ENABLE();

  vs_ssi_readwrite(c);

  VS_DCS_DISABLE();

  return;
}

Example #5

File: vs.c Project: Bob4ik888/WebRadio

void vs_reset(void)
{
  unsigned long i;

  DEBUGOUT("VS: reset\n");

  //ssi speed down
  vs_ssi_wait(); //wait for transfer complete
  vs_ssi_speed(2000000); //2 MHz

  //hard reset
  VS_CS_DISABLE();
  VS_DCS_DISABLE();
  VS_RST_ENABLE();
  delay_ms(5);
  VS_RST_DISABLE();
  delay_ms(10);

  //set registers
  vs_write_reg(VS_MODE, SM_SDINEW);

  //get VS version, set clock multiplier and load patch
  i = (vs_read_reg(VS_STATUS)&0xF0)>>4;
  if(i == 4)                                                         //VS1053
  {
    DEBUGOUT("VS: VS1053\n");
    vs_write_reg(VS_CLOCKF, 0x1800|VS1053_SC_MUL_4X);
    DEBUGOUT("VS: load VS1053B patch\n");                            //VS1053B
    vs_write_plugin(vs1053b_patch, VS1053B_PATCHLEN);
  }
  else if(i == 5)                                                    //VS1033
  {
    DEBUGOUT("VS: VS1033\n");
    vs_write_reg(VS_CLOCKF, 0x1800|VS1033_SC_MUL_4X);
    i = vs_read_ram(0x1942); //extra parameter (0x1940) -> version (0x1942)
    if(i < 3)                                                        //VS1033C
    {
      DEBUGOUT("VS: load VS1033C patch\n");
      vs_write_plugin(vs1033c_patch, VS1033C_PATCHLEN);
    }
    else                                                             //VS1033D
    {
      DEBUGOUT("VS: load VS1033D patch\n");
      vs_write_plugin(vs1033d_patch, VS1033D_PATCHLEN);
    }
  }

  //ssi speed up
  vs_ssi_speed(0); //0 = default speed

  return;
}

Example #6

File: vs.c Project: Bob4ik888/WebRadio

unsigned int vs_read_reg(unsigned int reg)
{
  unsigned int ret, timeout;

  IntMasterDisable();

  vs_ssi_wait(); //wait for transfer complete
  VS_DCS_DISABLE();
  VS_CS_ENABLE();
  vs_ssi_readwrite(VS_READ);
  vs_ssi_readwrite(reg);
  ret  = vs_ssi_readwrite(0xff)<<8;
  ret |= vs_ssi_readwrite(0xff);
  VS_CS_DISABLE();

  //execution -> DREQ low
  switch(reg)
  {
    case VS_MODE:     timeout = 20000; break;
    case VS_STATUS:   timeout =   100; break;
    case VS_BASS:     timeout =  1000; break;
    case VS_CLOCKF:   timeout = 20000; break;
    case VS_WRAM:     timeout =   100; break;
    case VS_WRAMADDR: timeout =   100; break;
    case VS_VOL:      timeout =  1000; break;
    default:          timeout =  1000; break;
  }
  for(; timeout!=0; timeout--)
  {
    if(vs_request())
    {
      break;
    }
  }

  IntMasterEnable();

  return ret;
}

Example #7

File: vs.c Project: Bob4ik888/WebRadio

void vs_write_reg(unsigned int reg, unsigned int data)
{
  unsigned int timeout;

  IntMasterDisable();

  vs_ssi_wait(); //wait for transfer complete
  VS_DCS_DISABLE();
  VS_CS_ENABLE();
  vs_ssi_readwrite(VS_WRITE);
  vs_ssi_readwrite(reg);
  vs_ssi_readwrite(data>>8);
  vs_ssi_readwrite(data);
  VS_CS_DISABLE();

  //execution -> DREQ low
  switch(reg)
  {
    case VS_MODE:     timeout = 20000; break;
    case VS_STATUS:   timeout =   100; break;
    case VS_BASS:     timeout =  1000; break;
    case VS_CLOCKF:   timeout = 20000; break;
    case VS_WRAM:     timeout =   100; break;
    case VS_WRAMADDR: timeout =   100; break;
    case VS_VOL:      timeout =  1000; break;
    default:          timeout =  1000; break;
  }
  for(; timeout!=0; timeout--)
  {
    if(vs_request())
    {
      break;
    }
  }

  IntMasterEnable();

  return;
}