/**Function************************************************************* Synopsis [Performs clock-gating for the AIG.] Description [] SideEffects [] SeeAlso [] ***********************************************************************/ void Cgt_ClockGatingRangeCheck( Cgt_Man_t * p, int iStart, int nOutputs ) { Vec_Ptr_t * vNodes = p->vFanout; Aig_Obj_t * pMiter, * pCand, * pMiterFrame, * pCandFrame, * pMiterPart, * pCandPart; int i, k, RetValue, nCalls; assert( Vec_VecSize(p->vGatesAll) == Aig_ManPoNum(p->pFrame) ); // go through all the registers inputs of this range for ( i = iStart; i < iStart + nOutputs; i++ ) { nCalls = p->nCalls; pMiter = Saig_ManLi( p->pAig, i ); Cgt_ManDetectCandidates( p->pAig, Aig_ObjFanin0(pMiter), p->pPars->nLevelMax, vNodes ); // go through the candidates of this PO Vec_PtrForEachEntry( Aig_Obj_t *, vNodes, pCand, k ) { // get the corresponding nodes from the frames pCandFrame = (Aig_Obj_t *)pCand->pData; pMiterFrame = (Aig_Obj_t *)pMiter->pData; // get the corresponding nodes from the part pCandPart = (Aig_Obj_t *)pCandFrame->pData; pMiterPart = (Aig_Obj_t *)pMiterFrame->pData; // try direct polarity if ( Cgt_SimulationFilter( p, pCandPart, pMiterPart ) ) { RetValue = Cgt_CheckImplication( p, pCandPart, pMiterPart ); if ( RetValue == 1 ) { Vec_VecPush( p->vGatesAll, i, pCand ); continue; } if ( RetValue == 0 ) Cgt_SimulationRecord( p ); } else p->nCallsFiltered++; // try reverse polarity if ( Cgt_SimulationFilter( p, Aig_Not(pCandPart), pMiterPart ) ) { RetValue = Cgt_CheckImplication( p, Aig_Not(pCandPart), pMiterPart ); if ( RetValue == 1 ) { Vec_VecPush( p->vGatesAll, i, Aig_Not(pCand) ); continue; } if ( RetValue == 0 ) Cgt_SimulationRecord( p ); } else p->nCallsFiltered++; } if ( p->pPars->fVerbose ) { // printf( "Flop %3d : Cand = %4d. Gate = %4d. SAT calls = %3d.\n", // i, Vec_PtrSize(vNodes), Vec_PtrSize(Vec_VecEntry(p->vGatesAll, i)), p->nCalls-nCalls ); } }
/**Function************************************************************* Synopsis [Derives the parameters of the best mapping/retiming for one node.] Description [] SideEffects [] SeeAlso [] ***********************************************************************/ void Seq_FpgaMappingCollectNode_rec( Abc_Obj_t * pAnd, Vec_Ptr_t * vMapping, Vec_Vec_t * vMapCuts ) { Abc_Obj_t * pFanin; Cut_Cut_t * pCutBest; int k; // skip if this is a non-PI node if ( !Abc_AigNodeIsAnd(pAnd) ) return; // skip a visited node if ( Abc_NodeIsTravIdCurrent(pAnd) ) return; Abc_NodeSetTravIdCurrent(pAnd); // visit the fanins of the node pCutBest = Seq_FpgaMappingSelectCut( pAnd ); for ( k = 0; k < (int)pCutBest->nLeaves; k++ ) { pFanin = Abc_NtkObj( pAnd->pNtk, pCutBest->pLeaves[k] >> 8 ); Seq_FpgaMappingCollectNode_rec( pFanin, vMapping, vMapCuts ); } // add this node Vec_PtrPush( vMapping, pAnd ); for ( k = 0; k < (int)pCutBest->nLeaves; k++ ) Vec_VecPush( vMapCuts, Vec_PtrSize(vMapping)-1, (void *)pCutBest->pLeaves[k] ); }
/**Function************************************************************* Synopsis [Returns the nodes by level.] Description [] SideEffects [] SeeAlso [] ***********************************************************************/ Vec_Vec_t * Ivy_ManLevelize( Ivy_Man_t * p ) { Vec_Vec_t * vNodes; Ivy_Obj_t * pObj; int i; vNodes = Vec_VecAlloc( 100 ); Ivy_ManForEachObj( p, pObj, i ) { assert( !Ivy_ObjIsBuf(pObj) ); if ( Ivy_ObjIsNode(pObj) ) Vec_VecPush( vNodes, pObj->Level, pObj ); }
Vec_Ptr_t * Dar_BalanceCone( Aig_Obj_t * pObj, Vec_Vec_t * vStore, int Level ) { Vec_Ptr_t * vNodes; assert( !Aig_IsComplement(pObj) ); assert( Aig_ObjIsNode(pObj) ); // extend the storage if ( Vec_VecSize( vStore ) <= Level ) Vec_VecPush( vStore, Level, 0 ); // get the temporary array of nodes vNodes = Vec_VecEntry( vStore, Level ); Vec_PtrClear( vNodes ); // collect the nodes in the implication supergate Dar_BalanceCone_rec( pObj, pObj, vNodes ); // remove duplicates Dar_BalanceUniqify( pObj, vNodes, Aig_ObjIsExor(pObj) ); return vNodes; }
/**Function************************************************************* Synopsis [Starts the simulation manager.] Description [] SideEffects [] SeeAlso [] ***********************************************************************/ Sym_Man_t * Sym_ManStart( Abc_Ntk_t * pNtk, int fVerbose ) { Sym_Man_t * p; int i, v; // start the manager p = ALLOC( Sym_Man_t, 1 ); memset( p, 0, sizeof(Sym_Man_t) ); p->pNtk = pNtk; p->vNodes = Abc_NtkDfs( pNtk, 0 ); p->nInputs = Abc_NtkCiNum(p->pNtk); p->nOutputs = Abc_NtkCoNum(p->pNtk); // internal simulation information p->nSimWords = SIM_NUM_WORDS(p->nInputs); p->vSim = Sim_UtilInfoAlloc( Abc_NtkObjNumMax(pNtk), p->nSimWords, 0 ); // symmetry info for each output p->vMatrSymms = Vec_PtrStart( p->nOutputs ); p->vMatrNonSymms = Vec_PtrStart( p->nOutputs ); p->vPairsTotal = Vec_IntStart( p->nOutputs ); p->vPairsSym = Vec_IntStart( p->nOutputs ); p->vPairsNonSym = Vec_IntStart( p->nOutputs ); for ( i = 0; i < p->nOutputs; i++ ) { p->vMatrSymms->pArray[i] = Extra_BitMatrixStart( p->nInputs ); p->vMatrNonSymms->pArray[i] = Extra_BitMatrixStart( p->nInputs ); } // temporary patterns p->uPatRand = ALLOC( unsigned, p->nSimWords ); p->uPatCol = ALLOC( unsigned, p->nSimWords ); p->uPatRow = ALLOC( unsigned, p->nSimWords ); p->vVarsU = Vec_IntStart( 100 ); p->vVarsV = Vec_IntStart( 100 ); // compute supports p->vSuppFun = Sim_ComputeFunSupp( pNtk, fVerbose ); p->vSupports = Vec_VecStart( p->nOutputs ); for ( i = 0; i < p->nOutputs; i++ ) for ( v = 0; v < p->nInputs; v++ ) if ( Sim_SuppFunHasVar( p->vSuppFun, i, v ) ) Vec_VecPush( p->vSupports, i, (void *)v ); return p; }
Aig_ManForEachCo( p, pObj, i ) { vSup = Vec_VecEntryInt( vSupps, i ); Vec_IntForEachEntry( vSup, Entry, k ) Vec_VecPush( vSuppsIn, Entry, (void *)(ABC_PTRUINT_T)i ); }
/**Function************************************************************* Synopsis [] Description [] SideEffects [] SeeAlso [] ***********************************************************************/ void Sat_ProofChecker( char * pFileName ) { FILE * pFile; Vec_Vec_t * vClauses; int c, i, Num, RetValue, Counter, Counter2, Clause1, Clause2; int RetValue; // open the file pFile = fopen( pFileName, "r" ); if ( pFile == NULL ) return; // count the number of clauses Counter = Counter2 = 0; while ( (c = fgetc(pFile)) != EOF ) { Counter += (c == '\n'); Counter2 += (c == '*'); } vClauses = Vec_VecStart( Counter+1 ); printf( "The proof contains %d roots and %d resolution steps.\n", Counter-Counter2, Counter2 ); // read the clauses rewind( pFile ); for ( i = 1 ; ; i++ ) { RetValue = RetValue = fscanf( pFile, "%d", &Num ); if ( RetValue != 1 ) break; assert( Num == i ); while ( (c = fgetc( pFile )) == ' ' ); if ( c == '*' ) { RetValue = fscanf( pFile, "%d %d", &Clause1, &Clause2 ); assert( RetValue == 2 ); RetValue = fscanf( pFile, "%d", &Num ); assert( RetValue == 1 ); assert( Num == 0 ); if ( !Sat_ProofResolve( vClauses, i, Clause1, Clause2 ) ) { printf( "Error detected in the resolution proof.\n" ); Vec_VecFree( vClauses ); fclose( pFile ); return; } } else { ungetc( c, pFile ); while ( 1 ) { RetValue = fscanf( pFile, "%d", &Num ); assert( RetValue == 1 ); if ( Num == 0 ) break; Vec_VecPush( vClauses, i, (void *)Num ); } RetValue = fscanf( pFile, "%d", &Num ); assert( RetValue == 1 ); assert( Num == 0 ); } } assert( i-1 == Counter ); if ( Vec_IntSize( Vec_VecEntry(vClauses, Counter) ) != 0 ) printf( "The last clause is not empty.\n" ); else printf( "The empty clause is derived.\n" ); Vec_VecFree( vClauses ); fclose( pFile ); }
ABC_NAMESPACE_IMPL_START //////////////////////////////////////////////////////////////////////// /// DECLARATIONS /// //////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////// /// FUNCTION DEFINITIONS /// //////////////////////////////////////////////////////////////////////// /**Function************************************************************* Synopsis [Starts the simulation manager.] Description [] SideEffects [] SeeAlso [] ***********************************************************************/ Sym_Man_t * Sym_ManStart( Abc_Ntk_t * pNtk, int fVerbose ) { Sym_Man_t * p; int i, v; // start the manager p = ABC_ALLOC( Sym_Man_t, 1 ); memset( p, 0, sizeof(Sym_Man_t) ); p->pNtk = pNtk; p->vNodes = Abc_NtkDfs( pNtk, 0 ); p->nInputs = Abc_NtkCiNum(p->pNtk); p->nOutputs = Abc_NtkCoNum(p->pNtk); // internal simulation information p->nSimWords = SIM_NUM_WORDS(p->nInputs); p->vSim = Sim_UtilInfoAlloc( Abc_NtkObjNumMax(pNtk), p->nSimWords, 0 ); // symmetry info for each output p->vMatrSymms = Vec_PtrStart( p->nOutputs ); p->vMatrNonSymms = Vec_PtrStart( p->nOutputs ); p->vPairsTotal = Vec_IntStart( p->nOutputs ); p->vPairsSym = Vec_IntStart( p->nOutputs ); p->vPairsNonSym = Vec_IntStart( p->nOutputs ); for ( i = 0; i < p->nOutputs; i++ ) { p->vMatrSymms->pArray[i] = Extra_BitMatrixStart( p->nInputs ); p->vMatrNonSymms->pArray[i] = Extra_BitMatrixStart( p->nInputs ); } // temporary patterns p->uPatRand = ABC_ALLOC( unsigned, p->nSimWords ); p->uPatCol = ABC_ALLOC( unsigned, p->nSimWords ); p->uPatRow = ABC_ALLOC( unsigned, p->nSimWords ); p->vVarsU = Vec_IntStart( 100 ); p->vVarsV = Vec_IntStart( 100 ); // compute supports p->vSuppFun = Sim_ComputeFunSupp( pNtk, fVerbose ); p->vSupports = Vec_VecStart( p->nOutputs ); for ( i = 0; i < p->nOutputs; i++ ) for ( v = 0; v < p->nInputs; v++ ) if ( Sim_SuppFunHasVar( p->vSuppFun, i, v ) ) Vec_VecPush( p->vSupports, i, (void *)(ABC_PTRUINT_T)v ); return p; }