static void mxc_wdt_config(void) { u16 val; val = WDOG_SEC_TO_COUNT(TIMER_MARGIN_MAX) | WCR_WDA_BIT | WCR_SRS_BIT | WCR_WDBG_BIT; __raw_writew(val, MXC_WDT_WCR); }
static void mxc_wdt_set_timeout(u32 base) { u16 val; val = __raw_readw(base + MXC_WDT_WCR); val = (val & 0x00FF) | WDOG_SEC_TO_COUNT(timer_margin); __raw_writew(val, base + MXC_WDT_WCR); val = __raw_readw(base + MXC_WDT_WCR); timer_margin = WDOG_COUNT_TO_SEC(val); }
static void imx2_wdt_set_timeout(int new_timeout) { u16 val = __raw_readw(imx2_wdt.base + IMX2_WDT_WCR); /* set the new timeout value in the WSR */ val &= ~IMX2_WDT_WCR_WT; val |= WDOG_SEC_TO_COUNT(new_timeout); __raw_writew(val, imx2_wdt.base + IMX2_WDT_WCR); }
int board_late_init(void) { #ifdef CONFIG_MXC_SPI setup_iomux_spi(); power_init(); #endif reset_phy(); #ifdef CONFIG_HW_WATCHDOG if(1){ /* NOTE: */ /* hw_watchdog_init() seems not work, use the following code */ /* which is stolen from linux kerenel to init the watchdog. */ /* hw_watchdog_reset() works fine! */ #define IMX2_WDT_WCR_WT (0xFF << 8) /* -> Watchdog Timeout Field */ #define IMX2_WDT_WCR_WRE (1 << 3) /* -> WDOG Reset Enable */ #define IMX2_WDT_WCR_WDE (1 << 2) /* -> Watchdog Enable */ #define WDOG_SEC_TO_COUNT(s) ((s * 2 - 1) << 8) u16 val = readw(WDOG1_BASE_ADDR); /* Strip the old watchdog Time-Out value */ val &= ~IMX2_WDT_WCR_WT; /* Generate reset if WDOG times out */ val &= ~IMX2_WDT_WCR_WRE; /* Keep Watchdog Disabled */ val &= ~IMX2_WDT_WCR_WDE; /* Set the watchdog's Time-Out value */ val |= WDOG_SEC_TO_COUNT(CONFIG_WATCHDOG_TIMEOUT_MSECS/1000); writew(val, WDOG1_BASE_ADDR); /* enable the watchdog */ val |= IMX2_WDT_WCR_WDE; writew(val, WDOG1_BASE_ADDR); /* According to i,MX515 Reference Manual, the PDE bit */ /* should be cleared within 16 second after boot */ /* Write to the PDE (Power Down Enable) bit */ writew(0, WDOG1_BASE_ADDR+8); #undef IMX2_WDT_WCR_WT #undef IMX2_WDT_WCR_WRE #undef IMX2_WDT_WCR_WDE #undef WDOG_SEC_TO_COUNT } #endif return 0; }
static inline void imx2_wdt_setup(void) { u16 val = __raw_readw(imx2_wdt.base + IMX2_WDT_WCR); /* Strip the old watchdog Time-Out value */ val &= ~IMX2_WDT_WCR_WT; /* Generate reset if WDOG times out */ val &= ~IMX2_WDT_WCR_WRE; /* Keep Watchdog Disabled */ val &= ~IMX2_WDT_WCR_WDE; /* Set the watchdog's Time-Out value */ val |= WDOG_SEC_TO_COUNT(imx2_wdt.timeout); __raw_writew(val, imx2_wdt.base + IMX2_WDT_WCR); /* enable the watchdog */ val |= IMX2_WDT_WCR_WDE; __raw_writew(val, imx2_wdt.base + IMX2_WDT_WCR); }