static void
auacer_setup_chan(struct auacer_softc *sc, struct auacer_chan *chan,
uint32_t start, uint32_t size, uint32_t blksize,
void (*intr)(void *), void *arg)
{
uint32_t port, slot;
uint32_t offs, val;
chan->start = start;
chan->ptr = 0;
chan->p = chan->start;
chan->end = chan->start + size;
chan->blksize = blksize;
chan->ack = 0;
chan->intr = intr;
chan->arg = arg;
auacer_add_entry(chan);
auacer_add_entry(chan);
port = chan->port;
slot = ALI_PORT2SLOT(port);
WRITE1(sc, port + ALI_OFF_CIV, 0);
WRITE1(sc, port + ALI_OFF_LVI, (chan->ptr - 1) & ALI_LVI_MASK);
offs = (char *)chan->dmalist - (char *)sc->sc_cdata;
WRITE4(sc, port + ALI_OFF_BDBAR, sc->sc_cddma + offs);
WRITE1(sc, port + ALI_OFF_CR,
ALI_CR_IOCE | ALI_CR_FEIE | ALI_CR_LVBIE | ALI_CR_RPBM);
val = READ4(sc, ALI_DMACR);
val &= ~(1 << (slot+16)); /* no pause */
val |= 1 << slot; /* start */
WRITE4(sc, ALI_DMACR, val);
}
static void
auacer_halt(struct auacer_softc *sc, struct auacer_chan *chan)
{
uint32_t val;
uint8_t port;
uint32_t slot;
port = chan->port;
DPRINTF(ALI_DEBUG_API, ("auacer_halt: port=0x%x\n", port));
chan->intr = 0;
slot = ALI_PORT2SLOT(port);
val = READ4(sc, ALI_DMACR);
val |= 1 << (slot+16); /* pause */
val &= ~(1 << slot); /* no start */
WRITE4(sc, ALI_DMACR, val);
WRITE1(sc, port + ALI_OFF_CR, 0);
while (READ1(sc, port + ALI_OFF_CR))
;
/* reset whole DMA things */
WRITE1(sc, port + ALI_OFF_CR, ALI_CR_RR);
/* clear interrupts */
WRITE1(sc, port + ALI_OFF_SR, READ1(sc, port+ALI_OFF_SR) | ALI_SR_W1TC);
WRITE4(sc, ALI_INTERRUPTSR, ALI_PORT2INTR(port));
}
static void start_dma_transfer(td243fc_rev2_softc_t *sc, jint_t ep_n,
juint32_t size)
{
td243fc_rev2_ep_t *ep = &sc->ep[ep_n];
jbool_t is_in = EP_IS_IN(ep_n);
juint32_t xybuf_size = ep->buf_size;
WRITE4(TD243FC_DMA_EP_SYSTEM_MEM_ADDR_REG((jint_t)(ep_n / 2), is_in),
ep->req ? (juint32_t)ep->req->buffer.dma_addr :
(juint32_t)sc->dma_buf.dma_addr);
if (ep->req)
xybuf_size = MIN(xybuf_size, ep->req->buffer.buffer_size);
else
xybuf_size = MIN(xybuf_size, sc->dma_buf.buffer_size);
TOGGLE_IF_SET(TD243FC_XFILLED_STATUS_REG, TD243FC_EP_BIT_INDEX(ep_n));
TOGGLE_IF_SET(TD243FC_YFILLED_STATUS_REG, TD243FC_EP_BIT_INDEX(ep_n));
TOGGLE_IF_SET(TD243FC_XBUF_INT_STATUS_REG, TD243FC_EP_BIT_INDEX(ep_n));
TOGGLE_IF_SET(TD243FC_YBUF_INT_STATUS_REG, TD243FC_EP_BIT_INDEX(ep_n));
WRITE4(TD243FC_EPN_PACKET_CONTROL_REG((jint_t)(ep_n / 2), is_in),
BFSET4(TD243FC_BUFFERSIZE, xybuf_size - 1) |
BFSET4(TD243FC_TTLBTECNT, size));
SET4(TD243FC_DMA_EP_ENABLE_REG, TD243FC_EP_BIT_INDEX(ep_n));
if (sc->add_to_list)
sc->ep_ready |= TD243FC_EP_BIT_INDEX(ep_n);
else
WRITE4(TD243FC_EP_READY_REG, TD243FC_EP_BIT_INDEX(ep_n));
}
static int
spi_attach(device_t dev)
{
struct spi_softc *sc;
uint32_t reg;
sc = device_get_softc(dev);
if (bus_alloc_resources(dev, spi_spec, sc->res)) {
device_printf(dev, "could not allocate resources\n");
return (ENXIO);
}
/* Memory interface */
sc->bst = rman_get_bustag(sc->res[0]);
sc->bsh = rman_get_bushandle(sc->res[0]);
reg = READ4(sc, SPI_MCR);
reg |= MCR_MSTR;
reg &= ~(MCR_CONT_SCKE | MCR_MDIS | MCR_FRZ);
reg &= ~(MCR_PCSIS_M << MCR_PCSIS_S);
reg |= (MCR_PCSIS_M << MCR_PCSIS_S); /* PCS Active low */
reg |= (MCR_CLR_TXF | MCR_CLR_RXF);
WRITE4(sc, SPI_MCR, reg);
reg = READ4(sc, SPI_RSER);
reg |= RSER_EOQF_RE;
WRITE4(sc, SPI_RSER, reg);
reg = READ4(sc, SPI_MCR);
reg &= ~MCR_HALT;
WRITE4(sc, SPI_MCR, reg);
reg = READ4(sc, SPI_CTAR0);
reg &= ~(CTAR_FMSZ_M << CTAR_FMSZ_S);
reg |= (CTAR_FMSZ_8 << CTAR_FMSZ_S);
/*
* TODO: calculate BR
* SCK baud rate = ( fsys / PBR ) * (1 + DBR) / BR
*
* reg &= ~(CTAR_BR_M << CTAR_BR_S);
*/
reg &= ~CTAR_CPOL; /* Polarity */
reg |= CTAR_CPHA;
/*
* Set LSB (Less significant bit first)
* must be used for some applications, e.g. some LCDs
*/
reg |= CTAR_LSBFE;
WRITE4(sc, SPI_CTAR0, reg);
reg = READ4(sc, SPI_CTAR0);
reg &= ~(CTAR_PBR_M << CTAR_PBR_S);
reg |= (CTAR_PBR_7 << CTAR_PBR_S);
WRITE4(sc, SPI_CTAR0, reg);
device_add_child(dev, "spibus", 0);
return (bus_generic_attach(dev));
}
static int
mtk_pic_attach(device_t dev)
{
struct mtk_pic_softc *sc;
intptr_t xref = pic_xref(dev);
sc = device_get_softc(dev);
if (bus_alloc_resources(dev, mtk_pic_spec, sc->pic_res)) {
device_printf(dev, "could not allocate resources\n");
return (ENXIO);
}
sc->pic_dev = dev;
/* Initialize mutex */
mtx_init(&sc->mutex, "PIC lock", "", MTX_SPIN);
/* Set the number of interrupts */
sc->nirqs = nitems(sc->pic_irqs);
/* Mask all interrupts */
WRITE4(sc, MTK_INTDIS, 0xFFFFFFFF);
/* But enable interrupt generation/masking */
WRITE4(sc, MTK_INTENA, 0x00000000);
/* Set all interrupts to type 0 */
WRITE4(sc, MTK_INTTYPE, 0xFFFFFFFF);
/* Register the interrupts */
if (mtk_pic_register_isrcs(sc) != 0) {
device_printf(dev, "could not register PIC ISRCs\n");
goto cleanup;
}
/*
* Now, when everything is initialized, it's right time to
* register interrupt controller to interrupt framefork.
*/
if (intr_pic_register(dev, xref) == NULL) {
device_printf(dev, "could not register PIC\n");
goto cleanup;
}
if (bus_setup_intr(dev, sc->pic_res[1], INTR_TYPE_CLK,
mtk_pic_intr, NULL, sc, &sc->pic_intrhand)) {
device_printf(dev, "could not setup irq handler\n");
intr_pic_deregister(dev, xref);
goto cleanup;
}
return (0);
cleanup:
bus_release_resources(dev, mtk_pic_spec, sc->pic_res);
return(ENXIO);
}
static int
pio_configure(device_t dev, int dir, int mask)
{
struct pio_softc *sc;
sc = device_get_softc(dev);
WRITE4(sc, PIO_INT_MASK, mask);
WRITE4(sc, PIO_DIR, dir);
return (0);
}
void
omgpio_pin_write(void *arg, int pin, int value)
{
struct omgpio_softc *sc = arg;
if (value)
WRITE4(sc, sc->sc_regs.setdataout,
1 << GPIO_PIN_TO_OFFSET(pin));
else
WRITE4(sc, sc->sc_regs.cleardataout,
1 << GPIO_PIN_TO_OFFSET(pin));
}
static int
fimd_init(struct fimd_softc *sc)
{
struct panel_info *panel;
int reg;
panel = sc->panel;
/* fb_init */
reg = panel->ivclk | panel->fixvclk;
DWRITE4(sc,VIDCON1,reg);
reg = (VIDCON0_ENVID | VIDCON0_ENVID_F);
reg |= (panel->clkval_f << CLKVAL_F_OFFSET);
WRITE4(sc,VIDCON0,reg);
reg = (panel->v_pulse_width << VSYNC_PULSE_WIDTH_OFFSET);
reg |= (panel->v_front_porch << V_FRONT_PORCH_OFFSET);
reg |= (panel->v_back_porch << V_BACK_PORCH_OFFSET);
DWRITE4(sc,VIDTCON0,reg);
reg = (panel->h_pulse_width << HSYNC_PULSE_WIDTH_OFFSET);
reg |= (panel->h_front_porch << H_FRONT_PORCH_OFFSET);
reg |= (panel->h_back_porch << H_BACK_PORCH_OFFSET);
DWRITE4(sc,VIDTCON1,reg);
reg = ((panel->width - 1) << HOZVAL_OFFSET);
reg |= ((panel->height - 1) << LINEVAL_OFFSET);
DWRITE4(sc,VIDTCON2,reg);
reg = sc->sc_info.fb_pbase;
WRITE4(sc, VIDW00ADD0B0, reg);
reg += (sc->sc_info.fb_stride * (sc->sc_info.fb_height + 1));
WRITE4(sc, VIDW00ADD1B0, reg);
WRITE4(sc, VIDW00ADD2, sc->sc_info.fb_stride);
reg = ((panel->width - 1) << OSD_RIGHTBOTX_F_OFFSET);
reg |= ((panel->height - 1) << OSD_RIGHTBOTY_F_OFFSET);
WRITE4(sc,VIDOSD0B,reg);
reg = panel->width * panel->height;
WRITE4(sc,VIDOSD0C,reg);
reg = READ4(sc, SHADOWCON);
reg |= CHANNEL0_EN;
reg &= ~(1 << 5); /* disable local path for channel0 */
WRITE4(sc,SHADOWCON,reg);
reg = BPPMODE_F_RGB_16BIT_565 << BPPMODE_F_OFFSET;
reg |= ENWIN_F_ENABLE | HALF_WORD_SWAP_EN; /* Note: swap=0 when ENLOCAL==1 */
reg &= ~ENLOCAL_F; /* use DMA */
WRITE4(sc,WINCON0,reg);
/* Enable DisplayPort Clk */
WRITE4(sc, DPCLKCON, DPCLKCON_EN);
return (0);
}
static int
dma_setup(struct edma_softc *sc, struct tcd_conf *tcd)
{
struct edma_channel *ch;
int chnum;
int reg;
chnum = tcd->channel;
ch = &edma_map[chnum];
ch->ih = tcd->ih;
ch->ih_user = tcd->ih_user;
TCD_WRITE4(sc, DMA_TCDn_SADDR(chnum), tcd->saddr);
TCD_WRITE4(sc, DMA_TCDn_DADDR(chnum), tcd->daddr);
reg = (tcd->smod << TCD_ATTR_SMOD_SHIFT);
reg |= (tcd->dmod << TCD_ATTR_DMOD_SHIFT);
reg |= (tcd->ssize << TCD_ATTR_SSIZE_SHIFT);
reg |= (tcd->dsize << TCD_ATTR_DSIZE_SHIFT);
TCD_WRITE2(sc, DMA_TCDn_ATTR(chnum), reg);
TCD_WRITE2(sc, DMA_TCDn_SOFF(chnum), tcd->soff);
TCD_WRITE2(sc, DMA_TCDn_DOFF(chnum), tcd->doff);
TCD_WRITE4(sc, DMA_TCDn_SLAST(chnum), tcd->slast);
TCD_WRITE4(sc, DMA_TCDn_DLASTSGA(chnum), tcd->dlast_sga);
TCD_WRITE4(sc, DMA_TCDn_NBYTES_MLOFFYES(chnum), tcd->nbytes);
reg = tcd->nmajor; /* Current Major Iteration Count */
TCD_WRITE2(sc, DMA_TCDn_CITER_ELINKNO(chnum), reg);
TCD_WRITE2(sc, DMA_TCDn_BITER_ELINKNO(chnum), reg);
reg = (TCD_CSR_INTMAJOR);
if(tcd->majorelink == 1) {
reg |= TCD_CSR_MAJORELINK;
reg |= (tcd->majorelinkch << TCD_CSR_MAJORELINKCH_SHIFT);
}
TCD_WRITE2(sc, DMA_TCDn_CSR(chnum), reg);
/* Enable requests */
reg = READ4(sc, DMA_ERQ);
reg |= (0x1 << chnum);
WRITE4(sc, DMA_ERQ, reg);
/* Enable error interrupts */
reg = READ4(sc, DMA_EEI);
reg |= (0x1 << chnum);
WRITE4(sc, DMA_EEI, reg);
return (0);
}
static int
pio_set(device_t dev, int bit, int enable)
{
struct pio_softc *sc;
sc = device_get_softc(dev);
if (enable)
WRITE4(sc, PIO_OUTSET, bit);
else
WRITE4(sc, PIO_OUTCLR, bit);
return (0);
}
static dcd_hw_init(td243fc_rev2_softc_t *sc)
{
WRITE4(TD243FC_RESET_CONTROL_REG,
TD243FC_RESET_FUNCTION_SIE | TD243FC_RESET_FUNCTION_CONTROLLER);
/* force USB core work as device bit1:0 = 10b, and XCVR mode
* bit 7:6 = 11b */
WRITE4(TD243FC_HARDWARE_MODE_REG, BFSET4(TD243FC_HF, TD243FC_DEVICE) |
BFSET4(TD243FC_OTGXCVR, TD243FC_SE_SE) |
BFSET4(TD243FC_HOSTXCVR, TD243FC_SE_SE));
/* Enable function controller clock */
SET4(TD243FC_CLOCK_CONTROL_REG, TD243FC_FCCLK);
}
void
omgpio_intr_unmask(struct omgpio_softc *sc, unsigned int gpio)
{
struct omgpio_softc *sc = omgpio_cd.cd_devs[GPIO_PIN_TO_INST(gpio)];
WRITE4(sc, sc->sc_regs.irqstatus_set0, 1 << GPIO_PIN_TO_OFFSET(gpio));
}
/* Disable an endpoint */
static jresult_t dcd_disable_ep(jdevice_t dev, pipe_desc_t *pipe)
{
td243fc_rev2_softc_t *sc = (td243fc_rev2_softc_t *)j_device_get_softc(dev);
jint_t ep_n = (jint_t)(pipe->dcd_handle);
td243fc_rev2_ep_t *ep = NULL;
jbool_t is_in = FALSE;
KASSERT(pipe, ("Pipe is NULL\n"));
KASSERT(pipe->dcd_handle, ("Pipe was not allocated\n"));
/* HSU Addition */
ep = &sc->ep[ep_n];
/* First set value in ep, only then try to ASSERT on ep->pipe */
KASSERT(ep->pipe, ("Pipe was not enabled\n"));
/* End of HSU Addition */
is_in = EP_IS_IN(ep_n);
DBG_I(DSLAVE_DCD, ("DCD: dcd_disable_ep pipe=%p, buf_size=%d\n", pipe,
ep->buf_size));
WRITE4(TD243FC_EPN_CONFIG_CONTROL_REG(ep_n/2, is_in), 0);
pipe->status = PIPE_DISABLED;
td243fc_mem_free(sc, ep->buf_size * 2);
ep->pipe = NULL;
return 0;
}
static int
pad_pin_set(device_t dev, uint32_t pin, unsigned int value)
{
struct pad_softc *sc;
struct gpio_bank bank;
int pin_shift;
int reg;
int i;
sc = device_get_softc(dev);
for (i = 0; i < sc->gpio_npins; i++) {
if (sc->gpio_pins[i].gp_pin == pin)
break;
}
if (i >= sc->gpio_npins)
return (EINVAL);
if (get_bank(sc, pin, &bank, &pin_shift) != 0)
return (EINVAL);
GPIO_LOCK(sc);
reg = READ4(sc, bank.port, bank.con + 0x4);
reg &= ~(PIN_OUT << pin_shift);
if (value)
reg |= (PIN_OUT << pin_shift);
WRITE4(sc, bank.port, bank.con + 0x4, reg);
GPIO_UNLOCK(sc);
return (0);
}
static int
audmux_configure(struct audmux_softc *sc,
int ssi_port, int audmux_port)
{
uint32_t reg;
/* Direction: output */
reg = (PTCR_TFS_DIR | PTCR_TCLKDIR | PTCR_SYN);
WRITE4(sc, AUDMUX_PTCR(audmux_port), reg);
/* Select source */
reg = (PDCR_RXDSEL_PORT(ssi_port) << PDCR_RXDSEL_S);
WRITE4(sc, AUDMUX_PDCR(audmux_port), reg);
return (0);
}
static int
msgdma_reset(struct msgdma_softc *sc)
{
int timeout;
dprintf("%s: read status: %x\n", __func__, READ4(sc, 0x00));
dprintf("%s: read control: %x\n", __func__, READ4(sc, 0x04));
dprintf("%s: read 1: %x\n", __func__, READ4(sc, 0x08));
dprintf("%s: read 2: %x\n", __func__, READ4(sc, 0x0C));
WRITE4(sc, DMA_CONTROL, CONTROL_RESET);
timeout = 100;
do {
if ((READ4(sc, DMA_STATUS) & STATUS_RESETTING) == 0)
break;
} while (timeout--);
dprintf("timeout %d\n", timeout);
if (timeout == 0)
return (-1);
dprintf("%s: read control after reset: %x\n",
__func__, READ4(sc, DMA_CONTROL));
return (0);
}
static void cancel_active_request(td243fc_rev2_softc_t *sc, jint_t ep_num)
{
request_t *req = sc->ep[ep_num].req;
if (!req)
return;
req->status = REQUEST_CANCELLED;
/* ABORT DMA TRANSFER */
WRITE4(TD243FC_DMA_EP_CHANNEL_CLEAR_REG, TD243FC_EP_BIT_INDEX(ep_num));
/* unset the ep */
WRITE4(TD243FC_EP_READY_CLEAR_REG, TD243FC_EP_BIT_INDEX(ep_num));
req_finish(sc, ep_num, req, REQUEST_CANCELLED);
}
static int
ccm_attach(device_t dev)
{
struct ccm_softc *sc;
int reg;
int i;
sc = device_get_softc(dev);
sc->dev = dev;
if (bus_alloc_resources(dev, ccm_spec, sc->res)) {
device_printf(dev, "could not allocate resources\n");
return (ENXIO);
}
/* Memory interface */
sc->bst = rman_get_bustag(sc->res[0]);
sc->bsh = rman_get_bushandle(sc->res[0]);
/* Enable oscillator */
reg = READ4(sc, CCM_CCR);
reg |= (FIRC_EN | FXOSC_EN);
WRITE4(sc, CCM_CCR, reg);
/* Wait 10 times */
for (i = 0; i < 10; i++) {
if (READ4(sc, CCM_CSR) & FXOSC_RDY) {
device_printf(sc->dev, "On board oscillator is ready.\n");
break;
}
cpufunc_nullop();
}
/* Clock is on during all modes, except stop mode. */
for (i = 0; i < CCM_CCGRN; i++) {
WRITE4(sc, CCM_CCGR(i), 0xffffffff);
}
/* Enable ENET clocks */
reg = READ4(sc, CCM_CSCDR1);
reg |= (ENET_TS_EN | RMII_CLK_EN);
WRITE4(sc, CCM_CSCDR1, reg);
return (0);
}
static void
set_control_reg(struct beri_softc *sc, int dir, control_reg_t *c)
{
uint32_t offset;
uint16_t src[4];
uint16_t *cp;
int i;
cp = (uint16_t *)c;
for (i = 0; i < 4; i++)
src[3 - i] = cp[i];
offset = dir ? sc->control_write : sc->control_read;
WRITE4(sc, offset + 0, ((uint32_t *)src)[0]);
WRITE4(sc, offset + 4, ((uint32_t *)src)[1]);
}
static int
adc_attach(device_t dev)
{
struct adc_softc *sc;
int err;
int reg;
sc = device_get_softc(dev);
if (bus_alloc_resources(dev, adc_spec, sc->res)) {
device_printf(dev, "could not allocate resources\n");
return (ENXIO);
}
/* Memory interface */
sc->bst = rman_get_bustag(sc->res[0]);
sc->bsh = rman_get_bushandle(sc->res[0]);
adc_sc = sc;
/* Setup interrupt handler */
err = bus_setup_intr(dev, sc->res[1], INTR_TYPE_BIO | INTR_MPSAFE,
NULL, adc_intr, sc, &sc->ih);
if (err) {
device_printf(dev, "Unable to alloc interrupt resource.\n");
return (ENXIO);
}
/* Configure 12-bit mode */
reg = READ4(sc, ADC_CFG);
reg &= ~(CFG_MODE_M << CFG_MODE_S);
reg |= (CFG_MODE_12 << CFG_MODE_S); /* 12bit */
WRITE4(sc, ADC_CFG, reg);
/* Configure for continuous conversion */
reg = READ4(sc, ADC_GC);
reg |= (GC_ADCO | GC_AVGE);
WRITE4(sc, ADC_GC, reg);
/* Disable interrupts */
reg = READ4(sc, ADC_HC0);
reg &= HC_AIEN;
WRITE4(sc, ADC_HC0, reg);
return (0);
}
/* Trigger REMOTE-WAKEUP event */
static jresult_t dcd_wake_the_host(jdevice_t dev)
{
td243fc_rev2_softc_t *sc = (td243fc_rev2_softc_t *)j_device_get_softc(dev);
WRITE4(TD243FC_COMMAND_REG, TD243FC_RSMINPROG);
return 0;
}
static int
auacer_set_params(void *v, int setmode, int usemode,
audio_params_t *play, audio_params_t *rec, stream_filter_list_t *pfil,
stream_filter_list_t *rfil)
{
struct auacer_softc *sc;
struct audio_params *p;
stream_filter_list_t *fil;
uint32_t control;
int mode, index;
DPRINTF(ALI_DEBUG_API, ("auacer_set_params\n"));
sc = v;
for (mode = AUMODE_RECORD; mode != -1;
mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) {
if ((setmode & mode) == 0)
continue;
p = mode == AUMODE_PLAY ? play : rec;
if (p == NULL)
continue;
if ((p->sample_rate != 8000) &&
(p->sample_rate != 11025) &&
(p->sample_rate != 12000) &&
(p->sample_rate != 16000) &&
(p->sample_rate != 22050) &&
(p->sample_rate != 24000) &&
(p->sample_rate != 32000) &&
(p->sample_rate != 44100) &&
(p->sample_rate != 48000))
return (EINVAL);
fil = mode == AUMODE_PLAY ? pfil : rfil;
index = auconv_set_converter(sc->sc_formats, AUACER_NFORMATS,
mode, p, TRUE, fil);
if (index < 0)
return EINVAL;
if (fil->req_size > 0)
p = &fil->filters[0].param;
/* p points HW encoding */
if (sc->sc_formats[index].frequency_type != 1
&& auacer_set_rate(sc, mode, p->sample_rate))
return EINVAL;
if (mode == AUMODE_PLAY) {
control = READ4(sc, ALI_SCR);
control &= ~ALI_SCR_PCM_246_MASK;
if (p->channels == 4)
control |= ALI_SCR_PCM_4;
else if (p->channels == 6)
control |= ALI_SCR_PCM_6;
WRITE4(sc, ALI_SCR, control);
}
}
return (0);
}
static int
dwc3_init(struct exynos_xhci_softc *esc)
{
int hwparams1;
int rev;
int reg;
rev = READ4(esc, GSNPSID);
if ((rev & GSNPSID_MASK) != 0x55330000) {
printf("It is not DWC3 controller\n");
return (-1);
}
/* Reset controller */
WRITE4(esc, GCTL, GCTL_CORESOFTRESET);
WRITE4(esc, GUSB3PIPECTL(0), GUSB3PIPECTL_PHYSOFTRST);
WRITE4(esc, GUSB2PHYCFG(0), GUSB2PHYCFG_PHYSOFTRST);
DELAY(100000);
reg = READ4(esc, GUSB3PIPECTL(0));
reg &= ~(GUSB3PIPECTL_PHYSOFTRST);
WRITE4(esc, GUSB3PIPECTL(0), reg);
reg = READ4(esc, GUSB2PHYCFG(0));
reg &= ~(GUSB2PHYCFG_PHYSOFTRST);
WRITE4(esc, GUSB2PHYCFG(0), reg);
reg = READ4(esc, GCTL);
reg &= ~GCTL_CORESOFTRESET;
WRITE4(esc, GCTL, reg);
hwparams1 = READ4(esc, GHWPARAMS1);
reg = READ4(esc, GCTL);
reg &= ~(GCTL_SCALEDOWN_MASK << GCTL_SCALEDOWN_SHIFT);
reg &= ~(GCTL_DISSCRAMBLE);
if (GHWPARAMS1_EN_PWROPT(hwparams1) == \
GHWPARAMS1_EN_PWROPT_CLK)
reg &= ~(GCTL_DSBLCLKGTNG);
if ((rev & REVISION_MASK) < 0x190a)
reg |= (GCTL_U2RSTECN);
WRITE4(esc, GCTL, reg);
/* Set host mode */
reg = READ4(esc, GCTL);
reg &= ~(GCTL_PRTCAPDIR(GCTL_PRTCAP_OTG));
reg |= GCTL_PRTCAPDIR(GCTL_PRTCAP_HOST);
WRITE4(esc, GCTL, reg);
return (0);
}
static int
spi_txrx(struct spi_softc *sc, uint8_t *out_buf,
uint8_t *in_buf, int bufsz, int cs)
{
uint32_t reg, wreg;
uint32_t txcnt;
uint32_t i;
txcnt = 0;
for (i = 0; i < bufsz; i++) {
txcnt++;
wreg = out_buf[i];
wreg |= PUSHR_CONT;
wreg |= (cs << PUSHR_PCS_S);
if (i == 0)
wreg |= PUSHR_CTCNT;
if (i == (bufsz - 1) || txcnt == SPI_FIFO_SIZE)
wreg |= PUSHR_EOQ;
WRITE4(sc, SPI_PUSHR, wreg);
if (i == (bufsz - 1) || txcnt == SPI_FIFO_SIZE) {
txcnt = 0;
/* Wait last entry in a queue to be transmitted */
while((READ4(sc, SPI_SR) & SR_EOQF) == 0)
continue;
reg = READ4(sc, SPI_SR);
reg |= (SR_TCF | SR_EOQF);
WRITE4(sc, SPI_SR, reg);
}
/* Wait until RX FIFO is empty */
while((READ4(sc, SPI_SR) & SR_RFDF) == 0)
continue;
in_buf[i] = READ1(sc, SPI_POPR);
}
return (0);
}
int
src_swreset(void)
{
if (src_sc == NULL)
return (1);
WRITE4(src_sc, SRC_SCR, SW_RST);
return (0);
}
static int
dma_stop(struct edma_softc *sc, int chnum)
{
int reg;
reg = READ4(sc, DMA_ERQ);
reg &= ~(0x1 << chnum);
WRITE4(sc, DMA_ERQ, reg);
return (0);
}
static void
pad_pin_configure(struct pad_softc *sc, struct gpio_pin *pin,
unsigned int flags)
{
struct gpio_bank bank;
int pin_shift;
int reg;
GPIO_LOCK(sc);
/*
* Manage input/output
*/
if (flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) {
pin->gp_flags &= ~(GPIO_PIN_INPUT|GPIO_PIN_OUTPUT);
if (get_bank(sc, pin->gp_pin, &bank, &pin_shift) != 0)
return;
pin_shift *= 4;
#if 0
printf("bank is 0x%08x pin_shift %d\n", bank.con, pin_shift);
#endif
if (flags & GPIO_PIN_OUTPUT) {
pin->gp_flags |= GPIO_PIN_OUTPUT;
reg = READ4(sc, bank.port, bank.con);
reg &= ~(0xf << pin_shift);
reg |= (PIN_OUT << pin_shift);
WRITE4(sc, bank.port, bank.con, reg);
} else {
pin->gp_flags |= GPIO_PIN_INPUT;
reg = READ4(sc, bank.port, bank.con);
reg &= ~(0xf << pin_shift);
WRITE4(sc, bank.port, bank.con, reg);
}
}
GPIO_UNLOCK(sc);
}
static void
auacer_reset(struct auacer_softc *sc)
{
WRITE4(sc, ALI_SCR, ALI_SCR_RESET);
WRITE4(sc, ALI_FIFOCR1, 0x83838383);
WRITE4(sc, ALI_FIFOCR2, 0x83838383);
WRITE4(sc, ALI_FIFOCR3, 0x83838383);
WRITE4(sc, ALI_INTERFACECR, ALI_IF_PO); /* XXX pcm out only */
WRITE4(sc, ALI_INTERRUPTCR, 0x00000000);
WRITE4(sc, ALI_INTERRUPTSR, 0x00000000);
}
static void start_zero_packet(td243fc_rev2_softc_t *sc, jint_t ep_n)
{
if (EP_IS_IN(ep_n))
{
TOGGLE_IF_NOT_SET(TD243FC_XFILLED_STATUS_REG,
TD243FC_EP_BIT_INDEX(ep_n));
}
if (sc->add_to_list)
sc->ep_ready |= TD243FC_EP_BIT_INDEX(ep_n);
else
WRITE4(TD243FC_EP_READY_REG, TD243FC_EP_BIT_INDEX(ep_n));
}
static int
pinmux_set(struct iomuxc_softc *sc)
{
phandle_t child, parent, root;
pcell_t iomux_config[MAX_MUX_LEN];
int len;
int values;
int pin;
int pin_cfg;
int i;
root = OF_finddevice("/");
len = 0;
parent = root;
/* Find 'iomux_config' prop in the nodes */
for (child = OF_child(parent); child != 0; child = OF_peer(child)) {
/* Find a 'leaf'. Start the search from this node. */
while (OF_child(child)) {
parent = child;
child = OF_child(child);
}
if (!fdt_is_enabled(child))
continue;
if ((len = OF_getproplen(child, "iomux_config")) > 0) {
OF_getprop(child, "iomux_config", &iomux_config, len);
values = len / (sizeof(uint32_t));
for (i = 0; i < values; i += 2) {
pin = fdt32_to_cpu(iomux_config[i]);
pin_cfg = fdt32_to_cpu(iomux_config[i+1]);
#if 0
device_printf(sc->dev, "Set pin %d to 0x%08x\n",
pin, pin_cfg);
#endif
WRITE4(sc, IOMUXC(pin), pin_cfg);
}
}
if (OF_peer(child) == 0) {
/* No more siblings. */
child = parent;
parent = OF_parent(child);
}
}
return (0);
}
