/*as use the spin_lock,
*1--there is no sleep,
*2--it is better to shorter the time,
*/
int am656in_isr(struct tvin_frontend_s *fe, unsigned int hcnt)
{
unsigned int ccir656_status = 0;
struct am656in_dev_s *devp = container_of(fe, am656in_dev_t, frontend);
ccir656_status = READ_CBUS_REG(BT_STATUS);
if(ccir656_status & 0xf0) //AFIFO OVERFLOW
devp->overflow_cnt++;
if(devp->overflow_cnt > 5)
{
devp->overflow_cnt = 0;
if(devp->para.port == TVIN_PORT_BT656) //NTSC or PAL input(interlace mode): D0~D7(with SAV + EAV )
reinit_bt656in_dec(devp);
else if(devp->para.port == TVIN_PORT_BT601)
reinit_bt601in_dec(devp);
else //if(am656in_dec_info.para.port == TVIN_PORT_CAMERA)
reinit_camera_dec(devp);
WRITE_CBUS_REG(BT_STATUS, ccir656_status | (1 << 9)); //WRITE_CBUS_REGite 1 to clean the SOF interrupt bit
printk("[bt656..] %s bt656in fifo overflow. \n",__func__);
}
return 0;
}
int eth_clk_set(int selectclk,unsigned long clk_freq,unsigned long out_clk)
{
int n;
if(((clk_freq)%out_clk)!=0)
{
printf("ERROR:source clk must n times of out_clk ,source clk=%d\n",out_clk,clk_freq);
return -1;
}
else
{
n=(int)((clk_freq)/out_clk);
}
WRITE_CBUS_REG(HHI_ETH_CLK_CNTL,
(n-1)<<0 |
selectclk<<9 |
1<<8//enable clk
);
udelay(100);
return 0;
}
static void __init meson_clockevent_init(void)
{
CLEAR_CBUS_REG_MASK(ISA_TIMER_MUX, TIMER_A_INPUT_MASK | TIMER_C_INPUT_MASK);
SET_CBUS_REG_MASK(ISA_TIMER_MUX,
(TIMER_UNIT_1us << TIMER_A_INPUT_BIT) |
(TIMER_UNIT_1us << TIMER_C_INPUT_BIT));
WRITE_CBUS_REG(ISA_TIMERA, 9999);
clockevent_meson_1mhz.mult =
div_sc(1000000, NSEC_PER_SEC, clockevent_meson_1mhz.shift);
clockevent_meson_1mhz.max_delta_ns =
clockevent_delta2ns(0xfffe, &clockevent_meson_1mhz);
clockevent_meson_1mhz.min_delta_ns =
clockevent_delta2ns(1, &clockevent_meson_1mhz);
clockevent_meson_1mhz.cpumask = cpumask_of(0);
clockevents_register_device(&clockevent_meson_1mhz);
/* Set up the IRQ handler */
setup_irq(INT_TIMER_A, &meson_timer_irq);
setup_irq(INT_TIMER_C, &meson_timer_irq);
}
static void __init meson_clocksource_init(void)
{
CLEAR_CBUS_REG_MASK(ISA_TIMER_MUX, TIMER_E_INPUT_MASK);
SET_CBUS_REG_MASK(ISA_TIMER_MUX, TIMERE_UNIT_1ms << TIMER_E_INPUT_BIT);
WRITE_CBUS_REG(ISA_TIMERE, 0);
clocksource_timer_e.shift = clocksource_hz2shift(24, 1000);
clocksource_timer_e.mult =
clocksource_khz2mult(1, clocksource_timer_e.shift);
clocksource_timer_f.shift = clocksource_timer_e.shift;
//clocksource_timer_f.mult = ((clocksource_timer_e.mult)>>6)*64;
clocksource_timer_f.mult = ((clocksource_timer_e.mult)>>6)*40;
/*printk("Timer-E=%x,%x, Timer-F=%x,%x",
clocksource_timer_e.shift,
clocksource_timer_e.mult,
clocksource_timer_f.shift,
clocksource_timer_f.mult
);*/
clocksource_register(&clocksource_timer_e);
clocksource_register(&clocksource_timer_f);
}
void hdmirx_set_pinmux(void)
{
WRITE_CBUS_REG(PERIPHS_PIN_MUX_0 , READ_CBUS_REG(PERIPHS_PIN_MUX_0 )|
( (1 << 27) | // pm_gpioW_0_hdmirx_5V_A
(1 << 26) | // pm_gpioW_1_hdmirx_HPD_A
(1 << 25) | // pm_gpioW_2_hdmirx_scl_A
(1 << 24) | // pm_gpioW_3_hdmirx_sda_A
(1 << 23) | // pm_gpioW_4_hdmirx_5V_B
(1 << 22) | // pm_gpioW_5_hdmirx_HPD_B
(1 << 21) | // pm_gpioW_6_hdmirx_scl_B
(1 << 20) | // pm_gpioW_7_hdmirx_sda_B
(1 << 19) | // pm_gpioW_8_hdmirx_5V_C
(1 << 18) | // pm_gpioW_9_hdmirx_HPD_C
(1 << 17) | // pm_gpioW_10_hdmirx_scl_C
(1 << 16) | // pm_gpioW_11_hdmirx_sda_C
(1 << 15) | // pm_gpioW_12_hdmirx_5V_D
(1 << 14) | // pm_gpioW_13_hdmirx_HPD_D
(1 << 13) | // pm_gpioW_14_hdmirx_scl_D
(1 << 12) | // pm_gpioW_15_hdmirx_sda_D
(1 << 11))); // pm_gpioW_16_hdmirx_cec
#ifdef USE_GPIO_FOR_HPD
if (pwr_gpio_pull_down)
WRITE_CBUS_REG(PAD_PULL_UP_REG2, READ_CBUS_REG(PAD_PULL_UP_REG2) |
((1<<0)|(1<<4)|(1<<8)|(1<<12)));
WRITE_CBUS_REG(PERIPHS_PIN_MUX_0, READ_CBUS_REG(PERIPHS_PIN_MUX_0 ) &
(~((1<<26)|(1<<22)|(1<<18)|(1<<14))));
WRITE_CBUS_REG(PREG_PAD_GPIO5_EN_N, READ_CBUS_REG(PREG_PAD_GPIO5_EN_N) &
(~((1<<1)|(1<<5)|(1<<9)|(1<<13))));
WRITE_CBUS_REG(PREG_PAD_GPIO5_O, READ_CBUS_REG(PREG_PAD_GPIO5_O) |
((1<<1)|(1<<5)|(1<<9)|(1<<13)));
#endif
#if 0
WRITE_CBUS_REG(PERIPHS_PIN_MUX_1 , READ_CBUS_REG(PERIPHS_PIN_MUX_1 )|
( (1 << 2) | // pm_gpioW_17_hdmirx_tmds_clk
(1 << 1) | // pm_gpioW_18_hdmirx_pix_clk
(1 << 0))); // pm_gpioW_19_hdmirx_audmeas
#endif
}
void am_set_regmap(unsigned int cnt, struct am_reg_s *p)
{
unsigned short i;
unsigned int temp = 0;
for (i=0; i<cnt; i++) {
switch (p->type)
{
case REG_TYPE_PHY:
#ifdef PQ_DEBUG_EN
pr_info("%s: bus type: phy..............\n", __func__);
#endif
break;
case REG_TYPE_CBUS:
if (p->mask == 0xffffffff)
WRITE_CBUS_REG(p->addr, p->val);
else
WRITE_CBUS_REG(p->addr, (READ_CBUS_REG(p->addr) & (~p->mask)) | (p->val & p->mask));
#ifdef PQ_DEBUG_EN
pr_info("%s: cbus: Reg0x%x = 0x%x...............\n", __func__, p->addr, (p->val & p->mask));
#endif
break;
case REG_TYPE_APB:
if (p->mask == 0xffffffff)
WRITE_APB_REG(p->addr, p->val);
else
WRITE_APB_REG(p->addr, (READ_APB_REG(p->addr) & (~p->mask)) | (p->val & p->mask));
#ifdef PQ_DEBUG_EN
pr_info("%s: apb bus: Reg0x%x = 0x%x...............\n", __func__, p->addr, (p->val & p->mask));
#endif
break;
case REG_TYPE_MPEG:
if (p->mask == 0xffffffff)
WRITE_MPEG_REG(p->addr, p->val);
else
WRITE_MPEG_REG(p->addr, (READ_MPEG_REG(p->addr) & (~p->mask)) | (p->val & p->mask));
#ifdef PQ_DEBUG_EN
pr_info("%s: mpeg: Reg0x%x = 0x%x...............\n", __func__, p->addr, (p->val & p->mask));
#endif
break;
case REG_TYPE_AXI:
if (p->mask == 0xffffffff)
WRITE_AXI_REG(p->addr, p->val);
else
WRITE_AXI_REG(p->addr, (READ_AXI_REG(p->addr) & (~p->mask)) | (p->val & p->mask));
#ifdef PQ_DEBUG_EN
pr_info("%s: axi: Reg0x%x = 0x%x...............\n", __func__, p->addr, (p->val & p->mask));
#endif
break;
case REG_TYPE_AHB:
if (p->mask == 0xffffffff)
WRITE_AHB_REG(p->addr, p->val);
else
WRITE_AHB_REG(p->addr, (READ_AHB_REG(p->addr) & (~p->mask)) | (p->val & p->mask));
#ifdef PQ_DEBUG_EN
pr_info("%s: ahb: Reg0x%x = 0x%x...............\n", __func__, p->addr, (p->val & p->mask));
#endif
break;
case REG_TYPE_INDEX_VPPCHROMA:
WRITE_CBUS_REG(VPP_CHROMA_ADDR_PORT, p->addr);
if (p->mask == 0xffffffff)
{
WRITE_CBUS_REG(VPP_CHROMA_DATA_PORT, p->val);
}
else
{
temp = READ_CBUS_REG(VPP_CHROMA_DATA_PORT);
WRITE_CBUS_REG(VPP_CHROMA_ADDR_PORT, p->addr);
WRITE_CBUS_REG(VPP_CHROMA_DATA_PORT, (temp & (~p->mask)) | (p->val & p->mask));
}
#ifdef PQ_DEBUG_EN
pr_info("%s: vppchroma: 0x1d70:port0x%x = 0x%x...............\n", __func__, p->addr, (p->val & p->mask));
#endif
break;
case REG_TYPE_INDEX_GAMMA:
#ifdef PQ_DEBUG_EN
pr_info("%s: bus type: REG_TYPE_INDEX_GAMMA..............\n", __func__);
#endif
break;
case VALUE_TYPE_CONTRAST_BRIGHTNESS:
#ifdef PQ_DEBUG_EN
pr_info("%s: bus type: VALUE_TYPE_CONTRAST_BRIGHTNESS..............\n", __func__);
#endif
break;
case REG_TYPE_INDEX_VPP_COEF:
if (((p->addr&0xf) == 0)||((p->addr&0xf) == 0x8))
{
WRITE_CBUS_REG(VPP_CHROMA_ADDR_PORT, p->addr);
WRITE_CBUS_REG(VPP_CHROMA_DATA_PORT, p->val);
}
else
{
WRITE_CBUS_REG(VPP_CHROMA_DATA_PORT, p->val);
}
#ifdef PQ_DEBUG_EN
pr_info("%s: vppcoef: 0x1d70:port0x%x = 0x%x...............\n", __func__, p->addr, (p->val & p->mask));
#endif
break;
default:
pr_info("%s: bus type error!!!bustype = 0x%x................\n", __func__, p->type);
break;
}
p++;
}
return;
}
void am_set_regmap(struct am_regs_s *p)
{
unsigned short i;
unsigned int temp = 0;
for (i=0; i<p->length; i++) {
switch (p->am_reg[i].type)
{
case REG_TYPE_PHY:
#ifdef PQ_DEBUG_EN
pr_info("%s: bus type: phy..............\n", __func__);
#endif
break;
case REG_TYPE_CBUS:
if (p->am_reg[i].mask == 0xffffffff)
WRITE_CBUS_REG(p->am_reg[i].addr, p->am_reg[i].val);
else
WRITE_CBUS_REG(p->am_reg[i].addr, (READ_CBUS_REG(p->am_reg[i].addr) & (~(p->am_reg[i].mask))) | (p->am_reg[i].val & p->am_reg[i].mask));
#ifdef PQ_DEBUG_EN
pr_info("%s: cbus: Reg0x%x(%u)=0x%x(%u)val=%x(%u)mask=%x(%u)\n", __func__, p->am_reg[i].addr,p->am_reg[i].addr,
(p->am_reg[i].val & p->am_reg[i].mask),(p->am_reg[i].val & p->am_reg[i].mask),
p->am_reg[i].val,p->am_reg[i].val,p->am_reg[i].mask,p->am_reg[i].mask);
#endif
break;
case REG_TYPE_APB:
if (p->am_reg[i].mask == 0xffffffff)
WRITE_APB_REG(p->am_reg[i].addr, p->am_reg[i].val);
else
WRITE_APB_REG(p->am_reg[i].addr, (READ_APB_REG(p->am_reg[i].addr) & (~(p->am_reg[i].mask))) | (p->am_reg[i].val & p->am_reg[i].mask));
#ifdef PQ_DEBUG_EN
pr_info("%s: apb: Reg0x%x(%u)=0x%x(%u)val=%x(%u)mask=%x(%u)\n", __func__, p->am_reg[i].addr,p->am_reg[i].addr,
(p->am_reg[i].val & p->am_reg[i].mask),(p->am_reg[i].val & p->am_reg[i].mask),
p->am_reg[i].val,p->am_reg[i].val,p->am_reg[i].mask,p->am_reg[i].mask);
#endif
break;
case REG_TYPE_MPEG:
if (p->am_reg[i].mask == 0xffffffff)
WRITE_MPEG_REG(p->am_reg[i].addr, p->am_reg[i].val);
else
WRITE_MPEG_REG(p->am_reg[i].addr, (READ_MPEG_REG(p->am_reg[i].addr) & (~(p->am_reg[i].mask))) | (p->am_reg[i].val & p->am_reg[i].mask));
#ifdef PQ_DEBUG_EN
pr_info("%s: mpeg: Reg0x%x(%u)=0x%x(%u)val=%x(%u)mask=%x(%u)\n", __func__, p->am_reg[i].addr,p->am_reg[i].addr,
(p->am_reg[i].val & p->am_reg[i].mask),(p->am_reg[i].val & p->am_reg[i].mask),
p->am_reg[i].val,p->am_reg[i].val,p->am_reg[i].mask,p->am_reg[i].mask);
#endif
break;
case REG_TYPE_AXI:
if (p->am_reg[i].mask == 0xffffffff)
WRITE_AXI_REG(p->am_reg[i].addr, p->am_reg[i].val);
else
WRITE_AXI_REG(p->am_reg[i].addr, (READ_AXI_REG(p->am_reg[i].addr) & (~(p->am_reg[i].mask))) | (p->am_reg[i].val & p->am_reg[i].mask));
#ifdef PQ_DEBUG_EN
pr_info("%s: axi: Reg0x%x(%u)=0x%x(%u)val=%x(%u)mask=%x(%u)\n", __func__, p->am_reg[i].addr,p->am_reg[i].addr,
(p->am_reg[i].val & p->am_reg[i].mask),(p->am_reg[i].val & p->am_reg[i].mask),
p->am_reg[i].val,p->am_reg[i].val,p->am_reg[i].mask,p->am_reg[i].mask);
#endif
break;
case REG_TYPE_AHB:
if (p->am_reg[i].mask == 0xffffffff)
WRITE_AHB_REG(p->am_reg[i].addr, p->am_reg[i].val);
else
WRITE_AHB_REG(p->am_reg[i].addr, (READ_AHB_REG(p->am_reg[i].addr) & (~(p->am_reg[i].mask))) | (p->am_reg[i].val & p->am_reg[i].mask));
#ifdef PQ_DEBUG_EN
pr_info("%s: ahb: Reg0x%x(%u)=0x%x(%u)val=%x(%u)mask=%x(%u)\n", __func__, p->am_reg[i].addr,p->am_reg[i].addr,
(p->am_reg[i].val & p->am_reg[i].mask),(p->am_reg[i].val & p->am_reg[i].mask),
p->am_reg[i].val,p->am_reg[i].val,p->am_reg[i].mask,p->am_reg[i].mask);
#endif
break;
case REG_TYPE_INDEX_VPPCHROMA:
WRITE_CBUS_REG(VPP_CHROMA_ADDR_PORT, p->am_reg[i].addr);
if (p->am_reg[i].mask == 0xffffffff)
{
WRITE_CBUS_REG(VPP_CHROMA_DATA_PORT, p->am_reg[i].val);
}
else
{
temp = READ_CBUS_REG(VPP_CHROMA_DATA_PORT);
WRITE_CBUS_REG(VPP_CHROMA_ADDR_PORT, p->am_reg[i].addr);
WRITE_CBUS_REG(VPP_CHROMA_DATA_PORT, (temp & (~(p->am_reg[i].mask))) | (p->am_reg[i].val & p->am_reg[i].mask));
}
#ifdef PQ_DEBUG_EN
pr_info("%s: chroma: Reg0x%x(%u)=0x%x(%u)val=%x(%u)mask=%x(%u)\n", __func__, p->am_reg[i].addr,p->am_reg[i].addr,
(p->am_reg[i].val & p->am_reg[i].mask),(p->am_reg[i].val & p->am_reg[i].mask),
p->am_reg[i].val,p->am_reg[i].val,p->am_reg[i].mask,p->am_reg[i].mask);
#endif
break;
case REG_TYPE_INDEX_GAMMA:
#ifdef PQ_DEBUG_EN
pr_info("%s: bus type: REG_TYPE_INDEX_GAMMA..............\n", __func__);
#endif
break;
case VALUE_TYPE_CONTRAST_BRIGHTNESS:
#ifdef PQ_DEBUG_EN
pr_info("%s: bus type: VALUE_TYPE_CONTRAST_BRIGHTNESS..............\n", __func__);
#endif
break;
case REG_TYPE_INDEX_VPP_COEF:
if (((p->am_reg[i].addr&0xf) == 0)||((p->am_reg[i].addr&0xf) == 0x8))
{
WRITE_CBUS_REG(VPP_CHROMA_ADDR_PORT, p->am_reg[i].addr);
WRITE_CBUS_REG(VPP_CHROMA_DATA_PORT, p->am_reg[i].val);
}
else
{
WRITE_CBUS_REG(VPP_CHROMA_DATA_PORT, p->am_reg[i].val);
}
#ifdef PQ_DEBUG_EN
pr_info("%s: coef: Reg0x%x(%u)=0x%x(%u)val=%x(%u)mask=%x(%u)\n", __func__, p->am_reg[i].addr,p->am_reg[i].addr,
(p->am_reg[i].val & p->am_reg[i].mask),(p->am_reg[i].val & p->am_reg[i].mask),
p->am_reg[i].val,p->am_reg[i].val,p->am_reg[i].mask,p->am_reg[i].mask);
#endif
break;
default:
#ifdef PQ_DEBUG_EN
pr_info("%s: bus type error!!!bustype = 0x%x................\n", __func__, p->am_reg[i].type);
#endif
break;
}
}
return;
}
static unsigned int inner_cs_input_level()
{
unsigned int level = 0;
unsigned int cs_no = 0;
//pin64 LED_CS0
CLEAR_CBUS_REG_MASK(PERIPHS_PIN_MUX_0, (3<<21));
// Enable VBG_EN
WRITE_CBUS_REG_BITS(PREG_AM_ANALOG_ADDR, 1, 0, 1);
// pin mux
// wire pm_gpioA_7_led_pwm = pin_mux_reg0[22];
WRITE_CBUS_REG(LED_PWM_REG0, 0);
WRITE_CBUS_REG(LED_PWM_REG1, 0);
WRITE_CBUS_REG(LED_PWM_REG2, 0);
WRITE_CBUS_REG(LED_PWM_REG3, 0);
WRITE_CBUS_REG(LED_PWM_REG4, 0);
WRITE_CBUS_REG(LED_PWM_REG0, (0 << 31) | // disable the overall circuit
(0 << 30) | // 1:Closed Loop 0:Open Loop
(PWM_TCNT << 16) | // PWM total count
(0 << 13) | // Enable
(1 << 12) | // enable
(0 << 10) | // test
(7 << 7) | // CS0 REF, Voltage FeedBack: about 0.505V
(7 << 4) | // CS1 REF, Current FeedBack: about 0.505V
(0 << 0) // DIMCTL Analog dimmer
);
WRITE_CBUS_REG(LED_PWM_REG1, (1 << 30) | // enable high frequency clock
(PWM_MAX_VAL << 16) | // MAX PWM value
(0 << 0) // MIN PWM value
);
WRITE_CBUS_REG(LED_PWM_REG2, (0 << 31) | // disable timeout test mode
(0 << 30) | // timeout based on the comparator output
(0 << 16) | // timeout = 10uS
(0 << 13) | // Select oscillator as the clock (just for grins)
(1 << 11) | // 1:Enable OverCurrent Portection 0:Disable
(3 << 8) | // Filter: shift every 3 ticks
(0 << 6) | // Filter: count 1uS ticks
(0 << 5) | // PWM polarity : negative
(0 << 4) | // comparator: negative, Different with NikeD3
(1 << 0) // +/- 1
);
WRITE_CBUS_REG(LED_PWM_REG3, ( 1 << 16) | // Feedback down-sampling = PWM_freq/1 = PWM_freq
( 1 << 14) | // enable to re-write MATCH_VAL
( 210 << 0) // preset PWM_duty = 50%
);
WRITE_CBUS_REG(LED_PWM_REG4, ( 0 << 30) | // 1:Digital Dimmer 0:Analog Dimmer
( 2 << 28) | // dimmer_timebase = 1uS
(1000 << 14) | // Digital dimmer_duty = 0%, the most darkness
(1000 << 0) // dimmer_freq = 1KHz
);
cs_no = READ_CBUS_REG(LED_PWM_REG3);
if(cs_no &(1<<14))
level |= (1<<0);
if(cs_no &(1<<15))
level |= (1<<4);
WRITE_CBUS_REG(VGHL_PWM_REG0, 0);
WRITE_CBUS_REG(VGHL_PWM_REG1, 0);
WRITE_CBUS_REG(VGHL_PWM_REG2, 0);
WRITE_CBUS_REG(VGHL_PWM_REG3, 0);
WRITE_CBUS_REG(VGHL_PWM_REG4, 0);
WRITE_CBUS_REG(VGHL_PWM_REG0, (0 << 31) | // disable the overall circuit
(0 << 30) | // 1:Closed Loop 0:Open Loop
(PWM_TCNT << 16) | // PWM total count
(0 << 13) | // Enable
(1 << 12) | // enable
(0 << 10) | // test
(7 << 7) | // CS0 REF, Voltage FeedBack: about 0.505V
(7 << 4) | // CS1 REF, Current FeedBack: about 0.505V
(0 << 0) // DIMCTL Analog dimmer
);
WRITE_CBUS_REG(VGHL_PWM_REG1, (1 << 30) | // enable high frequency clock
(PWM_MAX_VAL << 16) | // MAX PWM value
(0 << 0) // MIN PWM value
);
WRITE_CBUS_REG(VGHL_PWM_REG2, (0 << 31) | // disable timeout test mode
(0 << 30) | // timeout based on the comparator output
(0 << 16) | // timeout = 10uS
(0 << 13) | // Select oscillator as the clock (just for grins)
(1 << 11) | // 1:Enable OverCurrent Portection 0:Disable
(3 << 8) | // Filter: shift every 3 ticks
(0 << 6) | // Filter: count 1uS ticks
(0 << 5) | // PWM polarity : negative
(0 << 4) | // comparator: negative, Different with NikeD3
(1 << 0) // +/- 1
);
WRITE_CBUS_REG (VGHL_PWM_REG3, ( 1 << 16) | // Feedback down-sampling = PWM_freq/1 = PWM_freq
( 1 << 14) | // enable to re-write MATCH_VAL
( 210 << 0) // preset PWM_duty = 50%
);
WRITE_CBUS_REG(VGHL_PWM_REG4, ( 0 << 30) | // 1:Digital Dimmer 0:Analog Dimmer
( 2 << 28) | // dimmer_timebase = 1uS
(1000 << 14) | // Digital dimmer_duty = 0%, the most darkness
(1000 << 0) // dimmer_freq = 1KHz
);
cs_no = READ_CBUS_REG(VGHL_PWM_REG3);
if(cs_no &(1<<14))
level |= (1<<8);
if(cs_no &(1<<15))
level |= (1<<12);
return level;
}
void power_on_backlight(void)
{
if(ver == 2)
{
clear_mio_mux(2, 1<<17);
clear_mio_mux(4, 1<<12);
clear_mio_mux(3, 1<<3);
clear_mio_mux(7, 1<<20);
clear_mio_mux(10, 1<<6);
set_gpio_val(GPIOX_bank_bit32_63(53), GPIOX_bit_bit32_63(53), 0);
set_gpio_mode(GPIOX_bank_bit32_63(53), GPIOX_bit_bit32_63(53), 0);
}
else
{
clear_mio_mux(10, 1<<13);
clear_mio_mux(4, 1<<5);
clear_mio_mux(0, 1<<1);
set_gpio_val(GPIOB_bank_bit0_8(6), GPIOB_bit_bit0_8(6), 1);
set_gpio_mode(GPIOB_bank_bit0_8(6), GPIOB_bit_bit0_8(6), GPIO_OUTPUT_MODE);
}
//Init Analog pwm pinmux
CLEAR_CBUS_REG_MASK(PERIPHS_PIN_MUX_4, (1<<11));
CLEAR_CBUS_REG_MASK(PERIPHS_PIN_MUX_3, 1);
CLEAR_CBUS_REG_MASK(PERIPHS_PIN_MUX_3, (1<<1));
CLEAR_CBUS_REG_MASK(PERIPHS_PIN_MUX_7, (1<<18));
CLEAR_CBUS_REG_MASK(PERIPHS_PIN_MUX_10, (1<<6));
SET_CBUS_REG_MASK(PERIPHS_PIN_MUX_1, (1<<24));
WRITE_CBUS_REG(PWM_MISC_REG_AB, 0x2);
WRITE_CBUS_REG(PWM_PWM_B, 0);
//Init Digital pwm pinmux, tcon GPIOB2, GPIOB3,GPIOB4
SET_CBUS_REG_MASK(PERIPHS_PIN_MUX_0, (1<<4)|(1<<5)|(1<<3));
WRITE_CBUS_REG_BITS(TCON_MISC_SEL_ADDR, 1, OEH_SEL, 1);
WRITE_CBUS_REG(OEH_HS_ADDR, TCON_PWM_HS1);
WRITE_CBUS_REG(OEH_HE_ADDR, TCON_PWM_HE1);
WRITE_CBUS_REG(OEH_VS_ADDR, TCON_PWM_VS1);
WRITE_CBUS_REG(OEH_VE_ADDR, TCON_PWM_VS2);//180HZ
WRITE_CBUS_REG_BITS(TCON_MISC_SEL_ADDR, 1, CPV1_SEL, 1);
WRITE_CBUS_REG(CPV1_HS_ADDR, TCON_PWM_HS2);
WRITE_CBUS_REG(CPV1_HE_ADDR, TCON_PWM_HE2);
WRITE_CBUS_REG(CPV1_VS_ADDR, TCON_PWM_VS2);
WRITE_CBUS_REG(CPV1_VE_ADDR, TCON_PWM_VS2+TCON_PWM_VS2);
WRITE_CBUS_REG_BITS(TCON_MISC_SEL_ADDR, 1, OEV2_SEL, 1);
WRITE_CBUS_REG_BITS(TCON_MISC_SEL_ADDR, 1, OEV1_SEL, 1);
WRITE_CBUS_REG_BITS(TCON_MISC_SEL_ADDR, 1, OEV3_SEL, 1);
CLEAR_CBUS_REG_MASK(TCON_MISC_SEL_ADDR, 1<<OEV_UNITE);
WRITE_CBUS_REG(OEV1_HS_ADDR, TCON_PWM_HS3);
WRITE_CBUS_REG(OEV1_HE_ADDR, TCON_PWM_HE3);
WRITE_CBUS_REG(OEV1_VS_ADDR, TCON_PWM_VS3);
WRITE_CBUS_REG(OEV1_VE_ADDR, TCON_PWM_VS3+TCON_PWM_VS2);
}
void analog_switch(int flag)
{
int i;
unsigned reg_value = 0;
if (flag) {
printf("analog on\n");
SET_CBUS_REG_MASK(AM_ANALOG_TOP_REG0, 1 << 1); // set 0x206e bit[1] 1 to power on top analog
for (i = 0; i < ANALOG_COUNT; i++) {
if (analog_regs[i].enable && (analog_regs[i].set_bits || analog_regs[i].clear_bits)) {
if (analog_regs[i].enable == 1) {
WRITE_CBUS_REG(analog_regs[i].reg_addr, analog_regs[i].reg_value);
} else if (analog_regs[i].enable == 2) {
WRITE_APB_REG(analog_regs[i].reg_addr, analog_regs[i].reg_value);
} else if (analog_regs[i].enable == 3) {
WRITE_AHB_REG(analog_regs[i].reg_addr, analog_regs[i].reg_value);
}
}
}
} else {
printf("analog off\n");
for (i = 0; i < ANALOG_COUNT; i++) {
if (analog_regs[i].enable && (analog_regs[i].set_bits || analog_regs[i].clear_bits)) {
if (analog_regs[i].enable == 1) {
analog_regs[i].reg_value = READ_CBUS_REG(analog_regs[i].reg_addr);
printf("%s(0x%x):0x%x", analog_regs[i].name, CBUS_REG_ADDR(analog_regs[i].reg_addr), analog_regs[i].reg_value);
if (analog_regs[i].clear_bits) {
CLEAR_CBUS_REG_MASK(analog_regs[i].reg_addr, analog_regs[i].clear_bits);
printf(" & ~0x%x", analog_regs[i].clear_bits);
}
if (analog_regs[i].set_bits) {
SET_CBUS_REG_MASK(analog_regs[i].reg_addr, analog_regs[i].set_bits);
printf(" | 0x%x", analog_regs[i].set_bits);
}
reg_value = READ_CBUS_REG(analog_regs[i].reg_addr);
printf(" = 0x%x\n", reg_value);
} else if (analog_regs[i].enable == 2) {
analog_regs[i].reg_value = READ_APB_REG(analog_regs[i].reg_addr);
printf("%s(0x%x):0x%x", analog_regs[i].name, APB_REG_ADDR(analog_regs[i].reg_addr), analog_regs[i].reg_value);
if (analog_regs[i].clear_bits) {
CLEAR_APB_REG_MASK(analog_regs[i].reg_addr, analog_regs[i].clear_bits);
printf(" & ~0x%x", analog_regs[i].clear_bits);
}
if (analog_regs[i].set_bits) {
SET_APB_REG_MASK(analog_regs[i].reg_addr, analog_regs[i].set_bits);
printf(" | 0x%x", analog_regs[i].set_bits);
}
reg_value = READ_APB_REG(analog_regs[i].reg_addr);
printf(" = 0x%x\n", reg_value);
} else if (analog_regs[i].enable == 3) {
analog_regs[i].reg_value = READ_AHB_REG(analog_regs[i].reg_addr);
printf("%s(0x%x):0x%x", analog_regs[i].name, AHB_REG_ADDR(analog_regs[i].reg_addr), analog_regs[i].reg_value);
if (analog_regs[i].clear_bits) {
CLEAR_AHB_REG_MASK(analog_regs[i].reg_addr, analog_regs[i].clear_bits);
printf(" & ~0x%x", analog_regs[i].clear_bits);
}
if (analog_regs[i].set_bits) {
SET_AHB_REG_MASK(analog_regs[i].reg_addr, analog_regs[i].set_bits);
printf(" | 0x%x", analog_regs[i].set_bits);
}
reg_value = READ_AHB_REG(analog_regs[i].reg_addr);
printf(" = 0x%x\n", reg_value);
}
}
}
CLEAR_CBUS_REG_MASK(AM_ANALOG_TOP_REG0, 1 << 1); // set 0x206e bit[1] 0 to shutdown top analog
}
}
void cooling(void)
{
int i;
writel(0,P_WATCHDOG_TC);//disable Watchdog
//GPIOX_53 reset chip power ctrl
clrbits_le32(P_PREG_FGPIO_O, 1<<21);
clrbits_le32(P_PREG_FGPIO_EN_N, 1<<21);
for(i=0; i<800; i++)
{
__udelay(1000);
}
//vcc_12v/24v power down GPIOX_70
clrbits_le32(P_PREG_GGPIO_O, 1<<6);
clrbits_le32(P_PREG_GGPIO_EN_N, 1<<6);
setbits_le32(P_PERIPHS_PIN_MUX_2,((1<<29)|(1<<30)));
writel(0x18003033, P_UART1_CONTROL);
serial_puts("\nstandby...\n");
writel(0x209861f1, P_HHI_GCLK_MPEG0);
writel(0x208b8028, P_HHI_GCLK_MPEG1);
writel(0xfffffc07, P_HHI_GCLK_MPEG2);
writel(0xffc40021, P_HHI_GCLK_OTHER);
//analog off
WRITE_CBUS_REG(SAR_ADC_REG3, 0x3008510a);
//WRITE_CBUS_REG(VGHL_PWM_REG0, 0x0); //the same with off
//WRITE_CBUS_REG(WIFI_ADC_SAMPLING, 0x0); //the same with off
WRITE_APB_REG(ADC_EN_ADC, 0x0); //the same with off
//WRITE_AHB_REG(WIFI_ADC_DAC, 0x0); //the same with off
//WRITE_AHB_REG(ADC_EN_CMLGEN_RES, 0x0); //the same with off
//WRITE_AHB_REG(WIFI_SARADC, 0x0); //the same with off
//usb off
WRITE_CBUS_REG(PREI_USB_PHY_REG, 0x8040012b);
//clock off
//WRITE_CBUS_REG(HHI_DEMOD_CLK_CNTL, 0x400); //the same with off
//WRITE_CBUS_REG(HHI_SATA_CLK_CNTL, 0x0); //the same with off
//WRITE_CBUS_REG(HHI_ETH_CLK_CNTL, 0x207); //the same with off
//WRITE_CBUS_REG(HHI_WIFI_CLK_CNTL, 0x0); //the same with off
WRITE_CBUS_REG(HHI_VID_CLK_CNTL, 0x840e);
WRITE_CBUS_REG(HHI_AUD_CLK_CNTL, 0x800018);
WRITE_CBUS_REG(HHI_MALI_CLK_CNTL, 0x202);
WRITE_CBUS_REG(HHI_HDMI_CLK_CNTL, 0x203);
WRITE_CBUS_REG(HHI_MPEG_CLK_CNTL, 0x1083);
//pll off
WRITE_CBUS_REG(HHI_DEMOD_PLL_CNTL, 0x8232);
WRITE_CBUS_REG(HHI_VID_PLL_CNTL, 0x8641);
WRITE_CBUS_REG(HHI_AUD_PLL_CNTL, 0xca80);
WRITE_CBUS_REG(HHI_OTHER_PLL_CNTL, 0x887d);
#ifdef SYSTEM_16K
if (READ_CBUS_REG(HHI_MPEG_CLK_CNTL)&(1<<8))
CLEAR_CBUS_REG_MASK(HHI_MPEG_CLK_CNTL, (1<<8)); // clk81 = xtal
SET_CBUS_REG_MASK(HHI_MPEG_CLK_CNTL, (1<<9)); // xtal_rtc = rtc
WRITE_CBUS_REG_BITS(HHI_MPEG_CLK_CNTL, 0x1, 0, 6); // devider = 2
WRITE_CBUS_REG_BITS(HHI_MPEG_CLK_CNTL, 0, 12, 2); // clk81 src -> xtal_rtc
SET_CBUS_REG_MASK(HHI_MPEG_CLK_CNTL, (1<<8)); // clk81 = xtal_rtc / devider
#else
CLEAR_CBUS_REG_MASK(HHI_MPEG_CLK_CNTL, (1<<8)); // clk81 = xtal
WRITE_CBUS_REG_BITS(HHI_MPEG_CLK_CNTL, 0x1e, 0, 6); // devider = 30
WRITE_CBUS_REG_BITS(HHI_MPEG_CLK_CNTL, 0, 12, 2); // clk81 src -> xtal_rtc
SET_CBUS_REG_MASK(HHI_MPEG_CLK_CNTL, (1<<8)); // clk81 = xtal_rtc / devider
#endif
CLEAR_CBUS_REG_MASK(HHI_A9_CLK_CNTL, (1<<7)); // clka9 = xtal_rtc / 2
#ifdef SYSTEM_16K
SET_CBUS_REG_MASK(PREG_CTLREG0_ADDR, 1);
#endif
WRITE_CBUS_REG(HHI_A9_AUTO_CLK0,
(2 << 24) | // sleep select 1000uS timebase
(0x20 << 16) | // Set the delay wakeup time (32mS)
(0 << 5) | // don't clear the FIQ global mask
(0 << 4) | // don't clear the IRQ global mask
(2 << 2)); // Set interrupt wakeup only
WRITE_CBUS_REG(HHI_A9_AUTO_CLK1,
(0 << 20) | // start delay timebase
(1 << 12) | // 1uS enable delay
(1 << 8) | // 1uS gate delay
(1 << 0)); // 1us start delay
SET_CBUS_REG_MASK(HHI_A9_AUTO_CLK0, 1 << 0);
SET_CBUS_REG_MASK(HHI_SYS_PLL_CNTL, (1<<15)); // turn off sys pll
while(1)
{
if(serial_tstc()) break;
}
//vcc_12v/24v power on
setbits_le32(P_PREG_GGPIO_EN_N, 1<<6);
for(i=0; i<800; i++)
{
__udelay(1000);
}
//GPIOX_53 reset chip power ctrl
setbits_le32(P_PREG_FGPIO_O, 1<<21);
memory_pll_init(0,NULL);
serial_puts("\ngate clock on...\n");
writel(0xffffffff, P_HHI_GCLK_MPEG0);
writel(0xffffffff, P_HHI_GCLK_MPEG1);
writel(0xffffffff, P_HHI_GCLK_MPEG2);
writel(0xffffffff, P_HHI_GCLK_OTHER);
#if 0
//analog on
WRITE_CBUS_REG(SAR_ADC_REG3, 0x2008510a);
//WRITE_CBUS_REG(VGHL_PWM_REG0, 0x0); //the same with off
//WRITE_CBUS_REG(WIFI_ADC_SAMPLING, 0x0); //the same with off
//WRITE_APB_REG(ADC_EN_ADC, 0x0); //the same with off
//WRITE_AHB_REG(WIFI_ADC_DAC, 0x0); //the same with off
//WRITE_AHB_REG(ADC_EN_CMLGEN_RES, 0x0); //the same with off
//WRITE_AHB_REG(WIFI_SARADC, 0x0); //the same with off
//usb on
WRITE_CBUS_REG(PREI_USB_PHY_REG, 0x80400128);
//clock on
//WRITE_CBUS_REG(HHI_DEMOD_CLK_CNTL, 0x400); //the same with off
//WRITE_CBUS_REG(HHI_SATA_CLK_CNTL, 0x0); //the same with off
//WRITE_CBUS_REG(HHI_ETH_CLK_CNTL, 0x207); //the same with off
//WRITE_CBUS_REG(HHI_WIFI_CLK_CNTL, 0x0); //the same with off
WRITE_CBUS_REG(HHI_VID_CLK_CNTL, 0x840f);
WRITE_CBUS_REG(HHI_AUD_CLK_CNTL, 0x800018);
WRITE_CBUS_REG(HHI_MALI_CLK_CNTL, 0x302);
WRITE_CBUS_REG(HHI_HDMI_CLK_CNTL, 0x303);
WRITE_CBUS_REG(HHI_MPEG_CLK_CNTL, 0x1183);
//pll on
WRITE_CBUS_REG(HHI_DEMOD_PLL_CNTL, 0x232);
WRITE_CBUS_REG(HHI_VID_PLL_CNTL, 0x641);
WRITE_CBUS_REG(HHI_AUD_PLL_CNTL, 0x4a80);
//WRITE_CBUS_REG(HHI_OTHER_PLL_CNTL, 0x87d);
#endif
return 0;
}
static void restore_pinmux(void)
{
int i;
for (i=0;i<6;i++)
WRITE_CBUS_REG(PERIPHS_PIN_MUX_0+i, pinmux_backup[i]);
}
static void set_hpll_clk_out(unsigned clk)
{
printf("config HPLL\n");
aml_write_reg32_op(P_HHI_VID_PLL_CNTL2, 0x69c88000);
aml_write_reg32_op(P_HHI_VID_PLL_CNTL3, 0xca563823);
aml_write_reg32_op(P_HHI_VID_PLL_CNTL4, 0x40238100);
aml_write_reg32_op(P_HHI_VID_PLL_CNTL5, 0x00012286);
aml_write_reg32_op(P_HHI_VID2_PLL_CNTL2, 0x430a800); // internal LDO share with HPLL & VIID PLL
aml_write_reg32_op(P_HHI_HDMI_PHY_CNTL0, 0x08c31e8b);
switch(clk){
case 2160:
aml_write_reg32_op(P_HHI_VID_PLL_CNTL2, 0x59c80000);
aml_write_reg32_op(P_HHI_VID_PLL_CNTL3, 0x0a563823);
aml_write_reg32_op(P_HHI_VID_PLL_CNTL4, 0x0123b100);
aml_write_reg32_op(P_HHI_VID_PLL_CNTL5, 0x12385);
aml_write_reg32_op(P_HHI_VID_PLL_CNTL, 0x6001042d);
aml_write_reg32_op(P_HHI_VID_PLL_CNTL, 0x4001042d);
WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL);
break;
case 1488:
aml_write_reg32_op(P_HHI_VID_PLL_CNTL2, 0x69c8ce00);
aml_write_reg32_op(P_HHI_VID_PLL_CNTL4, 0x4023d100);
aml_write_reg32_op(P_HHI_VID_PLL_CNTL3, 0x8a7ad023);
aml_write_reg32_op(P_HHI_VID_PLL_CNTL5, 0x12286);
aml_write_reg32_op(P_HHI_VID_PLL_CNTL, 0x6000043d);
aml_write_reg32_op(P_HHI_VID_PLL_CNTL, 0x4000043d);
WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL);
break;
case 1080:
aml_write_reg32_op(P_HHI_VID_PLL_CNTL, 0x6000042d);
aml_write_reg32_op(P_HHI_VID_PLL_CNTL, 0x4000042d);
break;
case 1066:
WRITE_CBUS_REG(HHI_VID_PLL_CNTL, 0x42a);
break;
case 1058:
WRITE_CBUS_REG(HHI_VID_PLL_CNTL, 0x422);
break;
case 1086:
WRITE_CBUS_REG(HHI_VID_PLL_CNTL, 0x43e);
break;
case 1296:
aml_write_reg32_op(P_HHI_VID_PLL_CNTL2, 0x59c88000);
aml_write_reg32_op(P_HHI_VID_PLL_CNTL3, 0xca49b022);
aml_write_reg32_op(P_HHI_VID_PLL_CNTL4, 0x0023b100);
aml_write_reg32_op(P_HHI_VID_PLL_CNTL5, 0x00012385);
aml_write_reg32_op(P_HHI_VID_PLL_CNTL, 0x600c0436);
aml_write_reg32_op(P_HHI_VID_PLL_CNTL, 0x400c0436);
aml_write_reg32_op(P_HHI_VID_PLL_CNTL5, 0x00016385);
break;
default:
printf("error hpll clk: %d\n", clk);
break;
}
if(clk < 2970)
aml_write_reg32_op(P_HHI_VID_PLL_CNTL5, (aml_read_reg32_op(P_HHI_VID_PLL_CNTL5) & (~(0xf << 12))) | (0x6 << 12));
// Improve HDMI HPLL Long TIE
if( clk != 1296 )// 1296MHz is only for 480cvbs/576cvbs on m8 serials, and is not suitable with 0x8a56d023
aml_write_reg32_op(P_HHI_VID_PLL_CNTL3, 0x8a56d023);
// P_HHI_HDMI_PHY_CNTL1 bit[1]: enable clock bit[0]: soft reset
#define RESET_HDMI_PHY() \
aml_write_reg32_op(P_HHI_HDMI_PHY_CNTL1, 3); \
h_delay(); \
aml_write_reg32_op(P_HHI_HDMI_PHY_CNTL1, 2); \
h_delay()
RESET_HDMI_PHY();
RESET_HDMI_PHY();
RESET_HDMI_PHY();
printf("config HPLL done\n");
}
//NTSC or PAL input(interlace mode): CLOCK + D0~D7 + HSYNC + VSYNC + FID
static void reinit_bt601in_dec(struct am656in_dev_s *devp)
{
reset_bt656in_module();
WRITE_CBUS_REG(BT_PORT_CTRL, (0 << BT_IDQ_EN ) | // use external idq pin.
(1 << BT_IDQ_PHASE ) |
( 1 << BT_FID_HSVS ) | // FID came from HS VS.
( 1 << BT_HSYNC_PHASE ) |
(1 << BT_D8B ) |
(4 << BT_FID_DELAY ) |
(5 << BT_VSYNC_DELAY) |
(5 << BT_HSYNC_DELAY));
WRITE_CBUS_REG(BT_601_CTRL2 , ( 10 << 16)); // FID field check done point.
WRITE_CBUS_REG(BT_SWAP_CTRL, ( 4 << 0 ) | // suppose the input bitstream format is Cb0 Y0 Cr0 Y1.
( 5 << 4 ) |
( 6 << 8 ) |
( 7 << 13 ) );
WRITE_CBUS_REG(BT_LINECTRL , ( 1 << 31 ) | //software line ctrl enable.
(1644 << 16 ) | //1440 + 204
220 ) ;
// ANCI is the field blanking data, like close caption. If it connected to digital camara interface, the jpeg bitstream also use this ANCI FIFO.
//WRITE_CBUS_REG(BT_ANCISADR, devp->pbufAddr);
//WRITE_CBUS_REG(BT_ANCIEADR, devp->pbufAddr + BT656IN_ANCI_DATA_SIZE);
WRITE_CBUS_REG(BT_AFIFO_CTRL, (1 <<31) | // load start and end address to afifo.
(1 << 6) | // fill _en;
(1 << 3)) ; // urgent
WRITE_CBUS_REG(BT_INT_CTRL , // (1 << 5) | //ancififo done int.
// (1 << 4) | //SOF interrupt enable.
// (1 << 3) | //EOF interrupt enable.
(1 << 1)); // | //input overflow interrupt enable.
// (1 << 0)); //bt656 controller error interrupt enable.
WRITE_CBUS_REG(BT_ERR_CNT, (626 << 16) | (2000));
//otherwise there is always error flag,
//because the camera input use HREF ont HSYNC,
//there are some lines without HREF sometime
WRITE_CBUS_REG(BT_FIELDSADR, (1 << 16) | 1); // field 0/1 start lcnt
if(devp->para.fmt == TVIN_SIG_FMT_BT601IN_576I_50HZ) //input is PAL
{
WRITE_CBUS_REG(BT_VBIEND, 22 | (22 << 16)); //field 0/1 VBI last line number
WRITE_CBUS_REG(BT_VIDEOSTART, 23 | (23 << 16)); //Line number of the first video start line in field 0/1.
WRITE_CBUS_REG(BT_VIDEOEND , 312 | // Line number of the last video line in field 1. added video end for avoid overflow.
(312 <<16)); // Line number of the last video line in field 0
WRITE_CBUS_REG(BT_CTRL , (0 << BT_MODE_BIT ) | // BT656 standaREAD_CBUS_REG interface.
(1 << BT_AUTO_FMT ) |
(1 << BT_EN_BIT ) | // enable BT moduale.
(0 << BT_REF_MODE_BIT ) | // timing reference is from bit stream.
(0 << BT_FMT_MODE_BIT ) | //PAL
(1 << BT_SLICE_MODE_BIT )| // no ancillay flag.
(0 << BT_FID_EN_BIT ) | // use external fid pin.
(1 << BT_CLK27_SEL_BIT) | // use external xclk27.
(1 << BT_XCLK27_EN_BIT) ); // xclk27 is input.
WRITE_CBUS_REG(VDIN_WR_V_START_END, 287 | //v end
(0 << 16) ); // v start
}
else //if(am656in_dec_info.para.fmt == TVIN_SIG_FMT_BT601IN_480I) //input is NTSC
{
WRITE_CBUS_REG(BT_VBIEND, 21 | (21 << 16)); //field 0/1 VBI last line number
WRITE_CBUS_REG(BT_VIDEOSTART, 18 | (18 << 16)); //Line number of the first video start line in field 0/1.
WRITE_CBUS_REG(BT_VIDEOEND , 257 | // Line number of the last video line in field 1. added video end for avoid overflow.
(257 <<16)); // Line number of the last video line in field 0
WRITE_CBUS_REG(BT_CTRL ,(0 << BT_MODE_BIT ) | // BT656 standaREAD_CBUS_REG interface.
(1 << BT_AUTO_FMT ) |
(1 << BT_EN_BIT ) | // enablem656in_star BT moduale.
(0 << BT_REF_MODE_BIT ) | // timing reference is from bit stream.
(1 << BT_FMT_MODE_BIT ) | // NTSC
(1 << BT_SLICE_MODE_BIT )| // no ancillay flag.
(0 << BT_FID_EN_BIT ) | // use external fid pin.
(1 << BT_CLK27_SEL_BIT) | // use external xclk27.
(1 << BT_XCLK27_EN_BIT) ); // xclk27 is input.
WRITE_CBUS_REG(VDIN_WR_V_START_END, 239 | //v end
(0 << 16) ); // v start
}
return;
}
//CAMERA input(progressive mode): CLOCK + D0~D7 + HREF + VSYNC
static void reinit_camera_dec(struct am656in_dev_s *devp)
{
//reset_bt656in_module();
int temp_data;
unsigned char hsync_enable = devp->para.hsync_phase;
unsigned char vsync_enable = devp->para.vsync_phase;
unsigned short hs_bp = devp->para.hs_bp;
unsigned short vs_bp = devp->para.vs_bp;
temp_data = READ_CBUS_REG(BT_CTRL);
temp_data &= ~( 1 << BT_EN_BIT );
WRITE_CBUS_REG(BT_CTRL, temp_data); //disable BT656 input
// reset BT656in module.
temp_data = READ_CBUS_REG(BT_CTRL);
temp_data |= ( 1 << BT_SOFT_RESET );
WRITE_CBUS_REG(BT_CTRL, temp_data);
/*WRITE_CBUS_REG(BT_VIDEOSTART, 1 | (1 << 16)); //Line number of the first video start line in field 0/1.there is a blank
WRITE_CBUS_REG(BT_VIDEOEND , (am656in_dec_info.active_line )| // Line number of the last video line in field 1. added video end for avoid overflow.
((am656in_dec_info.active_line ) << 16)); */ // Line number of the last video line in field 0
WRITE_CBUS_REG(BT_PORT_CTRL, (0 << BT_IDQ_EN ) | // use external idq pin.
(0 << BT_IDQ_PHASE ) |
(0 << BT_FID_HSVS ) | // FID came from HS VS.
(vsync_enable << BT_VSYNC_PHASE) |
(hsync_enable << BT_HSYNC_PHASE) |
(0 << BT_D8B ) |
(4 << BT_FID_DELAY ) |
(0 << BT_VSYNC_DELAY) |
(2 << BT_HSYNC_DELAY)
);
//WRITE_CBUS_REG(BT_PORT_CTRL,0x421001);
WRITE_CBUS_REG(BT_601_CTRL2 , ( 10 << 16)); // FID field check done point.
WRITE_CBUS_REG(BT_SWAP_CTRL,
( 7 << 0 ) | //POS_Cb0_IN
( 4 << 4 ) | //POS_Y0_IN
( 5 << 8 ) | //POS_Cr0_IN
( 6 << 12 )); //POS_Y1_IN
WRITE_CBUS_REG(BT_LINECTRL , ( 1<< 31) | //software line ctrl enable.
((devp->para.h_active<< 1)<< 16 ) | //the number of active data per line
hs_bp);//horizontal active data start offset
// ANCI is the field blanking data, like close caption. If it connected to digital camara interface, the jpeg bitstream also use this ANCI FIFO.
//WRITE_CBUS_REG(BT_ANCISADR, devp->pbufAddr);
//WRITE_CBUS_REG(BT_ANCIEADR, devp->pbufAddr + BT656IN_ANCI_DATA_SIZE);
WRITE_CBUS_REG(BT_AFIFO_CTRL, (1 <<31) | // load start and end address to afifo.
(1 << 6) | // fill _en;
(1 << 3)) ; // urgent
WRITE_CBUS_REG(BT_INT_CTRL , //(1 << 5) | //ancififo done int.
//(1 << 4) | //SOF interrupt enable.
//(1 << 3) | //EOF interrupt enable.
(1 << 1)); //input overflow interrupt enable.
//(1 << 0)); //bt656 controller error interrupt enable.
WRITE_CBUS_REG(BT_ERR_CNT, ((2000) << 16) | (2000 * 10)); //total lines per frame and total pixel per line
//otherwise there is always error flag,
//because the camera input use HREF ont HSYNC,
//there are some lines without HREF sometime
WRITE_CBUS_REG(BT_FIELDSADR, (1 << 16) | 1); // field 0/1 start lcnt
WRITE_CBUS_REG(BT_VBISTART, 1 | (1 << 16)); //field 0/1 VBI last line number
WRITE_CBUS_REG(BT_VBIEND, 1 | (1 << 16)); //field 0/1 VBI last line number
WRITE_CBUS_REG(BT_VIDEOSTART, vs_bp | (vs_bp << 16)); //Line number of the first video start line in field 0/1.there is a blank
WRITE_CBUS_REG(BT_VIDEOEND , (devp->para.v_active + vs_bp)| // Line number of the last video line in field 1. added video end for avoid overflow.
((devp->para.v_active + vs_bp) << 16)); // Line number of the last video line in field 0
WRITE_CBUS_REG(BT_CTRL , (1 << BT_EN_BIT) // enable BT moduale.
|(0 << BT_REF_MODE_BIT ) // timing reference is from bit stream.
|(0 << BT_FMT_MODE_BIT ) //PAL
|(1 << BT_SLICE_MODE_BIT ) // no ancillay flag.
|(0 << BT_MODE_BIT) // BT656 standard interface.
|(1 << BT_CLOCK_ENABLE) // enable 656 clock.
|(0 << BT_FID_EN_BIT) // use external fid pin.
|(1 << BT_XCLK27_EN_BIT) // xclk27 is input.
|(1 << BT_PROG_MODE )
|(0 << BT_AUTO_FMT)
|(1 << BT_CAMERA_MODE) // enable camera mode
|(1 << BT_656CLOCK_RESET)
|(1 << BT_SYSCLOCK_RESET)
);
temp_data = READ_CBUS_REG(BT_CTRL);
temp_data &= ~( 1 << BT_SOFT_RESET );
WRITE_CBUS_REG(BT_CTRL, temp_data);
//enable BTR656 interface
WRITE_CBUS_REG(PERIPHS_PIN_MUX_7,0) ; //disable XIF function. it's shared with gpioZ_3.
temp_data = READ_CBUS_REG(PERIPHS_PIN_MUX_9);
WRITE_CBUS_REG(PERIPHS_PIN_MUX_9, temp_data|(1 << 13) | // gpioZ 11 to bt656 clk;
(1 << 14) | // enable gpioZ 10:3 to be bt656 dt_in
(1 << 15) |
(1 << 16));
return;
}
/*
NTSC or PAL input(interlace mode): CLOCK + D0~D7(with SAV + EAV )
*/
static void reinit_bt656in_dec(struct am656in_dev_s *devp)
{
reset_bt656in_module();
WRITE_CBUS_REG(BT_FIELDSADR, (4 << 16) | 4); // field 0/1 start lcnt: default value
// configuration the BT PORT control
// For standaREAD_CBUS_REG bt656 in stream, there's no HSYNC VSYNC pins.
// So we don't need to configure the port.
WRITE_CBUS_REG(BT_PORT_CTRL, 1 << BT_D8B); // data itself is 8 bits.
WRITE_CBUS_REG(BT_SWAP_CTRL, ( 4 << 0 ) | //POS_Y1_IN
( 5 << 4 ) | //POS_Cr0_IN
( 6 << 8 ) | //POS_Y0_IN
( 7 << 12 )); //POS_CB0_IN
WRITE_CBUS_REG(BT_LINECTRL , 0) ;
//there is no use anci in m2
// ANCI is the field blanking data, like close caption. If it connected to digital camara interface, the jpeg bitstream also use this ANCI FIFO.
// WRITE_CBUS_REG(BT_ANCISADR, devp->pbufAddr);
// WRITE_CBUS_REG(BT_ANCIEADR, devp->pbufAddr + BT656IN_ANCI_DATA_SIZE);
WRITE_CBUS_REG(BT_AFIFO_CTRL, (1 <<31) | // load start and end address to afifo.
(1 << 6) | // fill _en;
(1 << 3)) ; // urgent
WRITE_CBUS_REG(BT_INT_CTRL , // (1 << 5) | //ancififo done int.
// (1 << 4) | //SOF interrupt enable.
// (1 << 3) | //EOF interrupt enable.
(1 << 1)); // | //input overflow interrupt enable.
// (1 << 0)); //bt656 controller error interrupt enable.
WRITE_CBUS_REG(BT_ERR_CNT, (626 << 16) | (1760));
if(devp->para.fmt== TVIN_SIG_FMT_BT656IN_576I_50HZ) //input is PAL
{
WRITE_CBUS_REG(BT_VBIEND, 22 | (22 << 16)); //field 0/1 VBI last line number
WRITE_CBUS_REG(BT_VIDEOSTART, 23 | (23 << 16)); //Line number of the first video start line in field 0/1.
WRITE_CBUS_REG(BT_VIDEOEND , 312 | // Line number of the last video line in field 1. added video end for avoid overflow.
(312 <<16)); // Line number of the last video line in field 0
WRITE_CBUS_REG(BT_CTRL , (0 << BT_UPDATE_ST_SEL) | //Update bt656 status register when end of frame.
(1 << BT_COLOR_REPEAT) | //Repeated the color data when do 4:2:2 -> 4:4:4 data transfer.
(1 << BT_AUTO_FMT ) | //use haREAD_CBUS_REGware to check the PAL/NTSC format input format if it's standaREAD_CBUS_REG BT656 input format.
(1 << BT_MODE_BIT ) | // BT656 standaREAD_CBUS_REG interface.
(1 << BT_EN_BIT ) | // enable BT moduale.
(1 << BT_REF_MODE_BIT ) | // timing reference is from bit stream.
(1 << BT_CLK27_SEL_BIT) | // use external xclk27.
(1 << BT_XCLK27_EN_BIT)) ; // xclk27 is input.
WRITE_CBUS_REG(VDIN_WR_V_START_END, 287 | //v end
(0 << 16) ); // v start
}
else //if(am656in_dec_info.para.fmt == TVIN_SIG_FMT_BT656IN_480I) //input is PAL //input is NTSC
{
WRITE_CBUS_REG(BT_VBIEND, 21 | (21 << 16)); //field 0/1 VBI last line number
WRITE_CBUS_REG(BT_VIDEOSTART, 18 | (18 << 16)); //Line number of the first video start line in field 0/1.
WRITE_CBUS_REG(BT_VIDEOEND , 257 | // Line number of the last video line in field 1. added video end for avoid overflow.
(257 <<16)); // Line number of the last video line in field 0
WRITE_CBUS_REG(BT_CTRL , (0 << BT_UPDATE_ST_SEL) | //Update bt656 status register when end of frame.
(1 << BT_COLOR_REPEAT) | //Repeated the color data when do 4:2:2 -> 4:4:4 data transfer.
(1 << BT_AUTO_FMT ) | //use haREAD_CBUS_REGware to check the PAL/NTSC format input format if it's standaREAD_CBUS_REG BT656 input format.
(1 << BT_MODE_BIT ) | // BT656 standaREAD_CBUS_REG interface.
(1 << BT_EN_BIT ) | // enable BT moduale.
(1 << BT_REF_MODE_BIT ) | // timing reference is from bit stream.
(1 << BT_CLK27_SEL_BIT) | // use external xclk27.
(1 << BT_XCLK27_EN_BIT) | // xclk27 is input.
(1 << BT_FMT_MODE_BIT)); //input format is NTSC
WRITE_CBUS_REG(VDIN_WR_V_START_END, 239 | //v end
(0 << 16) ); // v start
}
return;
}
_mali_osk_errcode_t mali_platform_power_mode_change(mali_power_mode power_mode)
{
unsigned long flags;
unsigned cpu_divider, mali_divider;
unsigned ddr_pll_setting, sys_pll_setting;
unsigned cpu_freq, ddr_freq;
int mali_flag;
MALI_DEBUG_PRINT(3, ( "mali_platform_power_mode_change power_mode=%d\n", power_mode));
switch (power_mode) {
case MALI_POWER_MODE_LIGHT_SLEEP:
case MALI_POWER_MODE_DEEP_SLEEP:
/* Turn off mali clock gating */
if (mali_clk) {
mali_clk->disable(mali_clk);
} else {
spin_lock_irqsave(&lock, flags);
CLEAR_CBUS_REG_MASK(HHI_MALI_CLK_CNTL, 1 << 8);
spin_unlock_irqrestore(&lock, flags);
}
break;
case MALI_POWER_MODE_ON:
/* Turn on MALI clock gating */
if (mali_clk) {
mali_clk->enable(mali_clk);
}
else {
spin_lock_irqsave(&lock, flags);
CLEAR_CBUS_REG_MASK(HHI_MALI_CLK_CNTL, 1 << 8);
sys_pll_setting = READ_MPEG_REG(HHI_SYS_PLL_CNTL);
cpu_freq = ((sys_pll_setting&0x1ff)*24)>>(sys_pll_setting>>16); // assume 24M xtal
cpu_divider = READ_MPEG_REG_BITS(HHI_SYS_CPU_CLK_CNTL, 2, 2);
if (cpu_divider == 3)
cpu_divider = 2; // now fix at /4
cpu_freq >>= cpu_divider;
ddr_pll_setting = READ_MPEG_REG(HHI_DDR_PLL_CNTL);
ddr_freq = ((ddr_pll_setting&0x1ff)*24)>>((ddr_pll_setting>>16)&3);
mali_divider = 1;
while ((mali_divider * cpu_freq < ddr_freq) || (264 * mali_divider < ddr_freq)) // assume mali max 264M
mali_divider++;
mali_flag = ((mali_divider-1) != (READ_MPEG_REG(HHI_MALI_CLK_CNTL)&0x7f));
if (mali_flag){
WRITE_CBUS_REG(HHI_MALI_CLK_CNTL,
(3 << 9) | // select ddr pll as clock source
((mali_divider-1) << 0)); // ddr clk / divider
READ_CBUS_REG(HHI_MALI_CLK_CNTL); // delay
}
SET_CBUS_REG_MASK(HHI_MALI_CLK_CNTL, 1 << 8);
spin_unlock_irqrestore(&lock, flags);
if (mali_flag)
MALI_DEBUG_PRINT(3, ("(CTS_MALI_CLK) = %d/%d = %dMHz --- when mali gate on\n", ddr_freq, mali_divider, ddr_freq/mali_divider));
}
mali_meson_poweron(0);
break;
}
last_power_mode = power_mode;
MALI_SUCCESS;
}
static void setup_new_net_chip(void)
{
eth_aml_reg0_t eth_reg0;
//setup ethernet clk need calibrate to configre
#ifdef RMII_PHY_INTERFACE
/* setup ethernet pinmux use gpioz(5-14) */
SET_CBUS_REG_MASK(PERIPHS_PIN_MUX_6, (1 << 14) | (1 << 13) | (1 << 12) |
(1 << 11) | (1 << 8 ) | (1 << 7 ) | (1 << 10 ) | (1 << 6 ) | (1 << 5 ));
eth_reg0.d32 = 0;
eth_reg0.b.phy_intf_sel = 0;
eth_reg0.b.data_endian = 0;
eth_reg0.b.desc_endian = 0;
eth_reg0.b.rx_clk_rmii_invert = 0;
eth_reg0.b.rgmii_tx_clk_src = 0;
eth_reg0.b.rgmii_tx_clk_phase = 0;
eth_reg0.b.rgmii_tx_clk_ratio = 1;
eth_reg0.b.phy_ref_clk_enable = 1;
eth_reg0.b.clk_rmii_i_invert = 1;
eth_reg0.b.clk_en = 1;
eth_reg0.b.adj_enable = 1;
eth_reg0.b.adj_setup = 0;
eth_reg0.b.adj_delay = 18;
eth_reg0.b.adj_skew = 0;
eth_reg0.b.cali_start = 0;
eth_reg0.b.cali_rise = 0;
eth_reg0.b.cali_sel = 0;
eth_reg0.b.rgmii_rx_reuse = 0;
eth_reg0.b.eth_urgent = 0;
WRITE_CBUS_REG(PREG_ETHERNET_ADDR0, eth_reg0.d32 );//1 //rmii mode
WRITE_CBUS_REG(0x2050,0x1000);//1 //rmii mode
#elif RGMII_PHY_INTERFACE
SET_CBUS_REG_MASK(PERIPHS_PIN_MUX_6, 0xffef);
eth_reg0.d32 = 0;
eth_reg0.b.phy_intf_sel = 1;
eth_reg0.b.data_endian = 0;
eth_reg0.b.desc_endian = 0;
eth_reg0.b.rx_clk_rmii_invert = 0;
eth_reg0.b.rgmii_tx_clk_src = 0;
eth_reg0.b.rgmii_tx_clk_phase = 0;
eth_reg0.b.rgmii_tx_clk_ratio = 2;
eth_reg0.b.phy_ref_clk_enable = 1;
eth_reg0.b.clk_rmii_i_invert = 1;
eth_reg0.b.clk_en = 1;
eth_reg0.b.adj_enable = 1;
eth_reg0.b.adj_setup = 1;
eth_reg0.b.adj_delay = 4;
eth_reg0.b.adj_skew = 0xc;
eth_reg0.b.cali_start = 0;
eth_reg0.b.cali_rise = 0;
eth_reg0.b.cali_sel = 0;
eth_reg0.b.rgmii_rx_reuse = 0;
eth_reg0.b.eth_urgent = 0;
WRITE_CBUS_REG(0x2050, eth_reg0.d32);// rgmii mode
SET_CBUS_REG_MASK(0x10a5,1<<27);
WRITE_CBUS_REG(0x2050,0x7d21);// rgmii mode
SET_CBUS_REG_MASK(0x108a,0xb803);
SET_CBUS_REG_MASK(HHI_MPLL_CNTL9,(1638<<0)| (0<<14)|(1<<15) | (1<<14) | (5<<16) | (0<<25) | (0<<26) |(0<<30) | (0<<31));
#endif
#ifdef RGMII_PHY_INTERFACE
/* setup ethernet mode */
CLEAR_CBUS_REG_MASK(HHI_MEM_PD_REG0, (1 << 3) | (1<<2));
/* hardware reset ethernet phy : gpioz14 connect phyreset pin*/
CLEAR_CBUS_REG_MASK(PREG_PAD_GPIO2_EN_N, 1 << 28);
CLEAR_CBUS_REG_MASK(PREG_PAD_GPIO2_O, 1 << 28);
udelay(10000);
SET_CBUS_REG_MASK(PREG_PAD_GPIO2_O, 1 << 28);
#else
/* setup ethernet mode */
CLEAR_CBUS_REG_MASK(HHI_MEM_PD_REG0, (1 << 3) | (1<<2));
/* hardware reset ethernet phy : gpioz14 connect phyreset pin*/
CLEAR_CBUS_REG_MASK(PREG_PAD_GPIO1_EN_N, 1 << 31);
CLEAR_CBUS_REG_MASK(PREG_PAD_GPIO1_O, 1 << 31);
udelay(10000);
SET_CBUS_REG_MASK(PREG_PAD_GPIO1_O, 1 << 31);
#endif
}
static void set_hpll_clk_out(unsigned clk)
{
printk("config HPLL\n");
#if MESON_CPU_TYPE == MESON_CPU_TYPE_MESON8
printk("%s[%d] clk = %d\n", __func__, __LINE__, clk);
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c88000);
aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0xca563823);
aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x40238100);
aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x00012286);
aml_write_reg32(P_HHI_VID2_PLL_CNTL2, 0x430a800); // internal LDO share with HPLL & VIID PLL
switch(clk){
case 2971: // only for 4k mode
#ifdef CONFIG_AML_VOUT_FRAMERATE_AUTOMATION
case 2976: // only for 4k mode with clock*0.999
#endif
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c84000);
aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0xce49c022);
aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x4123b100);
aml_set_reg32_bits(P_HHI_VID2_PLL_CNTL2, 1, 16, 1);
aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x00012385);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x6000043d);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x4000043d);
WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL);
h_delay();
aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x00016385); // optimise HPLL VCO 2.97GHz performance
#ifdef CONFIG_AML_VOUT_FRAMERATE_AUTOMATION
if (clk == 2976)
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c84d04); // lower div_frac to get clk*0.999
else
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c84e00);
#else
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c84e00);
#endif
break;
case 2970: // for 1080p/i 720p mode
#ifdef CONFIG_AML_VOUT_FRAMERATE_AUTOMATION
case 2975: // For 1080P/i 720p mode with clock*0.999
#endif
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c84000);
aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0x8a46c023);
aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x4123b100);
aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x00012385);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x6000043d);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x4000043d);
WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL);
h_delay();
aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x00016385); // optimise HPLL VCO 2.97GHz performance
#ifdef CONFIG_AML_VOUT_FRAMERATE_AUTOMATION
if (clk == 2975)
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c84d04); // lower div_frac to get clk*0.999
else
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c84e00);
#else
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c84e00);
#endif
break;
case 2160:
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c84000);
aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0x8a46c023);
aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x0123b100);
aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x12385);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x6001042d);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x4001042d);
WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL);
break;
case 2058:
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x59c80000);
aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0x0a563823);
aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x0123b100);
aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x12385);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x6001042a);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x4001042a);
WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL);
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c8cdf4);
break;
case 1600:
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c8c000);
aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0x8a7ad023);
aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x4023d100);
aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x12286);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x60000442);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x40000442);
WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL);
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c8c506);
break;
case 1710:
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c8c000);
aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0x8a7ad023);
aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x4023d100);
aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x12286);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x60000447);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x40000447);
WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL);
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c8c3ac);
break;
case 2130:
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x59c80000);
aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0x0a563823);
aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x0123b100);
aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x12385);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x6001042c);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x4001042c);
WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL);
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c8c74f);
break;
case 2600:
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x59c80000);
aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0x0a563823);
aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x0123b100);
aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x12385);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x60010436);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x40010436);
WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL);
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c8c294);
break;
case 2925:
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x59c80000);
aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0x0a563823);
aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x0123b100);
aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x12385);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x6001043c);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x4001043c);
WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL);
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c8cfb4);
break;
case 2380:
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x59c80000);
aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0x0a563823);
aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x0123b100);
aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x12385);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x60010431);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x40010431);
WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL);
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c8c994);
break;
case 1716:
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c8c000);
aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x4023d100);
aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0x8a7ad023);
aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x12286);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x60000447);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x40000447);
WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL);
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c8c7f8);
break;
case 2014:
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x59c8cf55);
aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0x0a563823);
aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x0123b100);
aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x12385);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x60010429);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x40010429);
WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL);
break;
case 1422:
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c8c000);
aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x4023d100);
aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0x8a7ad023);
aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x12286);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x6000043b);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x4000043b);
WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL);
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c8c40f);
break;
case 1540:
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c8c2ab);
aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x4023d100);
aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0x8a7ad023);
aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x12286);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x60000440);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x40000440);
WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL);
break;
#ifdef CONFIG_AML_VOUT_FRAMERATE_AUTOMATION
case 2161:
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c84f48);
aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0x8a46c023);
aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x0123b100);
aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x12385);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x6001042c);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x4001042c);
WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL);
break;
#endif
case 1080:
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c8c000);
aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x4023d100);
aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0x8a7ad023);
aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x12286);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x6000042d);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x4000042d);
WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL);
break;
#ifdef CONFIG_AML_VOUT_FRAMERATE_AUTOMATION
case 1081:
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c8cf48);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x6000042c);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x4000042c);
WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL);
break;
#endif
case 1296:
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x59c88000);
aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0xca49b022);
aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x0023b100);
aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x00012385);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x600c0436);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x400c0436);
aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x00016385);
WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL);
break;
default:
printk("error hpll clk: %d\n", clk);
break;
}
if(clk < 2970)
aml_write_reg32(P_HHI_VID_PLL_CNTL5, (aml_read_reg32(P_HHI_VID_PLL_CNTL5) & (~(0xf << 12))) | (0x6 << 12));
#endif
#if MESON_CPU_TYPE == MESON_CPU_TYPE_MESON8B
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c88000);
aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0xca563823);
aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x40238100);
aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x00012286);
aml_write_reg32(P_HHI_VID2_PLL_CNTL2, 0x430a800); // internal LDO share with HPLL & VIID PLL
switch(clk){
case 2970:
#ifdef CONFIG_AML_VOUT_FRAMERATE_AUTOMATION
case 2975: // FOR 1080P/i 720p mode with clock*0.999
#endif
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c84000);
aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0x8a46c023);
aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x4123b100);
aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x00012385);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x6000043d);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x4000043d);
WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL);
h_delay();
aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x00016385); // optimise HPLL VCO 2.97GHz performance
#ifdef CONFIG_AML_VOUT_FRAMERATE_AUTOMATION
if( clk == 2975 )
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c84d04); // lower div_frac to get clk*0.999
else
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c84e00);
#else
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c84e00);
#endif
break;
#ifdef CONFIG_AML_VOUT_FRAMERATE_AUTOMATION
case 2161:
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c84f48);
aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0x8a46c023);
aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x0123b100);
aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x12385);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x6001042c);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x4001042c);
WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL);
break;
#endif
case 2160:
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c84000);
aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0x8a46c023);
aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x0123b100);
aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x12385);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x6001042d);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x4001042d);
WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL);
break;
case 1296:
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x59c88000);
aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0xca49b022);
aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x0023b100);
aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x00012385);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x600c0436);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x400c0436);
aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x00016385);
WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL);
break;
case 1422: /* VMODE_800P */
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c8c000);
aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x4023d100);
aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0x8a7ad023);
aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x12286);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x6000043b);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x4000043b);
WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL);
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c8c40f);
break;
case 2380: /* VMODE_800X480P_60HZ */
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x59c80000);
aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0x0a563823);
aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x0123b100);
aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x12385);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x60010431);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x40010431);
WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL);
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c8c994);
break;
case 1716: /* VMODE_1366X768P_60HZ */
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c8c000);
aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x4023d100);
aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0x8a7ad023);
aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x12286);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x60000447);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x40000447);
WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL);
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c8c7f8);
break;
case 1600: /* VMODE_800X600P_60HZ */
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c8c000);
aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0x8a7ad023);
aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x4023d100);
aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x12286);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x60000442);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x40000442);
WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL);
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c8c506);
break;
case 2058: /* VMODE_1024X600P_60HZ */
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x59c80000);
aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0x0a563823);
aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x0123b100);
aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x12385);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x6001042a);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x4001042a);
WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL);
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c8cdf4);
break;
case 2600: /* VMODE_1024X768P_60HZ */
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x59c80000);
aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0x0a563823);
aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x0123b100);
aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x12385);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x60010436);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x40010436);
WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL);
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c8c294);
break;
case 1710: /* VMODE_1360X768P_60HZ */
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c8c000);
aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0x8a7ad023);
aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x4023d100);
aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x12286);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x60000447);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x40000447);
WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL);
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c8c3ac);
break;
case 2130: /* VMODE_1440X900P_60HZ */
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x59c80000);
aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0x0a563823);
aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x0123b100);
aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x12385);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x6001042c);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x4001042c);
WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL);
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c8c74f);
break;
case 2925: /* VMODE_1680X1050P_60HZ */
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x59c80000);
aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0x0a563823);
aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x0123b100);
aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x12385);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x6001043c);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x4001043c);
WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL);
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c8cfb4);
break;
case 1540: /* VMODE_1920x1200 */
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c8c2ab);
aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x4023d100);
aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0x8a7ad023);
aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x12286);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x60000440);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x40000440);
WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL);
break;
case 2014: /* VMODE_VGA */
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x59c8cf55);
aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0x0a563823);
aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x0123b100);
aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x12385);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x60010429);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x40010429);
WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL);
break;
case 1058: /* VMODE_SVGA */
WRITE_CBUS_REG(HHI_VID_PLL_CNTL, 0x422);
break;
case 1086: /* VMODE_XGA */
WRITE_CBUS_REG(HHI_VID_PLL_CNTL, 0x43e);
break;
case 1080: /* VMODE_SXGA */
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c8c000);
aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x4023d100);
aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0x8a7ad023);
aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x12286);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x6000042d);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x4000042d);
WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL);
break;
default:
printk("error hpll clk: %d\n", clk);
break;
}
if(clk < 2970)
aml_write_reg32(P_HHI_VID_PLL_CNTL5, (aml_read_reg32(P_HHI_VID_PLL_CNTL5) & (~(0xf << 12))) | (0x6 << 12));
#endif
#if MESON_CPU_TYPE == MESON_CPU_TYPE_MESON6
printk("%s[%d] clk = %d\n", __func__, __LINE__, clk);
switch(clk){
case 1488:
WRITE_CBUS_REG(HHI_VID_PLL_CNTL, 0x43e);
break;
case 1080:
WRITE_CBUS_REG(HHI_VID_PLL_CNTL, 0x42d);
break;
case 1066:
WRITE_CBUS_REG(HHI_VID_PLL_CNTL, 0x42a);
break;
case 1058:
WRITE_CBUS_REG(HHI_VID_PLL_CNTL, 0x422);
break;
case 1086:
WRITE_CBUS_REG(HHI_VID_PLL_CNTL, 0x43e);
break;
case 1296:
break;
default:
printk("error hpll clk: %d\n", clk);
break;
}
#endif
#if defined(CONFIG_MACH_MESON8B_ODROIDC)
/* Improve HDMI HPLL Long TIE
* 1296MHz is only for 480cvbs/576cvbs on m8 serials
* and is not suitable with 0x8a56d023
*
* http://forum.odroid.com/viewtopic.php?f=117&t=15860&p=104507#p104507
*/
if (voutmode_vga() && clk != 1296)
aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0x8a56d023);
#endif
printk("config HPLL done\n");
}
/* ARM Interrupt Controller Initialization */
void __init meson_init_irq(void)
{
unsigned i;
/* Disable all interrupt requests */
WRITE_CBUS_REG(A9_0_IRQ_IN0_INTR_MASK, 0);
WRITE_CBUS_REG(A9_0_IRQ_IN1_INTR_MASK, 0);
WRITE_CBUS_REG(A9_0_IRQ_IN2_INTR_MASK, 0);
WRITE_CBUS_REG(A9_0_IRQ_IN3_INTR_MASK, 0);
/* Clear all interrupts */
WRITE_CBUS_REG(A9_0_IRQ_IN0_INTR_STAT_CLR, ~0);
WRITE_CBUS_REG(A9_0_IRQ_IN1_INTR_STAT_CLR, ~0);
WRITE_CBUS_REG(A9_0_IRQ_IN2_INTR_STAT_CLR, ~0);
WRITE_CBUS_REG(A9_0_IRQ_IN3_INTR_STAT_CLR, ~0);
/* Set all interrupts to IRQ */
WRITE_CBUS_REG(A9_0_IRQ_IN0_INTR_FIRQ_SEL, 0);
WRITE_CBUS_REG(A9_0_IRQ_IN1_INTR_FIRQ_SEL, 0);
WRITE_CBUS_REG(A9_0_IRQ_IN2_INTR_FIRQ_SEL, 0);
WRITE_CBUS_REG(A9_0_IRQ_IN3_INTR_FIRQ_SEL, 0);
/* set up genirq dispatch */
for (i = 0; i < NR_IRQS; i++) {
set_irq_chip(i, &meson_irq_chip);
set_irq_handler(i, handle_level_irq);
set_irq_flags(i, IRQF_VALID);
}
}
void set_vmode_clk(vmode_t mode)
{
enc_clk_val_t *p_enc =NULL;
int i = 0;
int j = 0;
mutex_lock(&setclk_mutex);
if(IS_MESON_M8M2_CPU){
p_enc=&setting_enc_clk_val_m8m2[0];
i = sizeof(setting_enc_clk_val_m8m2) / sizeof(enc_clk_val_t);
}else{
p_enc=&setting_enc_clk_val[0];
i = sizeof(setting_enc_clk_val) / sizeof(enc_clk_val_t);
}
printk("mode is: %d\n", mode);
for (j = 0; j < i; j++){
if(mode == p_enc[j].mode)
break;
}
set_viu_path(p_enc[j].viu_path, p_enc[j].viu_type);
set_hpll_clk_out(p_enc[j].hpll_clk_out);
#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8
set_hpll_lvds_od(p_enc[j].hpll_lvds_od);
#endif
mutex_unlock(&setclk_mutex);
set_hpll_hdmi_od(p_enc[j].hpll_hdmi_od);
#if MESON_CPU_TYPE == MESON_CPU_TYPE_MESON8B
if((mode == VMODE_800X600P_60HZ) || (mode == VMODE_1024X600P_60HZ) || (mode == VMODE_1024X768P_60HZ))
aml_set_reg32_bits(P_HHI_VID_PLL_CNTL, 2, 18, 2);
#endif
set_vid_pll_div(p_enc[j].vid_pll_div);
set_clk_final_div(p_enc[j].clk_final_div);
set_hdmi_tx_pixel_div(p_enc[j].hdmi_tx_pixel_div);
set_encp_div(p_enc[j].encp_div);
set_enci_div(p_enc[j].enci_div);
set_enct_div(p_enc[j].enct_div);
set_encl_div(p_enc[j].encl_div);
set_vdac0_div(p_enc[j].vdac0_div);
set_vdac1_div(p_enc[j].vdac1_div);
#if MESON_CPU_TYPE == MESON_CPU_TYPE_MESON6
// If VCO outputs 1488, then we will reset it to exact 1485
// please note, don't forget to re-config CNTL3/4
if(((READ_CBUS_REG(HHI_VID_PLL_CNTL) & 0x7fff) == 0x43e)||((READ_CBUS_REG(HHI_VID_PLL_CNTL) & 0x7fff) == 0x21ef)) {
WRITE_CBUS_REG_BITS(HHI_VID_PLL_CNTL, 0x21ef, 0, 14);
WRITE_CBUS_REG(HHI_VID_PLL_CNTL3, 0x4b525012);
WRITE_CBUS_REG(HHI_VID_PLL_CNTL4, 0x42000101);
}
#endif
// For debug only
#if 0
printk("hdmi debug tag\n%s\n%s[%d]\n", __FILE__, __FUNCTION__, __LINE__);
#define P(a) printk("%s 0x%04x: 0x%08x\n", #a, a, READ_CBUS_REG(a))
P(HHI_VID_PLL_CNTL);
P(HHI_VID_DIVIDER_CNTL);
P(HHI_VID_CLK_CNTL);
P(HHI_VID_CLK_DIV);
P(HHI_HDMI_CLK_CNTL);
P(HHI_VIID_CLK_DIV);
#define PP(a) printk("%s(%d): %d MHz\n", #a, a, clk_util_clk_msr(a))
PP(CTS_PWM_A_CLK );
PP(CTS_PWM_B_CLK );
PP(CTS_PWM_C_CLK );
PP(CTS_PWM_D_CLK );
PP(CTS_ETH_RX_TX );
PP(CTS_PCM_MCLK );
PP(CTS_PCM_SCLK );
PP(CTS_VDIN_MEAS_CLK );
PP(CTS_VDAC_CLK1 );
PP(CTS_HDMI_TX_PIXEL_CLK);
PP(CTS_MALI_CLK );
PP(CTS_SDHC_CLK1 );
PP(CTS_SDHC_CLK0 );
PP(CTS_AUDAC_CLKPI );
PP(CTS_A9_CLK );
PP(CTS_DDR_CLK );
PP(CTS_VDAC_CLK0 );
PP(CTS_SAR_ADC_CLK );
PP(CTS_ENCI_CLK );
PP(SC_CLK_INT );
PP(USB_CLK_12MHZ );
PP(LVDS_FIFO_CLK );
PP(HDMI_CH3_TMDSCLK );
PP(MOD_ETH_CLK50_I );
PP(MOD_AUDIN_AMCLK_I );
PP(CTS_BTCLK27 );
PP(CTS_HDMI_SYS_CLK );
PP(CTS_LED_PLL_CLK );
PP(CTS_VGHL_PLL_CLK );
PP(CTS_FEC_CLK_2 );
PP(CTS_FEC_CLK_1 );
PP(CTS_FEC_CLK_0 );
PP(CTS_AMCLK );
PP(VID2_PLL_CLK );
PP(CTS_ETH_RMII );
PP(CTS_ENCT_CLK );
PP(CTS_ENCL_CLK );
PP(CTS_ENCP_CLK );
PP(CLK81 );
PP(VID_PLL_CLK );
PP(AUD_PLL_CLK );
PP(MISC_PLL_CLK );
PP(DDR_PLL_CLK );
PP(SYS_PLL_CLK );
PP(AM_RING_OSC_CLK_OUT1 );
PP(AM_RING_OSC_CLK_OUT0 );
#endif
}
void cooling(void)
{
int i;
unsigned int tmp_data;
static struct meson_pm_config aml_pm_pdata = {
.pctl_reg_base = (void *)IO_APB_BUS_BASE,
.mmc_reg_base = (void *)APB_REG_ADDR(0x1000),
.hiu_reg_base = (void *)CBUS_REG_ADDR(0x1000),
.power_key = (1<<15),
.ddr_clk = 0x00120234, // 312m, 0x00110220, //384m
.sleepcount = 128,
//.set_vccx2 = set_vccx2, //Elvis Fool
.core_voltage_adjust = 5,
};
tvin_powerdown();
writel(0,P_WATCHDOG_TC);//disable Watchdog
//amp reset down GPIOX_51
clrbits_le32(P_PREG_FGPIO_O, 1<<19);
clrbits_le32(P_PREG_FGPIO_EN_N, 1<<19);
__udelay(1000);
//USB_PWR_CTL down x44
clrbits_le32(P_PREG_FGPIO_O, 1<<12);
clrbits_le32(P_PREG_FGPIO_EN_N, 1<<12);
//mute down x69
setbits_le32(P_PREG_GGPIO_O, 1<<5);
clrbits_le32(P_PREG_GGPIO_EN_N, 1<<5);
for(i=0; i<100; i++)
{
__udelay(1000);
}
//GPIOX_53 reset chip power ctrl BL_EN
setbits_le32(P_PREG_FGPIO_O, 1<<21);
clrbits_le32(P_PREG_FGPIO_EN_N, 1<<21);
//pwm x55
clrbits_le32(P_PREG_FGPIO_O, 1<<23);
clrbits_le32(P_PREG_FGPIO_EN_N, 1<<23);
//pwm b2
setbits_le32(P_PREG_GGPIO_O, 1<<10);
clrbits_le32(P_PREG_GGPIO_EN_N, 1<<10);
//pwm b3
setbits_le32(P_PREG_GGPIO_O, 1<<11);
clrbits_le32(P_PREG_GGPIO_EN_N, 1<<11);
for(i=0; i<100; i++)
{
__udelay(1000);
}
//GPIOX_48 LED_G
clrbits_le32(P_PREG_FGPIO_O, 1<<16);
clrbits_le32(P_PREG_FGPIO_EN_N, 1<<16);
//GPIOX_56 LED_R
setbits_le32(P_PREG_FGPIO_O, 1<<24);
clrbits_le32(P_PREG_FGPIO_EN_N, 1<<24);
//vcc_12v/24v power down GPIOX_70
//clrbits_le32(P_PREG_GGPIO_O, 1<<6);
//clrbits_le32(P_PREG_GGPIO_EN_N, 1<<6);
serial_hw_init();
//setbits_le32(P_PERIPHS_PIN_MUX_2,((1<<29)|(1<<30)));
writel(0x18003033, P_UART1_CONTROL);
serial_puts("\nstandby...\n");
writel(0x209861f1, P_HHI_GCLK_MPEG0);
writel(0x208b8028, P_HHI_GCLK_MPEG1);
writel(0xfffffc07, P_HHI_GCLK_MPEG2);
writel(0xffc40021, P_HHI_GCLK_OTHER);
//analog off
WRITE_CBUS_REG(SAR_ADC_REG3, 0x3008510a);
//WRITE_CBUS_REG(VGHL_PWM_REG0, 0x0); //the same with off
//WRITE_CBUS_REG(WIFI_ADC_SAMPLING, 0x0); //the same with off
WRITE_APB_REG(ADC_EN_ADC, 0x0); //the same with off
//WRITE_AHB_REG(WIFI_ADC_DAC, 0x0); //the same with off
//WRITE_AHB_REG(ADC_EN_CMLGEN_RES, 0x0); //the same with off
//WRITE_AHB_REG(WIFI_SARADC, 0x0); //the same with off
//usb off
WRITE_CBUS_REG(PREI_USB_PHY_REG, 0x8040012b);
//clock off
//WRITE_CBUS_REG(HHI_DEMOD_CLK_CNTL, 0x400); //the same with off
//WRITE_CBUS_REG(HHI_SATA_CLK_CNTL, 0x0); //the same with off
//WRITE_CBUS_REG(HHI_ETH_CLK_CNTL, 0x207); //the same with off
//WRITE_CBUS_REG(HHI_WIFI_CLK_CNTL, 0x0); //the same with off
WRITE_CBUS_REG(HHI_VID_CLK_CNTL, 0x840e);
WRITE_CBUS_REG(HHI_AUD_CLK_CNTL, 0x800018);
WRITE_CBUS_REG(HHI_MALI_CLK_CNTL, 0x202);
WRITE_CBUS_REG(HHI_HDMI_CLK_CNTL, 0x203);
WRITE_CBUS_REG(HHI_MPEG_CLK_CNTL, 0x1083);
//pll off
WRITE_CBUS_REG(HHI_DEMOD_PLL_CNTL, 0x8232);
WRITE_CBUS_REG(HHI_VID_PLL_CNTL, 0x8641);
WRITE_CBUS_REG(HHI_AUD_PLL_CNTL, 0xca80);
WRITE_CBUS_REG(HHI_OTHER_PLL_CNTL, 0x887d);
#ifdef SYSTEM_16K
if (READ_CBUS_REG(HHI_MPEG_CLK_CNTL)&(1<<8))
CLEAR_CBUS_REG_MASK(HHI_MPEG_CLK_CNTL, (1<<8)); // clk81 = xtal
SET_CBUS_REG_MASK(HHI_MPEG_CLK_CNTL, (1<<9)); // xtal_rtc = rtc
WRITE_CBUS_REG_BITS(HHI_MPEG_CLK_CNTL, 0x1, 0, 6); // devider = 2
WRITE_CBUS_REG_BITS(HHI_MPEG_CLK_CNTL, 0, 12, 2); // clk81 src -> xtal_rtc
SET_CBUS_REG_MASK(HHI_MPEG_CLK_CNTL, (1<<8)); // clk81 = xtal_rtc / devider
#else
CLEAR_CBUS_REG_MASK(HHI_MPEG_CLK_CNTL, (1<<8)); // clk81 = xtal
WRITE_CBUS_REG_BITS(HHI_MPEG_CLK_CNTL, 0x1e, 0, 6); // devider = 30
WRITE_CBUS_REG_BITS(HHI_MPEG_CLK_CNTL, 0, 12, 2); // clk81 src -> xtal_rtc
SET_CBUS_REG_MASK(HHI_MPEG_CLK_CNTL, (1<<8)); // clk81 = xtal_rtc / devider
#endif
CLEAR_CBUS_REG_MASK(HHI_A9_CLK_CNTL, (1<<7)); // clka9 = xtal_rtc / 2
#ifdef SYSTEM_16K
SET_CBUS_REG_MASK(PREG_CTLREG0_ADDR, 1);
#endif
WRITE_CBUS_REG(HHI_A9_AUTO_CLK0,
(2 << 24) | // sleep select 1000uS timebase
(0x20 << 16) | // Set the delay wakeup time (32mS)
(0 << 5) | // don't clear the FIQ global mask
(0 << 4) | // don't clear the IRQ global mask
(2 << 2)); // Set interrupt wakeup only
WRITE_CBUS_REG(HHI_A9_AUTO_CLK1,
(0 << 20) | // start delay timebase
(1 << 12) | // 1uS enable delay
(1 << 8) | // 1uS gate delay
(1 << 0)); // 1us start delay
SET_CBUS_REG_MASK(HHI_A9_AUTO_CLK0, 1 << 0); //ENABLE: If this bit is set to 1, then the auto-clock ratio module will execute a change once the START pulses is generated.
SET_CBUS_REG_MASK(HHI_SYS_PLL_CNTL, (1<<15)); // turn off sys pll
/*
while(1)
{
if(serial_tstc()) break;
}*/
WRITE_CBUS_REG(0x2620, 0x10001);
WRITE_CBUS_REG(0x2621, 0x24);
WRITE_CBUS_REG(0x2622, 0);
WRITE_CBUS_REG(0x2623, 0);
WRITE_CBUS_REG(0x2624, 0);
enable_custom_trigger();
#ifdef CONFIG_MACH_MESON2_7366M_CST02
WRITE_CBUS_REG(A9_0_IRQ_IN2_INTR_MASK, 1); //enable gpio interrupt
#endif
#ifdef CONFIG_MACH_MESON2_7366M_REFE03
WRITE_CBUS_REG(A9_0_IRQ_IN2_INTR_MASK, 1); //enable gpio interrupt
#endif
tmp_data = READ_CBUS_REG(PREG_CTLREG0_ADDR);
WRITE_CBUS_REG(PREG_CTLREG0_ADDR, tmp_data | 0x1);
tmp_data = READ_CBUS_REG(IR_DEC_REG0);
WRITE_CBUS_REG(IR_DEC_REG0, tmp_data & 0xFFFFFF00);
tmp_data = READ_CBUS_REG(IR_DEC_REG1);
WRITE_CBUS_REG(IR_DEC_REG1, tmp_data | 0x00000001);
WRITE_CBUS_REG(IR_DEC_REG1, tmp_data & 0xFFFFFFFE);
//hub reset down x50
clrbits_le32(P_PREG_FGPIO_O, 1<<18);
clrbits_le32(P_PREG_FGPIO_EN_N, 1<<18);
//GPIOX_32 si2176_RESET down
clrbits_le32(P_PREG_FGPIO_O, 1<<0);
clrbits_le32(P_PREG_FGPIO_EN_N, 1<<0);
//PHY_RESET x57
clrbits_le32(P_PREG_FGPIO_O, 1<<25);
clrbits_le32(P_PREG_FGPIO_EN_N, 1<<25);
//close ddr
//gpiob_8
setbits_le32(P_PREG_GGPIO_O, 1<<16);
clrbits_le32(P_PREG_GGPIO_EN_N, 1<<16);
//gpiob_5
setbits_le32(P_PREG_GGPIO_O, 1<<13);
clrbits_le32(P_PREG_GGPIO_EN_N, 1<<13);
//gpiob_6
//setbits_le32(P_PREG_GGPIO_O, 1<<14);
//clrbits_le32(P_PREG_GGPIO_EN_N, 1<<14);
for(i=0; i<100; i++)
{
__udelay(1000);
}
meson_cpu_suspend(aml_pm_pdata);
for(i=0; i<100; i++)
{
__udelay(1000);
}
//GPIOX_54 reset chip panel power
clrbits_le32(P_PREG_FGPIO_O, 1<<22);
clrbits_le32(P_PREG_FGPIO_EN_N, 1<<22);
//pwm x55
setbits_le32(P_PREG_FGPIO_O, 1<<23);
clrbits_le32(P_PREG_FGPIO_EN_N, 1<<23);
//pwm b2
clrbits_le32(P_PREG_GGPIO_O, 1<<10);
clrbits_le32(P_PREG_GGPIO_EN_N, 1<<10);
//pwm b3
clrbits_le32(P_PREG_GGPIO_O, 1<<11);
clrbits_le32(P_PREG_GGPIO_EN_N, 1<<11);
for(i=0; i<300; i++)
{
__udelay(1000);
}
//vcc_12v/24v power on
setbits_le32(P_PREG_GGPIO_O, 1<<6);
clrbits_le32(P_PREG_GGPIO_EN_N, 1<<6);
//setbits_le32(P_PREG_GGPIO_EN_N, 1<<6);
for(i=0; i<800; i++)
{
__udelay(1000);
}
//GPIOX_53 reset chip power ctrl
//setbits_le32(P_PREG_FGPIO_O, 1<<21);
memory_pll_init(0,NULL);
serial_puts("\ngate clock on...\n");
writel(0xffffffff, P_HHI_GCLK_MPEG0);
writel(0xffffffff, P_HHI_GCLK_MPEG1);
writel(0xffffffff, P_HHI_GCLK_MPEG2);
writel(0xffffffff, P_HHI_GCLK_OTHER);
#if 0
//analog on
WRITE_CBUS_REG(SAR_ADC_REG3, 0x2008510a);
//WRITE_CBUS_REG(VGHL_PWM_REG0, 0x0); //the same with off
//WRITE_CBUS_REG(WIFI_ADC_SAMPLING, 0x0); //the same with off
//WRITE_APB_REG(ADC_EN_ADC, 0x0); //the same with off
//WRITE_AHB_REG(WIFI_ADC_DAC, 0x0); //the same with off
//WRITE_AHB_REG(ADC_EN_CMLGEN_RES, 0x0); //the same with off
//WRITE_AHB_REG(WIFI_SARADC, 0x0); //the same with off
//usb on
WRITE_CBUS_REG(PREI_USB_PHY_REG, 0x80400128);
//clock on
//WRITE_CBUS_REG(HHI_DEMOD_CLK_CNTL, 0x400); //the same with off
//WRITE_CBUS_REG(HHI_SATA_CLK_CNTL, 0x0); //the same with off
//WRITE_CBUS_REG(HHI_ETH_CLK_CNTL, 0x207); //the same with off
//WRITE_CBUS_REG(HHI_WIFI_CLK_CNTL, 0x0); //the same with off
WRITE_CBUS_REG(HHI_VID_CLK_CNTL, 0x840f);
WRITE_CBUS_REG(HHI_AUD_CLK_CNTL, 0x800018);
WRITE_CBUS_REG(HHI_MALI_CLK_CNTL, 0x302);
WRITE_CBUS_REG(HHI_HDMI_CLK_CNTL, 0x303);
WRITE_CBUS_REG(HHI_MPEG_CLK_CNTL, 0x1183);
//pll on
WRITE_CBUS_REG(HHI_DEMOD_PLL_CNTL, 0x232);
WRITE_CBUS_REG(HHI_VID_PLL_CNTL, 0x641);
WRITE_CBUS_REG(HHI_AUD_PLL_CNTL, 0x4a80);
//WRITE_CBUS_REG(HHI_OTHER_PLL_CNTL, 0x87d);
#endif
return 0;
}
/*
* rc 0x12345678
* rw 0x12345678 1234
* adress must be hexadecimal and prefix with ox.
*/
ssize_t vdin_dbg_store(struct device *dev,
struct device_attribute *attr, const char *buf, size_t count)
{
char strcmd[16];
char straddr[10];
char strval[32];
int i = 0;
int j = 0;
unsigned long addr;
unsigned int value=0;
unsigned int retval;
/* get parameter command string */
j = 0;
while( (i < count) && (buf[i]) && (buf[i] != ',') && (buf[i] != ' ') && (buf[i] != 10)){
strcmd[j] = buf[i];
i++;
j++;
}
strcmd[j] = '\0';
/* ignore */
while( (i < count) && (buf[i]) && ((buf[i] ==',') || (buf[i] == ' ') || (buf[i] == 10))){
i++;
}
/* check address */
if (strncmp(&buf[i], "0x", 2) != 0){
pr_info("invalid parameter address\n");
tvin_dbg_usage();
return 32;
}
/* get parameter address string */
j = 0;
while( (i < count) && (buf[i]) && (buf[i] != ',') && (buf[i] != ' ' && (buf[i] != 10))){
straddr[j] = buf[i];
i++;
j++;
}
straddr[j] = 0;
addr = simple_strtoul(straddr, NULL, 16); //hex data
/* rc read cbus */
if (strncmp(strcmd, "rc", 2) == 0){
retval = READ_CBUS_REG(addr);
pr_info("%s: 0x%x --> 0x%x\n", strcmd, addr, retval);
return 32;
}
/* rp read apb */
else if (strncmp(strcmd, "rp", 2) == 0){
retval = READ_APB_REG(addr);
pr_info("%s: 0x%x --> 0x%x\n", strcmd, addr, retval);
return 32;
}
/* wc write cbus */
else if (strncmp(strcmd, "wc", 2) == 0){
/* get parameter value string*/
/* ignore */
while( (i < count) && (buf[i]) && ((buf[i] ==',') || (buf[i] == ' ') || (buf[i] == 10))){
i++;
}
if (!buf[i]){
pr_info("no parameter value\n");
tvin_dbg_usage();
return 32;
}
j = 0;
while( (i < count) && (buf[i]) && (buf[i] != ',') && (buf[i] != ' ')&& (buf[i] != 10)){
strval[j] = buf[i];
i++;
j++;
}
strval[j] = '\0';
value = simple_strtol(strval, NULL, 16); //hex data
WRITE_CBUS_REG(addr, value);
pr_info("%s: 0x%x <-- 0x%x\n", strcmd, addr, value);
return 32;
}
/* wp write apb */
else if (strncmp(strcmd, "wp", 2) == 0){
/* get parameter value string*/
/* ignore */
while( (i < count) && (buf[i]) && ((buf[i] ==',') || (buf[i] == ' ') || (buf[i] == 10))){
i++;
}
if (!buf[i]){
pr_info("no parameter value\n");
tvin_dbg_usage();
return 32;
}
j = 0;
while( (i < count) && (buf[i]) && (buf[i] != ',') && (buf[i] != ' ')&& (buf[i] != 10)){
strval[j] = buf[i];
i++;
j++;
}
strval[j] = '\0';
value = simple_strtol(strval, NULL, 16); //hex data
WRITE_APB_REG(addr, value);
pr_info("%s: 0x%x <-- 0x%x\n", strcmd, addr, value);
return 32;
}
else{
pr_info("invalid parameter\n");
tvin_dbg_usage();
return 32;
}
return 32;
}
/*
* set watchdog timer timeout.
* the watchdog timer issues a chip reset when the watchdog timer timeout.
* @timeout watchdog reset timeout in second
* @todo timeout limits supported.
*/
static inline void aml_wdt_settimeout(unsigned int timeout)
{
unsigned int enable = READ_CBUS_REG_BITS(WATCHDOG_TC, WATCHDOG_ENABLE_BIT, 1);
WRITE_CBUS_REG(WATCHDOG_RESET, 0);
WRITE_CBUS_REG(WATCHDOG_TC, (enable << WATCHDOG_ENABLE_BIT) | (0x186a0 * timeout));
}
static int sd_request(struct memory_card *card, struct card_blk_request *brq)
{
SD_MMC_Card_Info_t *sd_mmc_info = (SD_MMC_Card_Info_t *)card->card_info;
unsigned int lba, byte_cnt,ret;
unsigned char *data_buf;
struct card_host *host = card->host;
struct memory_card *sdio_card;
SD_MMC_Card_Info_t *sdio_info;
lba = brq->card_data.lba;
byte_cnt = brq->card_data.blk_size * brq->card_data.blk_nums;
data_buf = brq->crq.buf;
if(sd_mmc_info == NULL){
brq->card_data.error = SD_MMC_ERROR_NO_CARD_INS;
printk("[sd_request] sd_mmc_info == NULL, return SD_MMC_ERROR_NO_CARD_INS\n");
return 0;
}
if(!sd_mmc_info->blk_len){
card->card_io_init(card);
card->card_detector(card);
if(card->card_status == CARD_REMOVED){
brq->card_data.error = SD_MMC_ERROR_NO_CARD_INS;
return 0;
}
#if MESON_CPU_TYPE == MESON_CPU_TYPE_MESON6
switch_mod_gate_by_type(MOD_SDIO,1);
#endif
ret = sd_mmc_init(sd_mmc_info);
#if MESON_CPU_TYPE == MESON_CPU_TYPE_MESON6
switch_mod_gate_by_type(MOD_SDIO,0);
#endif
if(ret){
brq->card_data.error = SD_MMC_ERROR_NO_CARD_INS;
return 0;
}
}
#if MESON_CPU_TYPE == MESON_CPU_TYPE_MESON6
switch_mod_gate_by_type(MOD_SDIO,1);
#endif
sdio_card = card_find_card(host, CARD_SDIO);
if (sdio_card) {
sdio_close_host_interrupt(SDIO_IF_INT);
sdio_info = (SD_MMC_Card_Info_t *)sdio_card->card_info;
sd_gpio_enable(sdio_info->io_pad_type);
}
sd_sdio_enable(sd_mmc_info->io_pad_type);
if(brq->crq.cmd == READ) {
brq->card_data.error = sd_mmc_read_data(sd_mmc_info, lba, byte_cnt, data_buf);
}
else if(brq->crq.cmd == WRITE) {
brq->card_data.error = sd_mmc_write_data(sd_mmc_info, lba, byte_cnt, data_buf);
}
sd_gpio_enable(sd_mmc_info->io_pad_type);
if(brq->card_data.error == SD_WAIT_FOR_COMPLETION_TIMEOUT)
{
printk("[sd_request] wait for completion timeout, reinit\n");
card->card_io_init(card);
card->card_detector(card);
if(card->card_status == CARD_REMOVED){
printk("[sd_request] card removed\n");
brq->card_data.error = SD_MMC_ERROR_NO_CARD_INS;
return 0;
}
sd_mmc_staff_init(sd_mmc_info);
ret = sd_mmc_init(sd_mmc_info);
if(ret){
printk("[sd_request] reinit fail %d\n", ret);
brq->card_data.error = SD_MMC_ERROR_NO_CARD_INS;
return 0;
}
sd_sdio_enable(sd_mmc_info->io_pad_type);
if(brq->crq.cmd == READ) {
brq->card_data.error = sd_mmc_read_data(sd_mmc_info, lba, byte_cnt, data_buf);
}
else if(brq->crq.cmd == WRITE) {
brq->card_data.error = sd_mmc_write_data(sd_mmc_info, lba, byte_cnt, data_buf);
}
sd_gpio_enable(sd_mmc_info->io_pad_type);
if(brq->card_data.error == SD_WAIT_FOR_COMPLETION_TIMEOUT)
printk("[sd_request] after reinit still error \n");
}
sdio_card = card_find_card(host, CARD_SDIO);
if(sdio_card) {
sdio_info = (SD_MMC_Card_Info_t *)sdio_card->card_info;
sd_sdio_enable(sdio_info->io_pad_type);
if (sdio_info->sd_save_hw_io_flag) {
WRITE_CBUS_REG(SDIO_CONFIG, sdio_info->sd_save_hw_io_config);
WRITE_CBUS_REG(SDIO_MULT_CONFIG, sdio_info->sd_save_hw_io_mult_config);
}
sdio_open_host_interrupt(SDIO_IF_INT);
}
#if MESON_CPU_TYPE == MESON_CPU_TYPE_MESON6
switch_mod_gate_by_type(MOD_SDIO,0);
#endif
return 0;
}
void mali_meson_poweron(void)
{
unsigned long flags;
u32 p, p_aligned;
dma_addr_t p_phy;
int i;
unsigned int_mask;
if ((last_power_mode != -1) && (last_power_mode != MALI_POWER_MODE_DEEP_SLEEP)) {
return;
}
if (READ_MALI_REG(MALI_PP_PP_VERSION) != MALI_PP_PP_VERSION_MAGIC) {
printk("mali_meson_poweron: Mali APB bus access failed.");
return;
}
if (READ_MALI_REG(MALI_MMU_DTE_ADDR) != 0) {
printk("mali_meson_poweron: Mali is not really powered off.");
return;
}
p = (u32)kcalloc(4096 * 4, 1, GFP_KERNEL);
if (!p) {
printk("mali_meson_poweron: NOMEM in meson_poweron\n");
return;
}
p_aligned = __ALIGN_MASK(p, 4096);
/* DTE */
*(u32 *)(p_aligned) = (virt_to_phys((void *)p_aligned) + OFFSET_MMU_PTE) | MMU_FLAG_DTE_PRESENT;
/* PTE */
for (i=0; i<1024; i++) {
*(u32 *)(p_aligned + OFFSET_MMU_PTE + i*4) =
(virt_to_phys((void *)p_aligned) + OFFSET_MMU_VIRTUAL_ZERO + 4096 * i) |
MMU_FLAG_PTE_PAGE_PRESENT |
MMU_FLAG_PTE_RD_PERMISSION;
}
/* command & data */
memcpy((void *)(p_aligned + OFFSET_MMU_VIRTUAL_ZERO), poweron_data, 4096);
p_phy = dma_map_single(NULL, (void *)p_aligned, 4096 * 3, DMA_TO_DEVICE);
/* Set up Mali GP MMU */
WRITE_MALI_REG(MALI_MMU_DTE_ADDR, p_phy);
WRITE_MALI_REG(MALI_MMU_CMD, 0);
if ((READ_MALI_REG(MALI_MMU_STATUS) & 1) != 1) {
printk("mali_meson_poweron: MMU enabling failed.\n");
}
/* Set up Mali command registers */
WRITE_MALI_REG(MALI_APB_GP_VSCL_START, 0);
WRITE_MALI_REG(MALI_APB_GP_VSCL_END, 0x38);
WRITE_MALI_REG(MALI_APB_GP_INT_MASK, 0x3ff);
spin_lock_irqsave(&lock, flags);
int_mask = READ_CBUS_REG(A9_0_IRQ_IN1_INTR_MASK);
/* Set up ARM Mali interrupt */
WRITE_CBUS_REG(A9_0_IRQ_IN1_INTR_STAT_CLR, 1 << 16);
SET_CBUS_REG_MASK(A9_0_IRQ_IN1_INTR_MASK, 1 << 16);
/* Start GP */
WRITE_MALI_REG(MALI_APB_GP_CMD, 1);
for (i = 0; i<100; i++)
udelay(500);
/* check Mali GP interrupt */
if (READ_CBUS_REG(A9_0_IRQ_IN1_INTR_STAT) & (1<<16)) {
printk("mali_meson_poweron: Interrupt received.\n");
} else {
printk("mali_meson_poweron: No interrupt received.\n");
}
WRITE_CBUS_REG(A9_0_IRQ_IN1_INTR_STAT_CLR, 1 << 16);
CLEAR_CBUS_REG_MASK(A9_0_IRQ_IN1_INTR_MASK, 1 << 16);
/* force reset GP */
WRITE_MALI_REG(MALI_APB_GP_CMD, 1 << 5);
/* stop MMU paging and reset */
WRITE_MALI_REG(MALI_MMU_CMD, 1);
WRITE_MALI_REG(MALI_MMU_CMD, 1 << 6);
WRITE_CBUS_REG(A9_0_IRQ_IN1_INTR_MASK, int_mask);
spin_unlock_irqrestore(&lock, flags);
dma_unmap_single(NULL, p_phy, 4096 * 3, DMA_TO_DEVICE);
kfree((void *)p);
}
void enable_vdin_pinmux(void)
{
// disable LCD pinmux
WRITE_CBUS_REG(PERIPHS_PIN_MUX_0, READ_CBUS_REG(PERIPHS_PIN_MUX_0) &
( ~(1 | // LCD_R 2/3/4/5/6/7
(1 << 1) | // LCD_R 0/1
(1 << 2) | // LCD_G 2/3/4/5/6/7
(1 << 3) | // LCD_G 0/1
(1 << 4) | // LCD_B 2/3/4/5/6/7
(1 << 5) | // LCD_B 0/1
(1 << 18) | // LCD_HS
(1 << 19)) ) // LCD_VS
);
// disable TCON pinmux
WRITE_CBUS_REG(PERIPHS_PIN_MUX_8, READ_CBUS_REG(PERIPHS_PIN_MUX_8) &
( ~((1 << 19) | // TCON_VCOM
(1 << 20) | // TCON_CPH3
(1 << 21) | // TCON_CPH2
(1 << 22) | // TCON_CPH1
(1 << 23) | // TCON_STH1
(1 << 24) | // TCON_STV1
(1 << 25) | // TCON_CPV
(1 << 26) | // TCON_VCOM
(1 << 27) | // TCON_OEV
(1 << 28)) ) // TCON_OEH
);
// disable ENC pinmux
WRITE_CBUS_REG(PERIPHS_PIN_MUX_7, READ_CBUS_REG(PERIPHS_PIN_MUX_7) &
( ~(1 | // ENC_0
(1 << 1) | // ENC_1
(1 << 2) | // ENC_2
(1 << 3) | // ENC_3
(1 << 4) | // ENC_4
(1 << 5) | // ENC_5
(1 << 6) | // ENC_6
(1 << 7) | // ENC_7
(1 << 8) | // ENC_8
(1 << 9) | // ENC_9
(1 << 10) | // ENC_10
(1 << 11) | // ENC_11
(1 << 12) | // ENC_12
(1 << 13) | // ENC_13
(1 << 14) | // ENC_14
(1 << 15) | // ENC_15
(1 << 16) | // ENC_16(eNet_0)
(1 << 17)) ) // ENC_17(eNet_1)
);
// disable PWM pinmux
WRITE_CBUS_REG(PERIPHS_PIN_MUX_3, READ_CBUS_REG(PERIPHS_PIN_MUX_3) &
( ~((1 << 24) | // PWM_C
(1 << 25) | // PWM_C
(1 << 26))) // PWM_D
);
WRITE_CBUS_REG(PERIPHS_PIN_MUX_7, READ_CBUS_REG(PERIPHS_PIN_MUX_7) &
( ~((1 << 26) | // PWM_VS
(1 << 27) | // PWM_VS
(1 << 28))) // PWM_VS
);
// disable VGA pinmux
WRITE_CBUS_REG(PERIPHS_PIN_MUX_0, READ_CBUS_REG(PERIPHS_PIN_MUX_0) &
( ~((1 << 20) | // VGA_HS
(1 << 21))) // VGA_VS
);
// enable DVIN pinmux
WRITE_CBUS_REG(PERIPHS_PIN_MUX_0, READ_CBUS_REG(PERIPHS_PIN_MUX_0) |
( (1 << 6) | // DVIN R/G/B 0/1/2/3/4/5/6/7
(1 << 7) | // DVIN_CLK
(1 << 8) | // DVIN_HS
(1 << 9) | // DVIN_VS
(1 << 10)) // DVIN_DE
);
}
void tvafe_adc_configure(enum tvin_sig_fmt_e fmt)
{
int i = 0;
const unsigned char *buff_t = NULL;
/*adc reset*/
tvafe_adc_clear(TVAFE_ADC_CONFIGURE_INIT, 1);
tvafe_adc_clear(TVAFE_ADC_CONFIGURE_NORMAL, 1);
tvafe_adc_clear(TVAFE_ADC_CONFIGURE_RESET_ON, 1);
if (fmt < TVIN_SIG_FMT_VGA_MAX && fmt > TVIN_SIG_FMT_NULL) // VGA formats
{
buff_t = adc_vga_table[fmt-TVIN_SIG_FMT_VGA_512X384P_60HZ_D147];
}
else if (fmt < TVIN_SIG_FMT_COMP_MAX && fmt > TVIN_SIG_FMT_VGA_THRESHOLD) // Component formats
{
buff_t = adc_component_table[fmt-TVIN_SIG_FMT_COMP_480P_60HZ_D000];
}
// CVBS formats
else if(fmt < TVIN_SIG_FMT_CVBS_MAX && fmt > TVIN_SIG_FMT_HDMI_THRESHOLD)
{
buff_t = adc_cvbs_table;
}
else
{
pr_err("[tvafe..]%s: invaild fmt %s.\n",__func__,tvin_sig_fmt_str(fmt));
return;
}
for (i=0; i<ADC_REG_NUM; i++)
{
WRITE_APB_REG(((ADC_BASE_ADD+i)<<2), (unsigned int)(buff_t[i]));
}
//set componet different phase base on board design
if(fmt > TVIN_SIG_FMT_VGA_MAX && fmt < TVIN_SIG_FMT_COMP_MAX && enable_dphase)
{
WRITE_APB_REG_BITS(ADC_REG_56, comp_phase[fmt-TVIN_SIG_FMT_VGA_THRESHOLD -1],CLKPHASEADJ_BIT,CLKPHASEADJ_WID);
}
//for adc calibration clamping duration setting
if (fmt < TVIN_SIG_FMT_COMP_MAX)
{
tvafe_adc_set_clamp_para(fmt);
}
/* adc config normal */
tvafe_adc_clear(TVAFE_ADC_CONFIGURE_NORMAL, 0);
#ifdef TVAFE_DEBUG_PIN_ENABLE
//debug setting
// diable other mux on test pins 0~27 & 30
WRITE_CBUS_REG(PERIPHS_PIN_MUX_0 , READ_CBUS_REG(PERIPHS_PIN_MUX_0 )&0xcff0ffdf);
WRITE_CBUS_REG(PERIPHS_PIN_MUX_1 , READ_CBUS_REG(PERIPHS_PIN_MUX_1 )&0xfc017fff);
WRITE_CBUS_REG(PERIPHS_PIN_MUX_2 , READ_CBUS_REG(PERIPHS_PIN_MUX_2 )&0xe001ffff);
WRITE_CBUS_REG(PERIPHS_PIN_MUX_3 , READ_CBUS_REG(PERIPHS_PIN_MUX_3 )&0xfc000000);
WRITE_CBUS_REG(PERIPHS_PIN_MUX_4 , READ_CBUS_REG(PERIPHS_PIN_MUX_4 )&0xff8007ff);
WRITE_CBUS_REG(PERIPHS_PIN_MUX_6 , READ_CBUS_REG(PERIPHS_PIN_MUX_6 )&0xffffffbf);
WRITE_CBUS_REG(PERIPHS_PIN_MUX_7 , READ_CBUS_REG(PERIPHS_PIN_MUX_7 )&0xff00003f);
WRITE_CBUS_REG(PERIPHS_PIN_MUX_10, READ_CBUS_REG(PERIPHS_PIN_MUX_10)&0xffffffb3);
// enable TVFE_TEST mux on test pins 0~27 & 30
WRITE_CBUS_REG(PERIPHS_PIN_MUX_9 , 0x4fffffff);//
#endif
}
/*************************************************
* Amlogic Ethernet controller operation
*
* Note: RTL8211F gbit_phy use RGMII interface
*
*************************************************/
static void setup_net_chip(void)
{
eth_aml_reg0_t eth_reg0;
/*m8b mac clock use externel phy clock(125m/25m/2.5m)
setup ethernet clk need calibrate to configre
setup ethernet pinmux use DIF_TTL_0N/P 1N/P 2N/P 3N/P 4N/P GPIOH(3-9) */
#ifdef RMII_PHY_INTERFACE
/* setup ethernet pinmux use gpioz(5-14) */
SET_CBUS_REG_MASK(PERIPHS_PIN_MUX_6,0xff7f);
SET_CBUS_REG_MASK(PERIPHS_PIN_MUX_7,0xf00000);
eth_reg0.d32 = 0;
eth_reg0.b.phy_intf_sel = 0;
eth_reg0.b.data_endian = 0;
eth_reg0.b.desc_endian = 0;
eth_reg0.b.rx_clk_rmii_invert = 0;
eth_reg0.b.rgmii_tx_clk_src = 0;
eth_reg0.b.rgmii_tx_clk_phase = 0;
eth_reg0.b.rgmii_tx_clk_ratio = 1;
eth_reg0.b.phy_ref_clk_enable = 1;
eth_reg0.b.clk_rmii_i_invert = 1;
eth_reg0.b.clk_en = 1;
eth_reg0.b.adj_enable = 1;
eth_reg0.b.adj_setup = 0;
eth_reg0.b.adj_delay = 18;
eth_reg0.b.adj_skew = 0;
eth_reg0.b.cali_start = 0;
eth_reg0.b.cali_rise = 0;
eth_reg0.b.cali_sel = 0;
eth_reg0.b.rgmii_rx_reuse = 0;
eth_reg0.b.eth_urgent = 0;
WRITE_CBUS_REG(PREG_ETHERNET_ADDR0, eth_reg0.d32 );//1 //rmii mode
WRITE_CBUS_REG(0x2050,0x1000);//1 //rmii mode
#elif RGMII_PHY_INTERFACE
SET_CBUS_REG_MASK(PERIPHS_PIN_MUX_6, 0xffff);
eth_reg0.d32 = 0;
eth_reg0.b.phy_intf_sel = 1;
eth_reg0.b.data_endian = 0;
eth_reg0.b.desc_endian = 1;
eth_reg0.b.rx_clk_rmii_invert = 0;
eth_reg0.b.rgmii_tx_clk_src = 0;
eth_reg0.b.rgmii_tx_clk_phase = 0;
eth_reg0.b.rgmii_tx_clk_ratio = 2;
eth_reg0.b.phy_ref_clk_enable = 1;
eth_reg0.b.clk_rmii_i_invert = 1;
eth_reg0.b.clk_en = 1;
eth_reg0.b.adj_enable = 1;
eth_reg0.b.adj_setup = 1;
eth_reg0.b.adj_delay = 4;
eth_reg0.b.adj_skew = 0xc;
eth_reg0.b.cali_start = 0;
eth_reg0.b.cali_rise = 0;
eth_reg0.b.cali_sel = 0;
eth_reg0.b.rgmii_rx_reuse = 0;
eth_reg0.b.eth_urgent = 0;
WRITE_CBUS_REG(PREG_ETHERNET_ADDR0, eth_reg0.d32);// rgmii mode
#endif
/* setup ethernet mode */
CLEAR_CBUS_REG_MASK(HHI_MEM_PD_REG0, (1 << 3) | (1<<2));
/* hardware reset ethernet phy : gpioh_4 connect phyreset pin*/
CLEAR_CBUS_REG_MASK(PREG_PAD_GPIO3_EN_N, 1 << 23);
CLEAR_CBUS_REG_MASK(PREG_PAD_GPIO3_O, 1 << 23);
udelay(2000);
SET_CBUS_REG_MASK(PREG_PAD_GPIO3_O, 1 << 23);
}
/*
* writing with any value will reset the internal counter
* of the watchdog timer to zero.
* this will be used to pet the watchdog.
*/
static inline void aml_wdt_keepalive(void)
{
WRITE_CBUS_REG(WATCHDOG_RESET, 0);
}
