static void Parallel_putchar(unsigned char ch)
/*
* FUNCTION: Writes a character to the parallel port
* ARGUMENTS:
* ch = character to write
*/
{
int count=0;
int status;
int wait=0;
do
{
status=LP_S;
count++;
}
while ( count < 500000 && !(status & LP_PBUSY) );
if (count==500000)
{
DPRINT("printer_putchar(): timed out\n");
return;
}
WRITE_PORT_UCHAR((PUCHAR)LP_B,ch);
while (wait != 10000) { wait++; }
WRITE_PORT_UCHAR((PUCHAR)LP_C, (LP_PSELECP | LP_PINITP | LP_PSTROBE ));
while (wait) { wait--; }
WRITE_PORT_UCHAR((PUCHAR)LP_C, LP_PSELECP | LP_PINITP);
}
static __inline
void
setCx86(UCHAR reg, UCHAR data)
{
WRITE_PORT_UCHAR((PUCHAR)(ULONG_PTR)0x22, reg);
WRITE_PORT_UCHAR((PUCHAR)(ULONG_PTR)0x23, data);
}
BOOLEAN
NTAPI
HalEnableSystemInterrupt(
ULONG Vector,
KIRQL Irql,
KINTERRUPT_MODE InterruptMode)
{
ULONG irq;
if (Vector < IRQ_BASE || Vector >= IRQ_BASE + NR_IRQS)
return FALSE;
irq = Vector - IRQ_BASE;
pic_mask.both &= ~(1 << irq);
if (irq < 8)
{
WRITE_PORT_UCHAR((PUCHAR)0x21, (UCHAR)(pic_mask.master|pic_mask_intr.master));
}
else
{
WRITE_PORT_UCHAR((PUCHAR)0xa1, (UCHAR)(pic_mask.slave|pic_mask_intr.slave));
}
return TRUE;
}
NTSTATUS NTAPI
HwReset(PCONTROLLER_INFO ControllerInfo)
/*
* FUNCTION: Reset the controller
* ARGUMENTS:
* ControllerInfo: controller to reset
* RETURNS:
* STATUS_SUCCESS in all cases
* NOTES:
* - Generates an interrupt that must be serviced four times (one per drive)
*/
{
TRACE_(FLOPPY, "HwReset called\n");
/* Write the reset bit in the DRSR */
WRITE_PORT_UCHAR(ControllerInfo->BaseAddress + DATA_RATE_SELECT_REGISTER, DRSR_SW_RESET);
/* Check for the reset bit in the DOR and set it if necessary (see Intel doc) */
if(!(READ_PORT_UCHAR(ControllerInfo->BaseAddress + DIGITAL_OUTPUT_REGISTER) & DOR_RESET))
{
HwDumpRegisters(ControllerInfo);
INFO_(FLOPPY, "HwReset: Setting Enable bit\n");
WRITE_PORT_UCHAR(ControllerInfo->BaseAddress + DIGITAL_OUTPUT_REGISTER, DOR_DMA_IO_INTERFACE_ENABLE|DOR_RESET);
HwDumpRegisters(ControllerInfo);
if(!(READ_PORT_UCHAR(ControllerInfo->BaseAddress + DIGITAL_OUTPUT_REGISTER) & DOR_RESET))
{
WARN_(FLOPPY, "HwReset: failed to set the DOR enable bit!\n");
HwDumpRegisters(ControllerInfo);
return STATUS_UNSUCCESSFUL;
}
}
return STATUS_SUCCESS;
}
VOID
NTAPI
HalpPCISynchronizeType2(IN PBUS_HANDLER BusHandler,
IN PCI_SLOT_NUMBER Slot,
IN PKIRQL Irql,
IN PPCI_TYPE2_ADDRESS_BITS PciCfg)
{
PCI_TYPE2_CSE_BITS PciCfg2Cse;
PPCIPBUSDATA BusData = (PPCIPBUSDATA)BusHandler->BusData;
/* Setup the configuration register */
PciCfg->u.AsUSHORT = 0;
PciCfg->u.bits.Agent = (USHORT)Slot.u.bits.DeviceNumber;
PciCfg->u.bits.AddressBase = (USHORT)BusData->Config.Type2.Base;
/* Acquire the lock */
KeRaiseIrql(HIGH_LEVEL, Irql);
KiAcquireSpinLock(&HalpPCIConfigLock);
/* Setup the CSE Register */
PciCfg2Cse.u.AsUCHAR = 0;
PciCfg2Cse.u.bits.Enable = TRUE;
PciCfg2Cse.u.bits.FunctionNumber = (UCHAR)Slot.u.bits.FunctionNumber;
PciCfg2Cse.u.bits.Key = -1;
/* Write the bus number and CSE */
WRITE_PORT_UCHAR(BusData->Config.Type2.Forward,
(UCHAR)BusHandler->BusNumber);
WRITE_PORT_UCHAR(BusData->Config.Type2.CSE, PciCfg2Cse.u.AsUCHAR);
}
void dc_dbg_init()
{
#ifdef DBG_COM
u32 divisor;
u8 lcr;
/* set baud rate and data format (8N1) */
/* turn on DTR and RTS */
WRITE_PORT_UCHAR(pv(SER_MCR(COM_BASE)), SR_MCR_DTR | SR_MCR_RTS);
/* set DLAB */
lcr = READ_PORT_UCHAR(pv(SER_LCR(COM_BASE))) | SR_LCR_DLAB;
WRITE_PORT_UCHAR(pv(SER_LCR(COM_BASE)), lcr);
/* set baud rate */
divisor = 115200 / DEFAULT_BAUD_RATE;
WRITE_PORT_UCHAR(pv(SER_DLL(COM_BASE)), divisor & 0xff);
WRITE_PORT_UCHAR(pv(SER_DLM(COM_BASE)), (divisor >> 8) & 0xff);
/* reset DLAB and set 8N1 format */
WRITE_PORT_UCHAR(pv(SER_LCR(COM_BASE)),
SR_LCR_CS8 | SR_LCR_ST1 | SR_LCR_PNO);
/* read junk out of the RBR */
READ_PORT_UCHAR(pv(SER_RBR(COM_BASE)));
#endif /* DBG_COM */
#ifdef DBG_HAL_DISPLAY
InbvAcquireDisplayOwnership();
InbvEnableDisplayString(TRUE);
#endif /* DBG_HAL_DISPLAY */
}
NTSTATUS W98Ports_ParallelSetChipMode (IN PDEVICE_OBJECT DeviceObject, IN PPARALLEL_CHIP_MODE ChipMode)
{
#define CONTROL_FORWARD 0x04
#define CONTROL_REVERSE 0x24
PDEVICE_EXTENSION DeviceExtension;
PUCHAR ECR;
PUCHAR DCR;
PUCHAR DR;
UCHAR Data;
PAGED_CODE ();
/* First check that we know the mode requested. Anything else is an error */
if (!( (ChipMode->ModeFlags==ECR_SPP_MODE) || (ChipMode->ModeFlags==ECR_BYTE_PIO_MODE) ))
return STATUS_INVALID_DEVICE_STATE;
/* Get a pointer to device data */
DeviceExtension= (PDEVICE_EXTENSION) DeviceObject->DeviceExtension;
if (DeviceExtension->BaseAddress!=0x3BC)
{
ECR= (PUCHAR) DeviceExtension->BaseAddress+ECR_OFFSET;
PPJOY_DBGPRINT (FILE_IOCTL|PPJOY_FENTRY, ("W98Ports_ParallelSetChipMode: Set ECR register 0x%x to 0x%x)",ECR,ChipMode->ModeFlags) );
WRITE_PORT_UCHAR (ECR,ChipMode->ModeFlags);
}
/* Set reverse mode if ChipMode is bidirectional, else set forward mode */
DCR= (PUCHAR) DeviceExtension->BaseAddress+DCR_OFFSET;
if (ChipMode->ModeFlags)
{
WRITE_PORT_UCHAR (DCR,CONTROL_REVERSE);
DR= (PUCHAR) DeviceExtension->BaseAddress;
/* Now test that reverse mode works. */
WRITE_PORT_UCHAR (DR,0xA5);
Data= READ_PORT_UCHAR (DR);
if (Data==0xA5)
{
/* Hmm, first time we got same data, try again with new value */
WRITE_PORT_UCHAR (DR,0x5A);
Data= READ_PORT_UCHAR (DR);
if (Data==0x5A)
{
/* Same data again. This is too much... assume port is not bidirectional */
return STATUS_INVALID_DEVICE_STATE;
}
}
}
else
{
WRITE_PORT_UCHAR (DCR,CONTROL_FORWARD);
}
return STATUS_SUCCESS;
}
VOID
NTAPI
HalDisableSystemInterrupt(
ULONG Vector,
KIRQL Irql)
{
ULONG irq;
if (Vector < IRQ_BASE || Vector >= IRQ_BASE + NR_IRQS)
{
ASSERT(FALSE);
return;
}
irq = Vector - IRQ_BASE;
pic_mask.both |= (1 << irq);
if (irq < 8)
{
WRITE_PORT_UCHAR((PUCHAR)0x21, (UCHAR)(pic_mask.master|pic_mask_intr.slave));
}
else
{
WRITE_PORT_UCHAR((PUCHAR)0xa1, (UCHAR)(pic_mask.slave|pic_mask_intr.slave));
}
return;
}
static DECLSPEC_NOINLINE VOID
LogQemuPut(
IN CHAR Char
)
{
WRITE_PORT_UCHAR(Port12, (UCHAR)Char);
WRITE_PORT_UCHAR(Port402, (UCHAR)Char);
}
void cPcSpeakerServer::makeImpulse(uint32 counter)
{
// TODO: To decrease debug-print this line is in comment.
// traceMedium("PcSpeakerServer: makeImpulse " << counter << endl);
// Generate the impulse
WRITE_PORT_UCHAR(TIMER_PORT, TIMER_SPEAKER_COUNTER_S0);
WRITE_PORT_UCHAR(TIMER_DATA_2, (UCHAR)(counter & 0xFF)); // LSB first
WRITE_PORT_UCHAR(TIMER_DATA_2, (UCHAR)((counter >> 8) & 0xFF));
}
static void Parallel_Reset(void)
/*
* FUNCTION: Resets the device attached to the parallel port
*/
{
int i;
WRITE_PORT_UCHAR((PUCHAR)LP_C,0);
for (i=0;i<LP_DELAY;i++);
WRITE_PORT_UCHAR((PUCHAR)LP_C,LP_PSELECP | LP_PINITP);
}
static BOOL HalpInitSysTimer(BYTE timeoutPerSecond)
{
WORD timeout = (WORD)(1193180/timeoutPerSecond);
WRITE_PORT_UCHAR((PUCHAR)0x43, 0x34);
WRITE_PORT_UCHAR((PUCHAR)0x40, (UCHAR)(timeout & 0xff));
WRITE_PORT_UCHAR((PUCHAR)0x40, (UCHAR)(timeout >> 8));
return TRUE;
}
VOID
FORCEINLINE
HalpWriteCmos(IN UCHAR Reg,
IN UCHAR Value)
{
/* Select the register */
WRITE_PORT_UCHAR(CMOS_CONTROL_PORT, Reg);
/* Write the value */
WRITE_PORT_UCHAR(CMOS_DATA_PORT, Value);
}
static BOOL KbdpResetIndicator(void)
{
UCHAR status;
do { status = READ_PORT_UCHAR((PUCHAR)0x64); } while( status & 0x02 );
WRITE_PORT_UCHAR((PUCHAR)0x60, 0xed);
do { status = READ_PORT_UCHAR((PUCHAR)0x64); } while( status & 0x02 );
WRITE_PORT_UCHAR((PUCHAR)0x60, m_KbdData.indicator_status);
return 0;
}
VOID
SerialInterruptRequest (
PUCHAR PortAddress
)
/*++
Routine Description:
This routine generates an interrupt on the interrupt line for
com port.
Arguments:
PortAddress - the port address of the desired com port.
Return Value:
None.
--*/
{
USHORT i;
UCHAR Temp;
WRITE_PORT_UCHAR(
PortAddress + MODEM_CONTROL_REGISTER,
8
);
WRITE_PORT_UCHAR(
PortAddress + INTERRUPT_ENABLE_REGISTER,
0
);
WRITE_PORT_UCHAR(
PortAddress + INTERRUPT_ENABLE_REGISTER,
0xf
);
//
// Add some delay
//
for (i = 0; i < 5 ; i++ ) {
Temp = READ_PORT_UCHAR((PUCHAR) PIC1_PORT1);
Temp = READ_PORT_UCHAR((PUCHAR) PIC2_PORT1);
}
}
/**********************************************************************************************************
* INTERNAL FUNTIONS *
**********************************************************************************************************/
static void CrtpSetCursorPos(WORD x, WORD y)
{
UCHAR data;
ENTER_CRITICAL_SECTION();
m_CursorXPos=x; m_CursorYPos=y;
EXIT_CRITICAL_SECTION();
data=(UCHAR)((x+y*SCREEN_CX)>>8);
WRITE_PORT_UCHAR((PUCHAR)0x3d4, 0x0e);
WRITE_PORT_UCHAR((PUCHAR)0x3d5, data);
data=(UCHAR)((x+y*SCREEN_CX)&0xff);
WRITE_PORT_UCHAR((PUCHAR)0x3d4, 0x0f);
WRITE_PORT_UCHAR((PUCHAR)0x3d5, data);
}
VOID
SynthMidiSendFM(
IN PUCHAR PortBase,
IN ULONG Address,
IN UCHAR Data
)
{
// these delays need to be 23us at least for old opl2 chips, even
// though new chips can handle 1 us delays.
WRITE_PORT_UCHAR(PortBase + (Address < 0x100 ? 0 : 2), (UCHAR)Address);
KeStallExecutionProcessor(23);
WRITE_PORT_UCHAR(PortBase + (Address < 0x100 ? 1 : 3), Data);
KeStallExecutionProcessor(23);
}
VOID
PutLedDisplay(
IN UCHAR Value
)
/*++
Routine Description:
This displays a 0--F in the single hexadecimal digit display in
Jensen.
Arguments:
Value The lower four bits of this will be displayed
in the Jensen LED.
Return Value:
None.
--*/
{
WRITE_PORT_UCHAR ((PUCHAR)SYSCTL,
(READ_PORT_UCHAR((PUCHAR)SYSCTL) & 0xf0)
|
(Value & 0x0f)
);
}
BOOLEAN
SendKbdCommand(
IN UCHAR Command
)
/*++
Routine Description:
This routine polls the Status Register until the controller is ready to
accept a command or timeout, then it send the Command.
Arguments:
None.
Return Value:
TRUE if timeout, FALSE if OK;
--*/
{
ULONG i;
for (i=0; i <KBD_TIMEOUT; i++) {
if ((READ_PORT_UCHAR((PUCHAR)&KEYBOARD_READ->Status) & KBD_IBF_MASK) == 0) {
WRITE_PORT_UCHAR((PUCHAR)&KEYBOARD_WRITE->Command,Command);
return FALSE;
}
}
return TRUE;
}
ACPI_STATUS
AcpiOsWritePort (
ACPI_IO_ADDRESS Address,
UINT32 Value,
UINT32 Width)
{
DPRINT("AcpiOsWritePort %p, width %d\n",Address,Width);
switch (Width)
{
case 8:
WRITE_PORT_UCHAR((PUCHAR)Address, Value);
break;
case 16:
WRITE_PORT_USHORT((PUSHORT)Address, Value);
break;
case 32:
WRITE_PORT_ULONG((PULONG)Address, Value);
break;
default:
DPRINT1("AcpiOsWritePort got bad width: %d\n",Width);
return (AE_BAD_PARAMETER);
break;
}
return (AE_OK);
}
static NTSTATUS frob_port(PDEVICE_OBJECT devobj, PIRP irp, PUCHAR port)
{
NTSTATUS status = STATUS_SUCCESS;
PIO_STACK_LOCATION irpsp;
PFILE_OBJECT fileobj;
struct eppflex *s = devobj->DeviceExtension;
struct eppflexfile *fs;
struct eppflex_rwdata *rw = (struct eppflex_rwdata *)irp->AssociatedIrp.SystemBuffer;
UCHAR data;
irpsp = IoGetCurrentIrpStackLocation(irp);
fileobj = irpsp->FileObject;
fs = fileobj->FsContext;
irp->IoStatus.Information = 0;
if (irpsp->Parameters.DeviceIoControl.InputBufferLength < sizeof(struct eppflex_rwdata) ||
irpsp->Parameters.DeviceIoControl.OutputBufferLength < sizeof(struct eppflex_rwdata))
status = STATUS_INVALID_PARAMETER;
else if ((port < fs->info.Controller || port >= fs->info.Controller+fs->info.SpanOfController) &&
(port < fs->pnpinfo.EcpController || port >= fs->pnpinfo.EcpController+fs->pnpinfo.SpanOfEcpController))
status = STATUS_ACCESS_VIOLATION;
else {
data = READ_PORT_UCHAR(port);
data = (data & ~rw->mask) ^ rw->data;
WRITE_PORT_UCHAR(port, data);
rw->data = data;
irp->IoStatus.Information = sizeof(struct eppflex_rwdata);
}
irp->IoStatus.Status = status;
IoCompleteRequest(irp, IO_NO_INCREMENT);
return status;
}
VOID
HalpInitializeNMI(
VOID
)
/*++
Routine Description:
This function is called to intialize SIO NMI interrupts.
Arguments:
None.
Return Value:
None.
--*/
{
UCHAR DataByte;
//
// Initialize the SIO NMI interrupt.
//
KeInitializeInterrupt( &HalpEisaNmiInterrupt,
HalHandleNMI,
NULL,
NULL,
EISA_NMI_VECTOR,
EISA_NMI_LEVEL,
EISA_NMI_LEVEL,
LevelSensitive,
FALSE,
0,
FALSE
);
//
// Don't fail if the interrupt cannot be connected.
//
KeConnectInterrupt( &HalpEisaNmiInterrupt );
//
// Clear the Eisa NMI disable bit. This bit is the high order of the
// NMI enable register. Note that the other bits should be left as
// they are, according to the chip's documentation.
//
//[wem] ?? Avanti simply writes zero to NmiEnable -- OK
DataByte = READ_PORT_UCHAR(&((PEISA_CONTROL) HalpEisaControlBase)->NmiEnable);
((PNMI_ENABLE)(&DataByte))->NmiDisable = 0;
WRITE_PORT_UCHAR(&((PEISA_CONTROL) HalpEisaControlBase)->NmiEnable, DataByte);
#ifdef DBG
DbgPrint("HalpIntializeNMI: wrote 0x%x to NmiEnable\n", DataByte);
#endif
}
VOID
ScsiPortWritePortUchar(
IN PUCHAR Port,
IN UCHAR Value
)
/*++
Routine Description:
Write to the specificed port address.
Arguments:
Port - Supplies a pointer to the port address.
Value - Supplies the value to be written.
Return Value:
None
--*/
{
WRITE_PORT_UCHAR(Port, Value);
}
/*
* FUNCTION: Write data to a port, waiting first for it to become ready
*/
BOOLEAN
i8042Write(
IN PPORT_DEVICE_EXTENSION DeviceExtension,
IN PUCHAR addr,
IN UCHAR data)
{
ULONG Counter;
ASSERT(addr);
ASSERT(DeviceExtension->ControlPort != NULL);
Counter = DeviceExtension->Settings.PollingIterations;
while ((KBD_IBF & READ_PORT_UCHAR(DeviceExtension->ControlPort)) &&
(Counter--))
{
KeStallExecutionProcessor(50);
}
if (Counter)
{
WRITE_PORT_UCHAR(addr, data);
INFO_(I8042PRT, "Sent 0x%x to port %p\n", data, addr);
return TRUE;
}
return FALSE;
}
static void DebugPrintFuncSerial(const char *format, ...)
{
char buf[TEMP_BUFFER_SIZE];
NTSTATUS status;
size_t len;
va_list list;
va_start(list, format);
status = RtlStringCbVPrintfA(buf, sizeof(buf), format, list);
if (status == STATUS_SUCCESS)
{
len = strlen(buf);
}
else
{
len = 2;
buf[0] = 'O';
buf[1] = '\n';
}
if (len)
{
WRITE_PORT_BUFFER_UCHAR(RHEL_DEBUG_PORT, (PUCHAR)buf, len);
WRITE_PORT_UCHAR(RHEL_DEBUG_PORT, '\r');
}
va_end(list);
}
/* NSC/Cyrix CPU indexed register access macros */
static __inline
UCHAR
getCx86(UCHAR reg)
{
WRITE_PORT_UCHAR((PUCHAR)(ULONG_PTR)0x22, reg);
return READ_PORT_UCHAR((PUCHAR)(ULONG_PTR)0x23);
}
static
inline
VOID
WriteData(USHORT Data)
{
WRITE_PORT_UCHAR((PUCHAR)ISAPNP_WRITE_DATA, Data);
}
static
inline
VOID
WriteAddress(USHORT Address)
{
WRITE_PORT_UCHAR((PUCHAR)ISAPNP_ADDRESS, Address);
}
void sound(int freq)
{
int scale;
if (freq == 0)
{
WRITE_PORT_UCHAR((PUCHAR)0x61, READ_PORT_UCHAR((PUCHAR)0x61) & ~3);
return;
}
scale = 1193046 / freq;
WRITE_PORT_UCHAR((PUCHAR)0x43, 0xb6);
WRITE_PORT_UCHAR((PUCHAR)0x42, scale & 0xff);
WRITE_PORT_UCHAR((PUCHAR)0x42, scale >> 8);
WRITE_PORT_UCHAR((PUCHAR)0x61, READ_PORT_UCHAR((PUCHAR)0x61) | 3);
}
void cPcSpeakerServer::soundOff()
{
traceMedium("PcSpeakerServer: soundOff" << endl);
// Turn off the PcSpekaer gate
UCHAR speaker = READ_PORT_UCHAR(SPEAKER_PORT);
WRITE_PORT_UCHAR(SPEAKER_PORT, speaker & (~SPEAKER_SIGNAL_BIT));
}
