//*****************************************************************************
//
// This example demonstrates the use of the watchdog timer.
//
//*****************************************************************************
int
main(void)
{
//
// Set the clocking to run directly from the crystal.
//
SysCtlClockSet(SYSCTL_SYSDIV_1 | SYSCTL_USE_OSC | SYSCTL_OSC_MAIN |
SYSCTL_XTAL_8MHZ);
//
// Initialize the OLED display and write status.
//
RIT128x96x4Init(1000000);
RIT128x96x4StringDraw("Watchdog example", 12, 24, 15);
//
// Enable the peripherals used by this example.
//
SysCtlPeripheralEnable(SYSCTL_PERIPH_WDOG0);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOG);
//
// Enable processor interrupts.
//
IntMasterEnable();
//
// Set GPIO G2 as an output. This drives an LED on the board that will
// toggle when a watchdog interrupt is processed.
//
GPIOPinTypeGPIOOutput(GPIO_PORTG_BASE, GPIO_PIN_2);
GPIOPinWrite(GPIO_PORTG_BASE, GPIO_PIN_2, 0);
//
// Enable the watchdog interrupt.
//
IntEnable(INT_WATCHDOG);
//
// Set the period of the watchdog timer.
//
WatchdogReloadSet(WATCHDOG0_BASE, SysCtlClockGet());
//
// Enable reset generation from the watchdog timer.
//
WatchdogResetEnable(WATCHDOG0_BASE);
//
// Enable the watchdog timer.
//
WatchdogEnable(WATCHDOG0_BASE);
//
// Loop forever while the LED winks as watchdog interrupts are handled.
//
while(1)
{
}
}
//*****************************************************************************
//
// This example demonstrates the use of the watchdog timer.
//
//*****************************************************************************
int
main(void)
{
//
// Set the clocking to run directly from the crystal.
//
SysCtlClockSet(SYSCTL_SYSDIV_1 | SYSCTL_USE_OSC | SYSCTL_OSC_MAIN |
SYSCTL_XTAL_6MHZ);
//
// Enable the peripherals used by this example.
//
SysCtlPeripheralEnable(SYSCTL_PERIPH_WDOG0);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC);
//
// Enable processor interrupts.
//
IntMasterEnable();
//
// Set GPIO C5 as an output. This drives an LED on the board that will
// toggle when a watchdog interrupt is processed.
//
GPIOPinTypeGPIOOutput(GPIO_PORTC_BASE, GPIO_PIN_5);
//
// Enable the watchdog interrupt.
//
IntEnable(INT_WATCHDOG);
//
// Set the period of the watchdog timer.
//
WatchdogReloadSet(WATCHDOG0_BASE, SysCtlClockGet());
//
// Enable reset generation from the watchdog timer.
//
WatchdogResetEnable(WATCHDOG0_BASE);
//
// Enable the watchdog timer.
//
WatchdogEnable(WATCHDOG0_BASE);
//
// Loop forever while the LED winks as watchdog interrupts are handled.
//
while(1)
{
}
}
/*
* ======== WatchdogCC26XX_hwInit ========
* This functions initializes the Watchdog hardware module.
*
* @pre Function assumes that the Watchdog handle is pointing to a hardware
* module which has already been opened.
*/
static void WatchdogCC26XX_initHw(Watchdog_Handle handle) {
WatchdogCC26XX_Object *object;
/* get the pointer to the object and hwAttrs */
object = handle->object;
/* unlock the Watchdog configuration registers */
WatchdogUnlock();
/* make sure the Watchdog is unlocked before continuing */
while(WatchdogLockState() == WATCHDOG_LOCK_LOCKED)
{ }
WatchdogReloadSet(object->reloadValue);
#ifndef CCWARE
/* set reset mode */
if (object->resetMode == Watchdog_RESET_ON) {
WatchdogResetEnable();
}
else {
WatchdogResetDisable();
}
#endif
/* set debug stall mode */
if (object->debugStallMode == Watchdog_DEBUG_STALL_ON) {
WatchdogStallEnable();
}
else {
WatchdogStallDisable();
}
/* enable the Watchdog interrupt as a non-maskable interrupt */
WatchdogIntTypeSet(WATCHDOG_INT_TYPE_NMI);
/* enable interrupts */
WatchdogIntEnable();
/* enable the Watchdog */
WatchdogEnable();
/* lock the Watchdog configuration registers */
WatchdogLock();
}
void hwInitWatchdog(long intervalMilliseconds) {
if (SysCtlPeripheralPresent(SYSCTL_PERIPH_WDOG)){
SysCtlPeripheralEnable(SYSCTL_PERIPH_WDOG);
WatchdogUnlock(WATCHDOG_BASE); // unlock WD register
WatchdogResetEnable(WATCHDOG_BASE); // enable reset capability on second timeout
/* watchdog resets the system on the second timeout!
* -> so we have to divide the time by 2
* -> on the first time-out only an interrupt is generated
*/
glWDLoad = (SysCtlClockGet()/1000) * (intervalMilliseconds/2);
WatchdogReloadSet(WATCHDOG_BASE, glWDLoad);
WatchdogStallEnable(WATCHDOG_BASE); // stops the watchdog during debug break
WatchdogIntUnregister(WATCHDOG_BASE); // mask interrupt -> interrupts are not seen and handled by processor
WatchdogEnable(WATCHDOG_BASE);
WatchdogLock(WATCHDOG_BASE); // lock WD register
}
}
void prvSetupHardware( void ){
tBoolean found;
long lEEPROMRetStatus;
unsigned short data,data2;
unsigned long uart_speed;
/* If running on Rev A2 silicon, turn the LDO voltage up to 2.75V. This is
a workaround to allow the PLL to operate reliably. */
if( DEVICE_IS_REVA2 ) {
SysCtlLDOSet( SYSCTL_LDO_2_75V );
}
/* Set the clocking to run from the PLL at 50 MHz */
SysCtlClockSet( SYSCTL_SYSDIV_4 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_8MHZ );
/* Enable Port F for Ethernet LEDs
LED0 Bit 3 Output
LED1 Bit 2 Output */
SysCtlPeripheralEnable( SYSCTL_PERIPH_GPIOF );
GPIODirModeSet( GPIO_PORTF_BASE, (GPIO_PIN_2 | GPIO_PIN_3), GPIO_DIR_MODE_HW );
GPIOPadConfigSet( GPIO_PORTF_BASE, (GPIO_PIN_2 | GPIO_PIN_3 ), GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD );
//
// Enable the GPIO pin for the LED (PF0). Set the direction as output, and
// enable the GPIO pin for digital function.
//
GPIOPinTypeGPIOOutput(GPIO_PORTF_BASE, GPIO_PIN_0);
//
// Enable processor interrupts.
//
IntMasterEnable();
if(SoftEEPROMInit(0x1F000, 0x20000, 0x800) != 0) {
LWIPDebug("SoftEEPROM initialisation failed.");
}
lEEPROMRetStatus = SoftEEPROMRead(UART0_SPEED_HIGH_ID, &data, &found);
if(lEEPROMRetStatus == 0 && found) {
SoftEEPROMRead(UART0_SPEED_LOW_ID, &data2, &found);
uart_speed = (data << 16 & 0xFFFF0000) | (data2 & 0x0000FFFF);
SoftEEPROMRead(UART0_CONFIG_ID, &data, &found);
} else {
uart_speed=115200;
data = (UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | UART_CONFIG_PAR_NONE);
}
uart_init(0, uart_speed, data);
SysCtlPeripheralEnable(SYSCTL_PERIPH_WDOG0);
IntPriorityGroupingSet(4);
IntPrioritySet(INT_WATCHDOG,SET_SYSCALL_INTERRUPT_PRIORITY(5));
IntEnable(INT_WATCHDOG); // Enable the watchdog interrupt.
WatchdogReloadSet(WATCHDOG0_BASE, SysCtlClockGet());
WatchdogResetEnable(WATCHDOG0_BASE);
WatchdogEnable(WATCHDOG0_BASE);
rtc_init();
modules_init();
}
//*****************************************************************************
//
//! \brief xwdt001 test execute main body.
//!
//! \return None.
//
//*****************************************************************************
static void xwdt001Execute(void)
{
unsigned long i = 0;
unsigned long tmp = 0;
unsigned long WdtBase = 0;
//
// Reset Enable/Disable Test
//
for(i = 0; i < WDT_NUM; i++)
{
WdtBase = WdtBaseTbl[i];
//
// Reset Enable Test
//
if(WdtBase == WATCHDOG1_BASE)
{
Watchdog1WriteSync();
}
WatchdogResetEnable(WdtBase);
tmp = xHWREG(WdtBase + WDT_O_CTL) & WDT_CTL_RESEN;
TestAssert((0 != tmp),
"WDT Test 001: Res%set Enable Failed");
//
// Reset Disable Test
//
if(WdtBase == WATCHDOG1_BASE)
{
Watchdog1WriteSync();
}
WatchdogResetDisable(WdtBase);
tmp = xHWREG(WdtBase + WDT_O_CTL) & WDT_CTL_RESEN;
TestAssert((0 == tmp),
"WDT Test 001: Reset Disable Failed");
}
//
// Lock/Unlock/GetState Test
//
for(i = 0; i < WDT_NUM; i++)
{
WdtBase = WdtBaseTbl[i];
//
// Lock Test
//
if(WdtBase == WATCHDOG1_BASE)
{
Watchdog1WriteSync();
}
WatchdogLock(WdtBase);
tmp = xHWREG(WdtBase + WDT_O_LOCK);
TestAssert((tmp == WDT_LOCK_LOCKED),
"WDT Test 001: Lock Failed");
//
// Get Lock State Test
//
tmp = WatchdogLockState(WdtBase);
TestAssert((tmp == xtrue),
"WDT Test 001: Get Lock State Failed");
//
// Unlock Test
//
if(WdtBase == WATCHDOG1_BASE)
{
Watchdog1WriteSync();
}
WatchdogUnlock(WdtBase);
tmp = xHWREG(WdtBase + WDT_O_LOCK);
TestAssert((tmp == WDT_LOCK_UNLOCKED),
"WDT Test 001: Unlock Failed");
//
// Get Lock State Test
//
tmp = WatchdogLockState(WdtBase);
TestAssert((tmp == xfalse),
"WDT Test 001: Get Lock State Failed");
}
//
// Reload Set/Get Test
//
for(i = 0; i < 1; i++)
{
unsigned long j = 0;
unsigned long TblSize = 0;
WdtBase = WdtBaseTbl[i];
TblSize = sizeof(ReloadValueTbl) / sizeof(ReloadValueTbl[0]);
for(j = 0; j < TblSize; j++)
{
//
// Reload Set Test
//
if(WdtBase == WATCHDOG1_BASE)
{
Watchdog1WriteSync();
}
WatchdogReloadSet(WdtBase, ReloadValueTbl[j]);
tmp = xHWREG(WdtBase + WDT_O_LOAD);
TestAssert((ReloadValueTbl[j] == tmp),
"WDT Test 001: Wdt Reload Set Failed");
//
// Reload Get Test
//
tmp = WatchdogReloadGet(WdtBase);
TestAssert((ReloadValueTbl[j] == tmp),
"WDT Test 001: Wdt Reload Get Failed");
}
}
//
// Stall Enable/Disable Test
//
for(i = 0; i < WDT_NUM; i++)
{
WdtBase = WdtBaseTbl[i];
//
// Stall Enable Test
//
if(WdtBase == WATCHDOG1_BASE)
{
Watchdog1WriteSync();
}
WatchdogStallEnable(WdtBase);
tmp = xHWREG(WdtBase + WDT_O_TEST) & WDT_TEST_STALL;
TestAssert((0 != tmp),
"WDT Test 001: Stall Enable Failed");
//
// Stall Disable Test
//
if(WdtBase == WATCHDOG1_BASE)
{
Watchdog1WriteSync();
}
WatchdogStallDisable(WdtBase);
tmp = xHWREG(WdtBase + WDT_O_TEST) & WDT_TEST_STALL;
TestAssert((0 == tmp),
"WDT Test 001: Stall Disable Failed");
}
//
// Enable/Running Test
//
for(i = 0; i < WDT_NUM; i++)
{
WdtBase = WdtBaseTbl[i];
//
// Enable Test
//
WatchdogEnable(WdtBase);
tmp = xHWREG(WdtBase + WDT_O_CTL) & WDT_CTL_INTEN;
TestAssert((0 != tmp),
"WDT Test 001: Enable Failed");
//
// IsRunning Test
//
tmp = WatchdogRunning(WdtBase);
TestAssert((0 != tmp),
"WDT Test 001: IsRunning Failed");
}
}
