static void OnMHDCableConnected(void)
{
TPI_DEBUG_PRINT(("[SIMG] MHD Connected\n"));
if (txPowerState == TX_POWER_STATE_D3) {
/* start tpi */
WriteByteTPI(TPI_ENABLE, 0x00); /* Write "0" to 72:C7 to
start HW TPI mode */
/* enable interrupts */
WriteIndexedRegister(INDEXED_PAGE_0, 0x78, 0x01);
TxPowerStateD0();
}
mobileHdCableConnected = TRUE;
WriteIndexedRegister(INDEXED_PAGE_0, 0xA0, 0x10);
TPI_DEBUG_PRINT(("[SIMG] Setting DDC Burst Mode\n"));
/* Increase DDC translation layer timer (burst mode) */
WriteByteCBUS(0x07, DDC_XLTN_TIMEOUT_MAX_VAL | 0x0E);
WriteByteCBUS(0x47, 0x03);
WriteByteCBUS(0x21, 0x01); /* Heartbeat Disable */
}
void mhd_tx_fifo_stable(void)
{
byte tmp;
tmp = ReadIndexedRegister(INDEXED_PAGE_0, 0x3E);
if ((tmp & (SI_BIT_7 | SI_BIT_6)) != 0x00)
{
WriteIndexedRegister(INDEXED_PAGE_0, 0x05, SI_BIT_4 | ASR_VALUE); // Assert Mobile HD FIFO Reset
delay_ms(1);
WriteIndexedRegister(INDEXED_PAGE_0, 0x05, ASR_VALUE); // Deassert Mobile HD FIFO Reset
}
}
void CheckTxFifoStable(void)
{
uint8_t bTemp;
bTemp = ReadIndexedRegister(0x01, 0x3E);
if ((bTemp & (BIT_7 | BIT_6)) != 0x00) {
TPI_DEBUG_PRINT(("FIFO Overrun / Underrun\n"));
WriteIndexedRegister(0x01, 0x05, BIT_4 | ASR_VALUE);
DelayMS(1);
WriteIndexedRegister(0x01, 0x05, ASR_VALUE);
}
}
void CheckTxFifoStable (void)
{
byte bTemp;
bTemp = ReadIndexedRegister(INDEXED_PAGE_0, 0x3E);
if ((bTemp & (SI_BIT_7 | SI_BIT_6)) != 0x00)
{
TPI_DEBUG_PRINT(("[SIMG] FIFO Overrun / Underrun\n"));
WriteIndexedRegister(INDEXED_PAGE_0, 0x05, SI_BIT_4 | ASR_VALUE); // Assert MHD FIFO Reset
delay_ms(1);
WriteIndexedRegister(INDEXED_PAGE_0, 0x05, ASR_VALUE); // Deassert MHD FIFO Reset
}
}
void mhd_rx_connected(void)
{
WriteIndexedRegister(INDEXED_PAGE_0, 0xA0, 0x10); //TX termination enable
WriteByteCBUS(0x07, DDC_XLTN_TIMEOUT_MAX_VAL | 0x0E); // Increase DDC translation layer timer (burst mode)
WriteByteCBUS(0x47, 0x03);
WriteByteCBUS(0x21, 0x01); // Heartbeat Disable
}
void ForceUsbIdSwitchOpen (void)
{
ReadModifyWriteIndexedRegister(0x01, 0x90, BIT_0, 0x00);
ReadModifyWriteIndexedRegister(0x01, 0x95, BIT_6, BIT_6);
WriteIndexedRegister(0x01, 0x92, 0x86);
ReadModifyWriteIndexedRegister(0x01, 0x79, BIT_5 | BIT_4, BIT_4);
}
byte MHD_Bridge_detect(void)
{
byte temp = 0;
byte BridgeOn = 0;
/* disable interrupts */
ReadModifyWriteTPI(TPI_INTERRUPT_ENABLE_REG,
RECEIVER_SENSE_EVENT_MASK, 0x00);
msleep(180);
if(!gpio_get_value(TEGRA_GPIO_PI5)&& MHD_HW_IsOn()) //TEGRA_GPIO_PI5: GPIO_ACCESSORY_INT
{
temp = ReadIndexedRegister(INDEXED_PAGE_0, 0x09);
if ((temp & RSEN) == 0x00) {
BridgeOn = FALSE;
//ReadModifyWriteTPI(0x79, SI_BIT_5 | SI_BIT_4, SI_BIT_4); //force HPD to 0
ReadModifyWriteIndexedRegister(INDEXED_PAGE_0, 0x79, SI_BIT_5 | SI_BIT_4, SI_BIT_4);
} else {
BridgeOn = TRUE;
//ReadModifyWriteTPI(0x79, BIT_5 | BIT_4, 0); //back to current state
}
printk("[HDMI] Bridge detect %x :: HPD %d\n",BridgeOn,gpio_get_value(TEGRA_GPIO_PN7)); //TEGRA_GPIO_PN7: GPIO_HDMI_HPD
//ReadModifyWriteTPI(0x79, SI_BIT_5 | SI_BIT_4, 0); //back to current state
ReadModifyWriteIndexedRegister(INDEXED_PAGE_0, 0x79, SI_BIT_5 | SI_BIT_4, 0);
}
MHD_INT_clear();
/* enable interrupts */
WriteIndexedRegister(INDEXED_PAGE_0, 0x78, 0x01);
printk("[HDMI]MHD_Bridge_detect -- \n");
return BridgeOn;
}
void ForceUsbIdSwitchOpen (void)
{
ReadModifyWriteIndexedRegister(INDEXED_PAGE_0, 0x90, SI_BIT_0, 0x00); // Disable discovery
ReadModifyWriteIndexedRegister(INDEXED_PAGE_0, 0x95, SI_BIT_6, SI_BIT_6); // Force USB ID Switch
WriteIndexedRegister(INDEXED_PAGE_0, 0x92, 0x46); // Force MHD mode
ReadModifyWriteIndexedRegister(INDEXED_PAGE_0, 0x79, SI_BIT_5 | SI_BIT_4, SI_BIT_4); // Force HPD to 0 when not in MHD mode.
}
void mhl_output_enable(void)
{
mdelay(100);
//ReadModifyWriteIndexedRegister(INDEXED_PAGE_0, 0x95, BIT_5, BIT_5);
//WriteIndexedRegister(INDEXED_PAGE_0, 0x74, 0x40);
WriteIndexedRegister(INDEXED_PAGE_0, 0xA0, 0x10);
mdelay(100);
ReadModifyWriteTPI(TPI_SYSTEM_CONTROL_DATA_REG, TMDS_OUTPUT_CONTROL_MASK, TMDS_OUTPUT_CONTROL_ACTIVE);
}
void MHD_INT_clear(void)
{
byte Int_state;
#if 0
Int_state= ReadByteTPI(TPI_INTERRUPT_STATUS_REG);
WriteByteTPI (TPI_INTERRUPT_STATUS_REG, Int_state); // Clear this interrupt.
WriteByteTPI(TPI_INTERRUPT_ENABLE_REG, 0x00);
WriteIndexedRegister(INDEXED_PAGE_0, 0x78, 0x01); // Enable
#endif
Int_state = ReadIndexedRegister(INDEXED_PAGE_0,0x74);
WriteIndexedRegister(INDEXED_PAGE_0,0x74,Int_state);
}
void sii9234_tpi_init(void)
{
MHD_HW_Reset();
//sii9234_initial_registers_set(); //previous setting
printk("[HDMI]9234 init ++ \n");
#if 0
/* disable interrupts */
ReadModifyWriteTPI(TPI_INTERRUPT_ENABLE_REG,
RECEIVER_SENSE_EVENT_MASK, 0x00);
//MHD_INT_clear();
#endif
sii9234_register_init();
/* start tpi */
WriteByteTPI(TPI_ENABLE, 0x00); /* Write "0" to 72:C7 to
start HW TPI mode */
/* enable interrupts */
WriteIndexedRegister(INDEXED_PAGE_0, 0x78, 0x01);
/* mhd rx connected */
WriteIndexedRegister(INDEXED_PAGE_0,
0xA0, 0x10); /* TX termination enable */
WriteByteCBUS(0x07, DDC_XLTN_TIMEOUT_MAX_VAL |
0x0E); /* Increase DDC translation layer timer (burst mode) */
WriteByteCBUS(0x47, 0x03);
WriteByteCBUS(0x21, 0x01); /* Heartbeat Disable */
/* enable mhd tx */
ReadModifyWriteTPI(TPI_SYSTEM_CONTROL_DATA_REG,
TMDS_OUTPUT_CONTROL_MASK, TMDS_OUTPUT_CONTROL_ACTIVE);
/* set mhd power active mode */
ReadModifyWriteTPI(TPI_DEVICE_POWER_STATE_CTRL_REG,
TX_POWER_STATE_MASK, 0x00);
mhd_tx_fifo_stable(); //fifo clear
printk("[HDMI]9234 init -- \n");
}
void sii9234_tpi_init(void)
{
MHD_HW_Reset();
pr_info("[HDMI]9234 init ++\n");
sii9234_register_init();
/* start tpi */
WriteByteTPI(TPI_ENABLE, 0x00); /* Write "0" to 72:C7 to
start HW TPI mode */
/* enable interrupts */
WriteIndexedRegister(INDEXED_PAGE_0, 0x78, 0x01);
/* mhd rx connected */
WriteIndexedRegister(INDEXED_PAGE_0,
0xA0, 0x10); /* TX termination enable */
WriteByteCBUS(0x07, DDC_XLTN_TIMEOUT_MAX_VAL |
0x0E); /* Increase DDC translation layer timer (burst mode) */
WriteByteCBUS(0x47, 0x03);
WriteByteCBUS(0x21, 0x01); /* Heartbeat Disable */
/* enable mhd tx */
ReadModifyWriteTPI(TPI_SYSTEM_CONTROL_DATA_REG,
TMDS_OUTPUT_CONTROL_MASK, TMDS_OUTPUT_CONTROL_ACTIVE);
/* set mhd power active mode */
ReadModifyWriteTPI(TPI_DEVICE_POWER_STATE_CTRL_REG,
TX_POWER_STATE_MASK, 0x00);
mhd_tx_fifo_stable(); /*fifo clear*/
#ifdef CONFIG_SAMSUNG_WORKAROUND_HPD_GLANCE
mhl_hpd_handler(true);
#endif
pr_info("[HDMI]9234 init --\n");
}
static void HotPlugService(void)
{
/* disable interrupts */
ReadModifyWriteTPI(TPI_INTERRUPT_ENABLE_REG,
RECEIVER_SENSE_EVENT_MASK, 0x00);
/* enable TMDS */
pr_info("[SIMG] TMDS -> Enabled\n");
ReadModifyWriteTPI(TPI_SYSTEM_CONTROL_DATA_REG,
TMDS_OUTPUT_CONTROL_MASK, TMDS_OUTPUT_CONTROL_ACTIVE);
tmdsPoweredUp = TRUE;
TxPowerStateD0();
/* enable interrupts */
WriteIndexedRegister(INDEXED_PAGE_0, 0x78, 0x01);
CheckTxFifoStable();
}
bool TPI_Init(void)
{
TPI_DEBUG_PRINT(("9232 SK "));
TPI_DEBUG_PRINT(("(X04)"));
TPI_DEBUG_PRINT((" FW 0.22\n"));
txPowerState = TX_POWER_STATE_D0;
InitializeStateVariables();
TxHW_Reset();
WriteInitialRegisterValues();
I2C_WriteByte(TPI_SLAVE_ADDR, 0x7A, 0x14);
if (!StartTPI()) {
return false;
}
if (!ProductID_Read()) {
return false;
}
hdcp_init(mhl_tpi_info);
MHLCableConnected = FALSE;
hdmiCableConnected = false;
OnDownstreamRxPoweredDown();
WriteIndexedRegister(0x01, 0xA0, 0xD0);
TPI_DEBUG_PRINT(("\ncalling CpCbusInitialize\n\n"));
CpCbusInitialize(mhl_tpi_info);
hdcp_off();
TxPowerStateD3();
MHLCableConnected = false;
hdmiCableConnected = false;
dsRxPoweredUp = false;
bInTpiMode =false;
txPowerState = txpsD3;
return true;
}
void OnMHDCableConnected (void)
{
TPI_DEBUG_PRINT (("[SIMG] MHD Connected\n"));
if (txPowerState == TX_POWER_STATE_D3)
{
sii9234_start_tpi();
EnableInterrupts();
TxPowerStateD0();
}
mobileHdCableConnected = TRUE;
WriteIndexedRegister(INDEXED_PAGE_0, 0xA0, 0x10);
TPI_DEBUG_PRINT (("[SIMG] Setting DDC Burst Mode\n"));
WriteByteCBUS(0x07, DDC_XLTN_TIMEOUT_MAX_VAL | 0x0E); // Increase DDC translation layer timer (burst mode)
WriteByteCBUS(0x47, 0x03);
WriteByteCBUS(0x21, 0x01); // Heartbeat Disable
}
static void EnableInterrupts (void)
{
ReadModifyWriteTPI(TPI_INTERRUPT_ENABLE_REG, RECEIVER_SENSE_EVENT_MASK, RECEIVER_SENSE_EVENT_MASK);
WriteIndexedRegister(INDEXED_PAGE_0, 0x75, SI_BIT_5); // Enable
}
void sii9234_enable_interrupts(void)
{
ReadModifyWriteTPI(TPI_INTERRUPT_ENABLE_REG, HOT_PLUG_EVENT_MASK, HOT_PLUG_EVENT_MASK);
WriteIndexedRegister(INDEXED_PAGE_0, 0x75, SI_BIT_5); // Enable
}
void sii9234_initial_registers_set(void)
{
printk ("==[SIMG] sii9234_initial_registers_set Start ==\n");
#if 0 //old cable
// Power Up
I2C_WriteByte(0x7A, 0x3D, 0x3F); // Power up CVCC 1.2V core
I2C_WriteByte(0x92, 0x11, 0x01); // Enable TxPLL Clock
I2C_WriteByte(0x92, 0x12, 0x15); // Enable Tx Clock Path & Equalizer
I2C_WriteByte(0x72, 0x08, 0x35); // Power Up TMDS Tx Core
// Analog PLL Control
I2C_WriteByte(0x92, 0x17, 0x03); // PLL Calrefsel
I2C_WriteByte(0x92, 0x1A, 0x20); // VCO Cal
I2C_WriteByte(0x92, 0x22, 0x8A); // Auto EQ
I2C_WriteByte(0x92, 0x23, 0x6A); // Auto EQ
I2C_WriteByte(0x92, 0x24, 0xAA); // Auto EQ
I2C_WriteByte(0x92, 0x25, 0xCA); // Auto EQ
I2C_WriteByte(0x92, 0x26, 0xEA); // Auto EQ
I2C_WriteByte(0x92, 0x4C, 0xA0); // Manual zone control
I2C_WriteByte(0x92, 0x4D, 0x00); // PLL Mode Value
I2C_WriteByte(0x72, 0x80, 0x14); // Enable Rx PLL Clock Value
I2C_WriteByte(0x92, 0x45, 0x44); // Rx PLL BW value from I2C
I2C_WriteByte(0x92, 0x31, 0x0A); // Rx PLL BW ~ 4MHz
I2C_WriteByte(0x72, 0xA1, 0xFC); // Disable internal Mobile HD driver
I2C_WriteByte(0x72, 0xA3, 0xFF); //AMP
I2C_WriteByte(0x72, 0x2B, 0x01); // Enable HDCP Compliance workaround
I2C_WriteByte(0x72, 0x91, 0xE5); // Skip RGND detection
I2C_WriteByte(0x72, 0xA5, 0x00); // RGND Hysterisis.
I2C_WriteByte(0x72, 0x90, 0x27); // Enable CBUS discovery
//I2C_WriteByte(0x72, 0x05, ASR_VALUE); // Enable Auto soft reset on SCDT = 0
I2C_WriteByte(0x72, 0x0D, 0x1C); // HDMI Transcode mode enable
WriteByteTPI(TPI_ENABLE, 0x00);
delay_ms(100);
WriteIndexedRegister(INDEXED_PAGE_0, 0xA0, 0x10);
delay_ms(100);
ReadModifyWriteTPI(TPI_SYSTEM_CONTROL_DATA_REG, TMDS_OUTPUT_CONTROL_MASK, TMDS_OUTPUT_CONTROL_ACTIVE);
#endif
#if 0 //test pattern generate
WriteByteTPI(0xBC, 0x81);
I2C_WriteByte(0x72, 0xBD, 0x01); // Enable Auto soft reset on SCDT = 0
I2C_WriteByte(0x72, 0xBB, 0x1D);
#endif
#if 0 //new MHL cable
// Power Up
I2C_WriteByte(0x7A, 0x3D, 0x3F); // Power up CVCC 1.2V core
//I2C_WriteByte(0x7A, 0x3D, 0x37); // Power up CVCC 1.2V core
I2C_WriteByte(0x92, 0x11, 0x01); // Enable TxPLL Clock
I2C_WriteByte(0x92, 0x12, 0x15); // Enable Tx Clock Path & Equalizer
I2C_WriteByte(0x72, 0x08, 0x35); // Power Up TMDS Tx Core
//I2C_WriteByte(0x72, 0x08, 0x37); // Power Up TMDS Tx Core
// Analog PLL Control
I2C_WriteByte(0x92, 0x17, 0x03); // PLL Calrefsel
I2C_WriteByte(0x92, 0x1A, 0x20); // VCO Cal
I2C_WriteByte(0x92, 0x22, 0x8A); // Auto EQ
I2C_WriteByte(0x92, 0x23, 0x6A); // Auto EQ
I2C_WriteByte(0x92, 0x24, 0xAA); // Auto EQ
I2C_WriteByte(0x92, 0x25, 0xCA); // Auto EQ
I2C_WriteByte(0x92, 0x26, 0xEA); // Auto EQ
I2C_WriteByte(0x92, 0x4C, 0xA0); // Manual zone control
//I2C_WriteByte(0x92, 0x1C, 0x11); //daniel RX0_offset test
//I2C_WriteByte(0x92, 0x1D, 0x11); //daniel RX1_offset test
//I2C_WriteByte(0x92, 0x1E, 0x11); //daniel RX2_offset test
I2C_WriteByte(0x92, 0x4D, 0x00); // PLL Mode Value
I2C_WriteByte(0x72, 0x80, 0x14); // Enable Rx PLL Clock Value
//I2C_WriteByte(0x72, 0x80, 0x24); // Enable Rx PLL Clock Value
//I2C_WriteByte(0x72, 0x80, 0x34); // Enable Rx PLL Clock Value
I2C_WriteByte(0x92, 0x45, 0x44); // Rx PLL BW value from I2C
I2C_WriteByte(0x92, 0x31, 0x0A); // Rx PLL BW ~ 4MHz
I2C_WriteByte(0x72, 0xA0, 0xD0);
I2C_WriteByte(0x72, 0xA1, 0xFC); // Disable internal Mobile HD driver
I2C_WriteByte(0x72, 0xA3, 0xFF);
I2C_WriteByte(0x72, 0x2B, 0x01); // Enable HDCP Compliance workaround
// CBUS & Discovery
//ReadModifyWriteTPI(0x90, BIT_3 | BIT_2, BIT_3); // CBUS discovery cycle time for each drive and float = 150us
I2C_WriteByte(0x72, 0x91, 0xE5); // Skip RGND detection
I2C_WriteByte(0x72, 0x94, 0x66); // 1.8V CBUS VTH & GND threshold
//set bit 2 and 3, which is Initiator Timeout
//I2C_WriteByte(CBUS_SLAVE_ADDR, 0x31, I2C_ReadByte(CBUS_SLAVE_ADDR, 0x31) | 0x0c);
I2C_WriteByte(0x72, 0xA5, 0x00); // RGND Hysterisis.
I2C_WriteByte(0x72, 0x95, 0x31); // RGND & single discovery attempt (RGND blocking)
I2C_WriteByte(0x72, 0x96, 0x22); // use 1K and 2K setting
ReadModifyWriteTPI(0x95, SI_BIT_6, SI_BIT_6); // Force USB ID switch to open
WriteByteTPI(0x92, 0x46); // Force MHD mode
WriteByteTPI(0x93, 0xDC); // Disable CBUS pull-up during RGND measurement
//old cable
//WriteByteTPI(0x92, 0x86); // Force MHD mode
//WriteByteTPI(0x93, 0xCC); // Disable CBUS pull-up during RGND measurement
delay_ms(25);
ReadModifyWriteTPI(0x95, SI_BIT_6, 0x00); // Release USB ID switch
I2C_WriteByte(0x72, 0x90, 0x27); // Enable CBUS discovery
//InitCBusRegs();
I2C_WriteByte(0x72, 0x05, 0x04); // Enable Auto soft reset on SCDT = 0
I2C_WriteByte(0x72, 0x0D, 0x1C); // HDMI Transcode mode enable
WriteByteTPI(TPI_ENABLE, 0x00);
delay_ms(100);
WriteIndexedRegister(INDEXED_PAGE_0, 0xA0, 0x10);
//WriteByteCBUS(0x07, DDC_XLTN_TIMEOUT_MAX_VAL | 0x0E); // Increase DDC translation layer timer (burst mode)
//WriteByteCBUS(0x47, 0x03);
//WriteByteCBUS(0x21, 0x01); // Heartbeat Disable
delay_ms(100);
ReadModifyWriteTPI(TPI_SYSTEM_CONTROL_DATA_REG, TMDS_OUTPUT_CONTROL_MASK, TMDS_OUTPUT_CONTROL_ACTIVE);
#endif
#if 1 //0607 update
// Power Up
I2C_WriteByte(0x7A, 0x3D, 0x3F); // Power up CVCC 1.2V core
I2C_WriteByte(0x92, 0x11, 0x01); // Enable TxPLL Clock
I2C_WriteByte(0x92, 0x12, 0x15); // Enable Tx Clock Path & Equalizer
I2C_WriteByte(0x72, 0x08, 0x35); // Power Up TMDS Tx Core
I2C_WriteByte(0x92, 0x00, 0x00); // SIMG: correcting HW default
I2C_WriteByte(0x92, 0x13, 0x60); // SIMG: Set termination value
I2C_WriteByte(0x92, 0x14, 0xF0); // SIMG: Change CKDT level
I2C_WriteByte(0x92, 0x4B, 0x06); // SIMG: Correcting HW default
// Analog PLL Control
I2C_WriteByte(0x92, 0x17, 0x07); // SIMG: PLL Calrefsel
I2C_WriteByte(0x92, 0x1A, 0x20); // VCO Cal
I2C_WriteByte(0x92, 0x22, 0xE0); // SIMG: Auto EQ
I2C_WriteByte(0x92, 0x23, 0xC0); // SIMG: Auto EQ
I2C_WriteByte(0x92, 0x24, 0xA0); // SIMG: Auto EQ
I2C_WriteByte(0x92, 0x25, 0x80); // SIMG: Auto EQ
I2C_WriteByte(0x92, 0x26, 0x60); // SIMG: Auto EQ
I2C_WriteByte(0x92, 0x27, 0x40); // SIMG: Auto EQ
I2C_WriteByte(0x92, 0x28, 0x20); // SIMG: Auto EQ
I2C_WriteByte(0x92, 0x29, 0x00); // SIMG: Auto EQ
I2C_WriteByte(0x92, 0x4D, 0x02); // SIMG: PLL Mode Value (order is important)
I2C_WriteByte(0x92, 0x4C, 0xA0); // Manual zone control
I2C_WriteByte(0x72, 0x80, 0x14); // Enable Rx PLL Clock Value
I2C_WriteByte(0x92, 0x31, 0x0B); // SIMG: Rx PLL BW value from I2C BW ~ 4MHz
I2C_WriteByte(0x92, 0x45, 0x06); // SIMG: DPLL Mode
I2C_WriteByte(0x72, 0xA0, 0x10); // SIMG: Term mode
I2C_WriteByte(0x72, 0xA1, 0xFC); // Disable internal Mobile HD driver
I2C_WriteByte(0x72, 0xA3, 0xEB); // SIMG: Output Swing
I2C_WriteByte(0x72, 0xA6, 0x0C); // SIMG: Swing Offset
I2C_WriteByte(0x72, 0x2B, 0x01); // Enable HDCP Compliance workaround
// CBUS & Discovery
//ReadModifyWriteTPI(0x90, BIT_3 | BIT_2, BIT_3); // CBUS discovery cycle time for each drive and float = 150us
I2C_WriteByte(0x72, 0x91, 0xE5); // Skip RGND detection
I2C_WriteByte(0x72, 0x94, 0x66); // 1.8V CBUS VTH & GND threshold
//set bit 2 and 3, which is Initiator Timeout
//I2C_WriteByte(CBUS_SLAVE_ADDR, 0x31, I2C_ReadByte(CBUS_SLAVE_ADDR, 0x31) | 0x0c);
I2C_WriteByte(0x72, 0xA5, 0x80); // SIMG: RGND Hysterisis, 3x mode for Beast
I2C_WriteByte(0x72, 0x95, 0x31); // RGND & single discovery attempt (RGND blocking)
I2C_WriteByte(0x72, 0x96, 0x22); // use 1K and 2K setting
ReadModifyWriteTPI(0x95, SI_BIT_6, SI_BIT_6); // Force USB ID switch to open
//WriteByteTPI(0x92, 0x46); // Force MHD mode
//WriteByteTPI(0x93, 0xDC); // Disable CBUS pull-up during RGND measurement
//old cable
WriteByteTPI(0x92, 0x86); // Force MHD mode
WriteByteTPI(0x93, 0xCC); // Disable CBUS pull-up during RGND measurement
delay_ms(25);
ReadModifyWriteTPI(0x95, SI_BIT_6, 0x00); // Release USB ID switch
I2C_WriteByte(0x72, 0x90, 0x27); // Enable CBUS discovery
//InitCBusRegs();
I2C_WriteByte(0x72, 0x05, 0x04); // Enable Auto soft reset on SCDT = 0
I2C_WriteByte(0x72, 0x0D, 0x1C); // HDMI Transcode mode enable
WriteByteTPI(TPI_ENABLE, 0x00);
delay_ms(100);
WriteIndexedRegister(INDEXED_PAGE_0, 0xA0, 0x10);
WriteByteCBUS(0x07, DDC_XLTN_TIMEOUT_MAX_VAL | 0x0E); // Increase DDC translation layer timer (burst mode)
WriteByteCBUS(0x47, 0x03);
WriteByteCBUS(0x21, 0x01); // Heartbeat Disable
delay_ms(100);
ReadModifyWriteTPI(TPI_SYSTEM_CONTROL_DATA_REG, TMDS_OUTPUT_CONTROL_MASK, TMDS_OUTPUT_CONTROL_ACTIVE);
#endif
printk ("==[SIMG] sii9234_initial_registers_set END ==\n");
}
void sii9234_initial_registers_set(void)
{
pr_info("==[SIMG] sii9234_initial_registers_set Start ==\n");
/* Power Up */
I2C_WriteByte(0x7A, 0x3D, 0x3F); /* Power up CVCC 1.2V core */
I2C_WriteByte(0x92, 0x11, 0x01); /* Enable TxPLL Clock */
I2C_WriteByte(0x92, 0x12, 0x15); /* Enable Tx Clock Path
& Equalizer */
I2C_WriteByte(0x72, 0x08, 0x35); /* Power Up TMDS Tx Core */
I2C_WriteByte(0x92, 0x00, 0x00); /* SIMG: correcting HW
default */
I2C_WriteByte(0x92, 0x13, 0x60); /* SIMG: Set termination
value */
I2C_WriteByte(0x92, 0x14, 0xF0); /* SIMG: Change CKDT level */
I2C_WriteByte(0x92, 0x4B, 0x06); /* SIMG: Correcting
HW default */
/* Analog PLL Control */
I2C_WriteByte(0x92, 0x17, 0x07); /* SIMG: PLL Calrefsel */
I2C_WriteByte(0x92, 0x1A, 0x20); /* VCO Cal */
I2C_WriteByte(0x92, 0x22, 0xE0); /* SIMG: Auto EQ */
I2C_WriteByte(0x92, 0x23, 0xC0); /* SIMG: Auto EQ */
I2C_WriteByte(0x92, 0x24, 0xA0); /* SIMG: Auto EQ */
I2C_WriteByte(0x92, 0x25, 0x80); /* SIMG: Auto EQ */
I2C_WriteByte(0x92, 0x26, 0x60); /* SIMG: Auto EQ */
I2C_WriteByte(0x92, 0x27, 0x40); /* SIMG: Auto EQ */
I2C_WriteByte(0x92, 0x28, 0x20); /* SIMG: Auto EQ */
I2C_WriteByte(0x92, 0x29, 0x00); /* SIMG: Auto EQ */
I2C_WriteByte(0x92, 0x4D, 0x02); /* SIMG: PLL Mode Value
(order is important) */
I2C_WriteByte(0x92, 0x4C, 0xA0); /* Manual zone control */
I2C_WriteByte(0x72, 0x80, 0x14); /* Enable Rx PLL Clock Value */
I2C_WriteByte(0x92, 0x31, 0x0B); /* SIMG: Rx PLL BW value
from I2C BW ~ 4MHz */
I2C_WriteByte(0x92, 0x45, 0x06); /* SIMG: DPLL Mode */
I2C_WriteByte(0x72, 0xA0, 0x10); /* SIMG: Term mode */
I2C_WriteByte(0x72, 0xA1, 0xFC); /* Disable internal Mobile
HD driver */
I2C_WriteByte(0x72, 0xA3, 0xEB); /* SIMG: Output Swing */
I2C_WriteByte(0x72, 0xA6, 0x0C); /* SIMG: Swing Offset */
I2C_WriteByte(0x72, 0x2B, 0x01); /* Enable HDCP Compliance
workaround */
// CBUS & Discovery
#if 0
ReadModifyWriteTPI(0x90, BIT_3 | BIT_2,
BIT_3); /* CBUS discovery cycle time
for each drive and
float = 150us */
#endif
I2C_WriteByte(0x72, 0x91, 0xE5); /* Skip RGND detection */
I2C_WriteByte(0x72, 0x94, 0x66); /* 1.8V CBUS VTH &
GND threshold */
#if 0
/* set bit 2 and 3, which is Initiator Timeout */
I2C_WriteByte(CBUS_SLAVE_ADDR, 0x31,
I2C_ReadByte(CBUS_SLAVE_ADDR, 0x31) | 0x0c);
#endif
I2C_WriteByte(0x72, 0xA5, 0x80); /* SIMG: RGND Hysterisis,
3x mode for Beast */
I2C_WriteByte(0x72, 0x95, 0x31); /* RGND & single discovery
attempt (RGND blocking) */
I2C_WriteByte(0x72, 0x96, 0x22); /* use 1K and 2K setting */
ReadModifyWriteTPI(0x95, SI_BIT_6,
SI_BIT_6); /* Force USB ID switch open */
#if 0
WriteByteTPI(0x92, 0x46); /* Force MHD mode */
WriteByteTPI(0x93, 0xDC); /* Disable CBUS pull-up
during RGND measurement */
#else
/*old cable */
WriteByteTPI(0x92, 0x86); /* Force MHD mode */
WriteByteTPI(0x93, 0xCC); /* Disable CBUS pull-up
during RGND measurement */
#endif
mdelay(25);
ReadModifyWriteTPI(0x95, SI_BIT_6,
0x00); /* Release USB ID switch */
I2C_WriteByte(0x72, 0x90, 0x27); /* Enable CBUS discovery */
I2C_WriteByte(0x72, 0x05, 0x04); /* Enable Auto soft reset
on SCDT = 0 */
I2C_WriteByte(0x72, 0x0D, 0x1C); /* HDMI Transcode mode enable */
WriteByteTPI(TPI_ENABLE, 0x00);
mdelay(100);
WriteIndexedRegister(INDEXED_PAGE_0, 0xA0, 0x10);
WriteByteCBUS(0x07, DDC_XLTN_TIMEOUT_MAX_VAL
| 0x0E); /* Increase DDC translation layer
timer (burst mode) */
WriteByteCBUS(0x47, 0x03);
WriteByteCBUS(0x21, 0x01); /* Heartbeat Disable */
mdelay(100);
ReadModifyWriteTPI(TPI_SYSTEM_CONTROL_DATA_REG,
TMDS_OUTPUT_CONTROL_MASK, TMDS_OUTPUT_CONTROL_ACTIVE);
printk ("==[SIMG] sii9234_initial_registers_set END ==\n");
}
void MHD_INT_clear(void)
{
byte Int_state;
Int_state = ReadIndexedRegister(INDEXED_PAGE_0, 0x74);
WriteIndexedRegister(INDEXED_PAGE_0, 0x74, Int_state);
}
