/**
* RWPMIO - Read/Write PMIO
*
*
*
* @param[in] Address - PMIO Offset value
* @param[in] OpFlag - Access sizes
* @param[in] AndMask - Data And Mask 32 bits
* @param[in] OrMask - Data OR Mask 32 bits
*
*/
VOID
RWPMIO (
IN UINT8 Address,
IN UINT8 OpFlag,
IN UINT32 AndMask,
IN UINT32 OrMask
)
{
UINT32 Result;
OpFlag = OpFlag & 0x7f;
ReadPMIO (Address, OpFlag, &Result);
Result = (Result & AndMask) | OrMask;
WritePMIO (Address, OpFlag, &Result);
}
/*
* Reference section 5.2.9 Fixed ACPI Description Table (FADT)
* in the ACPI 3.0b specification.
*/
void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
{
u16 val = 0;
acpi_header_t *header = &(fadt->header);
printk(BIOS_DEBUG, "ACPI_BLK_BASE: 0x%04x\n", ACPI_BLK_BASE);
/* Prepare the header */
memset((void *)fadt, 0, sizeof(acpi_fadt_t));
memcpy(header->signature, "FACP", 4);
header->length = sizeof(acpi_fadt_t);
header->revision = ACPI_FADT_REV_ACPI_3_0;
memcpy(header->oem_id, OEM_ID, 6);
memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
memcpy(header->asl_compiler_id, ASLC, 4);
header->asl_compiler_revision = 0;
if ((uintptr_t)facs > 0xffffffff)
printk(BIOS_DEBUG, "ACPI: FACS lives above 4G\n");
else
fadt->firmware_ctrl = (uintptr_t)facs;
if ((uintptr_t)dsdt > 0xffffffff)
printk(BIOS_DEBUG, "ACPI: DSDT lives above 4G\n");
else
fadt->dsdt = (uintptr_t)dsdt;
fadt->model = 0; /* reserved, should be 0 ACPI 3.0 */
fadt->preferred_pm_profile = FADT_PM_PROFILE;
fadt->sci_int = 9; /* HUDSON 1 - IRQ 09 – ACPI SCI */
fadt->smi_cmd = 0; /* disable system management mode */
fadt->acpi_enable = 0; /* unused if SMI_CMD = 0 */
fadt->acpi_disable = 0; /* unused if SMI_CMD = 0 */
fadt->s4bios_req = 0; /* unused if SMI_CMD = 0 */
fadt->pstate_cnt = 0; /* unused if SMI_CMD = 0 */
val = PM1_EVT_BLK_ADDRESS;
WritePMIO(SB_PMIOA_REG60, AccWidthUint16, &val);
val = PM1_CNT_BLK_ADDRESS;
WritePMIO(SB_PMIOA_REG62, AccWidthUint16, &val);
val = PM1_TMR_BLK_ADDRESS;
WritePMIO(SB_PMIOA_REG64, AccWidthUint16, &val);
val = GPE0_BLK_ADDRESS;
WritePMIO(SB_PMIOA_REG68, AccWidthUint16, &val);
/* CpuControl is in \_PR.CP00, 6 bytes */
val = CPU_CNT_BLK_ADDRESS;
WritePMIO(SB_PMIOA_REG66, AccWidthUint16, &val);
val = 0;
WritePMIO(SB_PMIOA_REG6A, AccWidthUint16, &val);
val = ACPI_PMA_CNT_BLK_ADDRESS;
WritePMIO(SB_PMIOA_REG6E, AccWidthUint16, &val);
/* AcpiDecodeEnable, When set, SB uses the contents of the
* PM registers at index 60-6B to decode ACPI I/O address.
* AcpiSmiEn & SmiCmdEn*/
val = BIT0 | BIT1 | BIT2 | BIT4;
WritePMIO(SB_PMIOA_REG74, AccWidthUint16, &val);
/* RTC_En_En, TMR_En_En, GBL_EN_EN */
outl(0x1, PM1_CNT_BLK_ADDRESS); /* set SCI_EN */
fadt->pm1a_evt_blk = PM1_EVT_BLK_ADDRESS;
fadt->pm1b_evt_blk = 0x0000;
fadt->pm1a_cnt_blk = PM1_CNT_BLK_ADDRESS;
fadt->pm1b_cnt_blk = 0x0000;
fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK_ADDRESS;
fadt->pm_tmr_blk = PM1_TMR_BLK_ADDRESS;
fadt->gpe0_blk = GPE0_BLK_ADDRESS;
fadt->gpe1_blk = 0; /* No gpe1 block in hudson1 */
fadt->pm1_evt_len = 4; /* 32 bits */
fadt->pm1_cnt_len = 2; /* 16 bits */
fadt->pm2_cnt_len = 1; /* 8 bits */
fadt->pm_tmr_len = 4; /* 32 bits */
fadt->gpe0_blk_len = 8; /* 64 bits */
fadt->gpe1_blk_len = 0;
fadt->gpe1_base = 0;
fadt->cst_cnt = 0x00; /* unused if SMI_CMD = 0 */
fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
fadt->flush_size = 0; /* set to 0 if WBINVD is 1 in flags */
fadt->flush_stride = 0; /* set to 0 if WBINVD is 1 in flags */
fadt->duty_offset = 1; /* CLK_VAL bits 3:1 */
fadt->duty_width = 3; /* CLK_VAL bits 3:1 */
fadt->day_alrm = 0; /* 0x7d these have to be */
fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */
fadt->century = 0; /* 0x7f to make rtc alarm work */
fadt->iapc_boot_arch = FADT_BOOT_ARCH; /* See table 5-10 */
fadt->res2 = 0; /* reserved, MUST be 0 ACPI 3.0 */
fadt->flags = ACPI_FADT_WBINVD | /* See table 5-10 ACPI 3.0a spec */
ACPI_FADT_C1_SUPPORTED |
ACPI_FADT_SLEEP_BUTTON |
ACPI_FADT_S4_RTC_WAKE |
ACPI_FADT_32BIT_TIMER |
ACPI_FADT_RESET_REGISTER |
ACPI_FADT_PCI_EXPRESS_WAKE |
ACPI_FADT_S4_RTC_VALID |
ACPI_FADT_REMOTE_POWER_ON;
/* Format is from 5.2.3.1: Generic Address Structure */
/* reset_reg: see section 4.7.3.6 ACPI 3.0a spec */
/* 8 bit write of value 0x06 to 0xCF9 in IO space */
fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO;
fadt->reset_reg.bit_width = 8;
fadt->reset_reg.bit_offset = 0;
fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
fadt->reset_reg.addrl = 0xcf9;
fadt->reset_reg.addrh = 0x0;
fadt->reset_value = 6;
fadt->res3 = 0; /* reserved, MUST be 0 ACPI 3.0 */
fadt->res4 = 0; /* reserved, MUST be 0 ACPI 3.0 */
fadt->res5 = 0; /* reserved, MUST be 0 ACPI 3.0 */
fadt->x_firmware_ctl_l = ((uintptr_t)facs) & 0xffffffff;
fadt->x_firmware_ctl_h = ((uint64_t)(uintptr_t)facs) >> 32;
fadt->x_dsdt_l = ((uintptr_t)dsdt) & 0xffffffff;
fadt->x_dsdt_h = ((uint64_t)(uintptr_t)dsdt) >> 32;
fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
fadt->x_pm1a_evt_blk.bit_width = 32;
fadt->x_pm1a_evt_blk.bit_offset = 0;
fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
fadt->x_pm1a_evt_blk.addrl = PM1_EVT_BLK_ADDRESS;
fadt->x_pm1a_evt_blk.addrh = 0x0;
fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
fadt->x_pm1b_evt_blk.bit_width = 0;
fadt->x_pm1b_evt_blk.bit_offset = 0;
fadt->x_pm1b_evt_blk.access_size = 0;
fadt->x_pm1b_evt_blk.addrl = 0x0;
fadt->x_pm1b_evt_blk.addrh = 0x0;
fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
fadt->x_pm1a_cnt_blk.bit_width = 16;
fadt->x_pm1a_cnt_blk.bit_offset = 0;
fadt->x_pm1a_cnt_blk.access_size = 0;
fadt->x_pm1a_cnt_blk.addrl = PM1_CNT_BLK_ADDRESS;
fadt->x_pm1a_cnt_blk.addrh = 0x0;
fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
fadt->x_pm1b_cnt_blk.bit_width = 0;
fadt->x_pm1b_cnt_blk.bit_offset = 0;
fadt->x_pm1b_cnt_blk.access_size = 0;
fadt->x_pm1b_cnt_blk.addrl = 0x0;
fadt->x_pm1b_cnt_blk.addrh = 0x0;
fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
fadt->x_pm2_cnt_blk.bit_width = 8; /* Hudson 1 Pm2Control is 8 bits */
fadt->x_pm2_cnt_blk.bit_offset = 0;
fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK_ADDRESS;
fadt->x_pm2_cnt_blk.addrh = 0x0;
fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO;
fadt->x_pm_tmr_blk.bit_width = 32;
fadt->x_pm_tmr_blk.bit_offset = 0;
fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
fadt->x_pm_tmr_blk.addrl = PM1_TMR_BLK_ADDRESS;
fadt->x_pm_tmr_blk.addrh = 0x0;
fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO;
fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + Event Enable */
fadt->x_gpe0_blk.bit_offset = 0;
fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
fadt->x_gpe0_blk.addrl = GPE0_BLK_ADDRESS;
fadt->x_gpe0_blk.addrh = 0x0;
fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO;
fadt->x_gpe1_blk.bit_width = 0;
fadt->x_gpe1_blk.bit_offset = 0;
fadt->x_gpe1_blk.access_size = 0;
fadt->x_gpe1_blk.addrl = 0;
fadt->x_gpe1_blk.addrh = 0x0;
header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t));
}
/* pm_base should be got from bar2 of sb900. Here I compact ACPI
* registers into 32 bytes limit.
* */
#define ACPI_PM_EVT_BLK (pm_base + 0x00) /* 4 bytes */
#define ACPI_PM1_CNT_BLK (pm_base + 0x04) /* 2 bytes */
#define ACPI_PM2_CNT_BLK (pm_base + 0x0F) /* 1 byte */
#define ACPI_PM_TMR_BLK (pm_base + 0x08) /* 4 bytes */
#define ACPI_GPE0_BLK (pm_base + 0x20) /* 8 bytes */
#define ACPI_CPU_CONTORL (pm_base + 0x10) /* 6 bytes */
void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
{
u16 val = 0;
acpi_header_t *header = &(fadt->header);
pm_base &= 0xFFFF;
printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base);
/* Prepare the header */
memset((void *)fadt, 0, sizeof(acpi_fadt_t));
memcpy(header->signature, "FACP", 4);
header->length = 244;
header->revision = 1;
memcpy(header->oem_id, OEM_ID, 6);
memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
memcpy(header->asl_compiler_id, ASLC, 4);
header->asl_compiler_revision = 0;
fadt->firmware_ctrl = (u32) facs;
fadt->dsdt = (u32) dsdt;
/* 3=Workstation,4=Enterprise Server, 7=Performance Server */
fadt->preferred_pm_profile = 0x03;
fadt->sci_int = 9;
/* disable system management mode by setting to 0: */
fadt->smi_cmd = 0;
fadt->acpi_enable = 0xf0;
fadt->acpi_disable = 0xf1;
fadt->s4bios_req = 0x0;
fadt->pstate_cnt = 0xe2;
val = PM1_EVT_BLK_ADDRESS;
WritePMIO(SB_PMIOA_REG60, AccWidthUint16, &val);
val = PM1_CNT_BLK_ADDRESS;
WritePMIO(SB_PMIOA_REG62, AccWidthUint16, &val);
val = PM1_TMR_BLK_ADDRESS;
WritePMIO(SB_PMIOA_REG64, AccWidthUint16, &val);
val = GPE0_BLK_ADDRESS;
WritePMIO(SB_PMIOA_REG68, AccWidthUint16, &val);
/* CpuControl is in \_PR.CP00, 6 bytes */
val = CPU_CNT_BLK_ADDRESS;
WritePMIO(SB_PMIOA_REG66, AccWidthUint16, &val);
val = 0;
WritePMIO(SB_PMIOA_REG6A, AccWidthUint16, &val);
val = ACPI_PM2_CNT_BLK;
WritePMIO(SB_PMIOA_REG6E, AccWidthUint16, &val);
/* AcpiDecodeEnable, When set, SB uses the contents of the
* PM registers at index 60-6B to decode ACPI I/O address.
* AcpiSmiEn & SmiCmdEn */
val = BIT0 | BIT1 | BIT2 | BIT4;
WritePMIO(SB_PMIOA_REG74, AccWidthUint16, &val);
/* RTC_En_En, TMR_En_En, GBL_EN_EN */
outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */
fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK;
fadt->pm1b_evt_blk = 0x0000;
fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK;
fadt->pm1b_cnt_blk = 0x0000;
fadt->pm2_cnt_blk = ACPI_PM2_CNT_BLK;
fadt->pm_tmr_blk = ACPI_PM_TMR_BLK;
fadt->gpe0_blk = ACPI_GPE0_BLK;
fadt->gpe1_blk = 0x0000; /* we dont have gpe1 block, do we? */
fadt->pm1_evt_len = 4;
fadt->pm1_cnt_len = 2;
fadt->pm2_cnt_len = 1;
fadt->pm_tmr_len = 4;
fadt->gpe0_blk_len = 8;
fadt->gpe1_blk_len = 0;
fadt->gpe1_base = 0;
fadt->cst_cnt = 0xe3;
fadt->p_lvl2_lat = 101;
fadt->p_lvl3_lat = 1001;
fadt->flush_size = 0;
fadt->flush_stride = 0;
fadt->duty_offset = 1;
fadt->duty_width = 3;
fadt->day_alrm = 0; /* 0x7d these have to be */
fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */
fadt->century = 0; /* 0x7f to make rtc alrm work */
fadt->iapc_boot_arch = 0x3; /* See table 5-11 */
fadt->flags = 0x0001c1a5;/* 0x25; */
fadt->res2 = 0;
fadt->reset_reg.space_id = 1;
fadt->reset_reg.bit_width = 8;
fadt->reset_reg.bit_offset = 0;
fadt->reset_reg.resv = 0;
fadt->reset_reg.addrl = 0xcf9;
fadt->reset_reg.addrh = 0x0;
fadt->reset_value = 6;
fadt->x_firmware_ctl_l = (u32) facs;
fadt->x_firmware_ctl_h = 0;
fadt->x_dsdt_l = (u32) dsdt;
fadt->x_dsdt_h = 0;
fadt->x_pm1a_evt_blk.space_id = 1;
fadt->x_pm1a_evt_blk.bit_width = 32;
fadt->x_pm1a_evt_blk.bit_offset = 0;
fadt->x_pm1a_evt_blk.resv = 0;
fadt->x_pm1a_evt_blk.addrl = ACPI_PM_EVT_BLK;
fadt->x_pm1a_evt_blk.addrh = 0x0;
fadt->x_pm1b_evt_blk.space_id = 1;
fadt->x_pm1b_evt_blk.bit_width = 4;
fadt->x_pm1b_evt_blk.bit_offset = 0;
fadt->x_pm1b_evt_blk.resv = 0;
fadt->x_pm1b_evt_blk.addrl = 0x0;
fadt->x_pm1b_evt_blk.addrh = 0x0;
fadt->x_pm1a_cnt_blk.space_id = 1;
fadt->x_pm1a_cnt_blk.bit_width = 16;
fadt->x_pm1a_cnt_blk.bit_offset = 0;
fadt->x_pm1a_cnt_blk.resv = 0;
fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK;
fadt->x_pm1a_cnt_blk.addrh = 0x0;
fadt->x_pm1b_cnt_blk.space_id = 1;
fadt->x_pm1b_cnt_blk.bit_width = 2;
fadt->x_pm1b_cnt_blk.bit_offset = 0;
fadt->x_pm1b_cnt_blk.resv = 0;
fadt->x_pm1b_cnt_blk.addrl = 0x0;
fadt->x_pm1b_cnt_blk.addrh = 0x0;
fadt->x_pm2_cnt_blk.space_id = 1;
fadt->x_pm2_cnt_blk.bit_width = 0;
fadt->x_pm2_cnt_blk.bit_offset = 0;
fadt->x_pm2_cnt_blk.resv = 0;
fadt->x_pm2_cnt_blk.addrl = ACPI_PM2_CNT_BLK;
fadt->x_pm2_cnt_blk.addrh = 0x0;
fadt->x_pm_tmr_blk.space_id = 1;
fadt->x_pm_tmr_blk.bit_width = 32;
fadt->x_pm_tmr_blk.bit_offset = 0;
fadt->x_pm_tmr_blk.resv = 0;
fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK;
fadt->x_pm_tmr_blk.addrh = 0x0;
fadt->x_gpe0_blk.space_id = 1;
fadt->x_gpe0_blk.bit_width = 32;
fadt->x_gpe0_blk.bit_offset = 0;
fadt->x_gpe0_blk.resv = 0;
fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK;
fadt->x_gpe0_blk.addrh = 0x0;
fadt->x_gpe1_blk.space_id = 1;
fadt->x_gpe1_blk.bit_width = 0;
fadt->x_gpe1_blk.bit_offset = 0;
fadt->x_gpe1_blk.resv = 0;
fadt->x_gpe1_blk.addrl = 0;
fadt->x_gpe1_blk.addrh = 0x0;
header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t));
}
/*---------------------------------------------------------------------------------------
* L O C A L F U N C T I O N S
*---------------------------------------------------------------------------------------
*/
void
gpioEarlyInit(
void
)
{
u8 Flags;
u8 Data8 = 0;
u8 StripInfo = 0;
u8 BoardType = 1;
u8 RegIndex8 = 0;
u8 boardRevC = 0x2;
u16 Data16 = 0;
u32 Index = 0;
u32 AcpiMmioAddr = 0;
u32 GpioMmioAddr = 0;
u32 IoMuxMmioAddr = 0;
u32 MiscMmioAddr = 0;
u32 SmiMmioAddr = 0;
u32 andMask32 = 0;
// Enable HUDSON MMIO Base (AcpiMmioAddr)
ReadPMIO (SB_PMIOA_REG24, AccWidthUint8, &Data8);
Data8 |= BIT0;
WritePMIO (SB_PMIOA_REG24, AccWidthUint8, &Data8);
// Get HUDSON MMIO Base (AcpiMmioAddr)
ReadPMIO (SB_PMIOA_REG24 + 3, AccWidthUint8, &Data8);
Data16 = Data8 << 8;
ReadPMIO (SB_PMIOA_REG24 + 2, AccWidthUint8, &Data8);
Data16 |= Data8;
AcpiMmioAddr = (u32)Data16 << 16;
GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
IoMuxMmioAddr = AcpiMmioAddr + IOMUX_BASE;
MiscMmioAddr = AcpiMmioAddr + MISC_BASE;
Data8 = Mmio8_G (MiscMmioAddr, SB_MISC_REG80);
if ((Data8 & BIT4) == 0) {
BoardType = 0; // external clock board
}
Data8 = Mmio8_G (GpioMmioAddr, GPIO_30);
StripInfo = (Data8 & BIT7) >> 7;
Data8 = Mmio8_G (GpioMmioAddr, GPIO_31);
StripInfo |= (Data8 & BIT7) >> 6;
if (StripInfo < boardRevC) { // for old board. Rev B
Mmio8_And_Or (IoMuxMmioAddr, GPIO_111, 0x00, 3); // function 3
Mmio8_And_Or (IoMuxMmioAddr, GPIO_113, 0x00, 0); // function 0
}
for (Index = 0; Index < MAX_GPIO_NO; Index++) {
if (!(((Index >= GPIO_RSVD_ZONE0_S) && (Index <= GPIO_RSVD_ZONE0_E)) || ((Index >= GPIO_RSVD_ZONE1_S) && (Index <= GPIO_RSVD_ZONE1_E)))) {
if ((StripInfo >= boardRevC) || ((Index != GPIO_111) && (Index != GPIO_113))) {
// Configure multi-funtion
Mmio8_And_Or (IoMuxMmioAddr, Index, 0x00, (gpio_table[Index].select & ~NonGpio));
}
// Configure GPIO
if(!((gpio_table[Index].NonGpioGevent & NonGpio))) {
Mmio8_And_Or (GpioMmioAddr, Index, 0xDF, gpio_table[Index].type);
Mmio8_And_Or (GpioMmioAddr, Index, 0xA3, gpio_table[Index].value);
}
if (Index == GPIO_65) {
if ( BoardType == 0 ) {
Mmio8_And_Or (IoMuxMmioAddr, GPIO_65, 0x00, 3); // function 3
}
}
}
// Configure GEVENT
if ((Index >= GEVENT_00) && (Index <= GEVENT_23) && ((gevent_table[Index - GEVENT_00].EventEnable))) {
SmiMmioAddr = AcpiMmioAddr + SMI_BASE;
andMask32 = ~(1 << (Index - GEVENT_00));
//EventEnable: 0-Disable, 1-Enable
Mmio32_And_Or (SmiMmioAddr, SMIREG_EVENT_ENABLE, andMask32, (gevent_table[Index - GEVENT_00].EventEnable << (Index - GEVENT_00)));
//SciTrig: 0-Falling Edge, 1-Rising Edge
Mmio32_And_Or (SmiMmioAddr, SMIREG_SCITRIG, andMask32, (gevent_table[Index - GEVENT_00].SciTrig << (Index - GEVENT_00)));
//SciLevl: 0-Edge trigger, 1-Level Trigger
Mmio32_And_Or (SmiMmioAddr, SMIREG_SCILEVEL, andMask32, (gevent_table[Index - GEVENT_00].SciLevl << (Index - GEVENT_00)));
//SmiSciEn: 0-Not send SMI, 1-Send SMI
Mmio32_And_Or (SmiMmioAddr, SMIREG_SMISCIEN, andMask32, (gevent_table[Index - GEVENT_00].SmiSciEn << (Index - GEVENT_00)));
//SciS0En: 0-Disable, 1-Enable
Mmio32_And_Or (SmiMmioAddr, SMIREG_SCIS0EN, andMask32, (gevent_table[Index - GEVENT_00].SciS0En << (Index - GEVENT_00)));
//SciMap: 00000b ~ 11111b
RegIndex8=(u8)((Index - GEVENT_00) >> 2);
Data8=(u8)(((Index - GEVENT_00) & 0x3) * 8);
Mmio32_And_Or (SmiMmioAddr, SMIREG_SCIMAP0+RegIndex8, ~(GEVENT_SCIMASK << Data8), (gevent_table[Index - GEVENT_00].SciMap << Data8));
//SmiTrig: 0-Active Low, 1-Active High
Mmio32_And_Or (SmiMmioAddr, SMIREG_SMITRIG, ~(gevent_table[Index - GEVENT_00].SmiTrig << (Index - GEVENT_00)), (gevent_table[Index - GEVENT_00].SmiTrig << (Index - GEVENT_00)));
//SmiControl: 0-Disable, 1-SMI, 2-NMI, 3-IRQ13
RegIndex8=(u8)((Index - GEVENT_00) >> 4);
Data8=(u8)(((Index - GEVENT_00) & 0xF) * 2);
Mmio32_And_Or (SmiMmioAddr, SMIREG_SMICONTROL0+RegIndex8, ~(SMICONTROL_MASK << Data8), (gevent_table[Index - GEVENT_00].SmiControl << Data8));
}
}
