/* * * This function setups the interrupt system so interrupts can occur for the * DMA. This function assumes INTC component exists in the hardware system. * * @param AxiDmaPtr is a pointer to the instance of the DMA engine * @param ReadIntrId is the read channel Interrupt ID. * @param WriteIntrId is the write channel Interrupt ID. * * @return XST_SUCCESS if successful, otherwise XST_FAILURE. * * @note None. * ******************************************************************************/ static int SetupIntrSystem(XAxiVdma *AxiVdmaPtr, u16 ReadIntrId, u16 WriteIntrId) { int Status; XIntc *IntcInstancePtr =&Intc; /* Initialize the interrupt controller and connect the ISRs */ Status = XIntc_Initialize(IntcInstancePtr, XPAR_INTC_0_DEVICE_ID); if (Status != XST_SUCCESS) { xil_printf( "Failed init intc\r\n"); return XST_FAILURE; } Status = XIntc_Connect(IntcInstancePtr, ReadIntrId, (XInterruptHandler)XAxiVdma_ReadIntrHandler, AxiVdmaPtr); if (Status != XST_SUCCESS) { xil_printf("Failed read channel connect intc %d\r\n", Status); return XST_FAILURE; } Status = XIntc_Connect(IntcInstancePtr, WriteIntrId, (XInterruptHandler)XAxiVdma_WriteIntrHandler, AxiVdmaPtr); if (Status != XST_SUCCESS) { xil_printf("Failed write channel connect intc %d\r\n", Status); return XST_FAILURE; } /* Start the interrupt controller */ Status = XIntc_Start(IntcInstancePtr, XIN_REAL_MODE); if (Status != XST_SUCCESS) { xil_printf( "Failed to start intc\r\n"); return XST_FAILURE; } /* Enable interrupts from the hardware */ XIntc_Enable(IntcInstancePtr, ReadIntrId); XIntc_Enable(IntcInstancePtr, WriteIntrId); Xil_ExceptionInit(); Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT, (Xil_ExceptionHandler)XIntc_InterruptHandler, (void *)IntcInstancePtr); Xil_ExceptionEnable(); /* Register call-back functions */ XAxiVdma_SetCallBack(AxiVdmaPtr, XAXIVDMA_HANDLER_GENERAL, ReadCallBack, (void *)AxiVdmaPtr, XAXIVDMA_READ); XAxiVdma_SetCallBack(AxiVdmaPtr, XAXIVDMA_HANDLER_ERROR, ReadErrorCallBack, (void *)AxiVdmaPtr, XAXIVDMA_READ); XAxiVdma_SetCallBack(AxiVdmaPtr, XAXIVDMA_HANDLER_GENERAL, WriteCallBack, (void *)AxiVdmaPtr, XAXIVDMA_WRITE); XAxiVdma_SetCallBack(AxiVdmaPtr, XAXIVDMA_HANDLER_ERROR, WriteErrorCallBack, (void *)AxiVdmaPtr, XAXIVDMA_WRITE); return XST_SUCCESS; }
/** * * Main function * * This function is the main entry point of the example on DMA core. It sets up * DMA engine to be ready to receive and send frames, and start the transfers. * It waits for the transfer of the specified number of frame sets, and check * for transfer errors. * * @return * - XST_SUCCESS if example finishes successfully * - XST_FAILURE if example fails. * * @note None. * ******************************************************************************/ int vdma_setup(XIntc controller) { Intc = controller; int Status; XAxiVdma_Config *Config; XAxiVdma_FrameCounter FrameCfg; WriteDone = 0; ReadDone = 0; WriteError = 0; ReadError = 0; ReadFrameAddr = READ_ADDRESS_BASE; WriteFrameAddr = WRITE_ADDRESS_BASE; xil_printf("\r\n--- Entering vdma_setup() --- \r\n"); /* The information of the XAxiVdma_Config comes from hardware build. * The user IP should pass this information to the AXI DMA core. */ Config = XAxiVdma_LookupConfig(DMA_DEVICE_ID); if (!Config) { xil_printf( "No video DMA found for ID %d\r\n", DMA_DEVICE_ID); return XST_FAILURE; } /* Initialize DMA engine */ Status = XAxiVdma_CfgInitialize(&AxiVdma, Config, Config->BaseAddress); if (Status != XST_SUCCESS) { xil_printf( "Configuration Initialization failed %d\r\n", Status); return XST_FAILURE; } Status = XAxiVdma_SetFrmStore(&AxiVdma, NUMBER_OF_READ_FRAMES, XAXIVDMA_READ); if (Status != XST_SUCCESS) { xil_printf( "Setting Frame Store Number Failed in Read Channel" " %d\r\n", Status); return XST_FAILURE; } Status = XAxiVdma_SetFrmStore(&AxiVdma, NUMBER_OF_WRITE_FRAMES, XAXIVDMA_WRITE); if (Status != XST_SUCCESS) { xil_printf( "Setting Frame Store Number Failed in Write Channel" " %d\r\n", Status); return XST_FAILURE; } /* Setup frame counter and delay counter for both channels * * This is to monitor the progress of the test only * * WARNING: In free-run mode, interrupts may overwhelm the system. * In that case, it is better to disable interrupts. */ FrameCfg.ReadFrameCount = NUMBER_OF_READ_FRAMES; FrameCfg.WriteFrameCount = NUMBER_OF_WRITE_FRAMES; FrameCfg.ReadDelayTimerCount = DELAY_TIMER_COUNTER; FrameCfg.WriteDelayTimerCount = DELAY_TIMER_COUNTER; Status = XAxiVdma_SetFrameCounter(&AxiVdma, &FrameCfg); if (Status != XST_SUCCESS) { xil_printf( "Set frame counter failed %d\r\n", Status); if(Status == XST_VDMA_MISMATCH_ERROR) xil_printf("DMA Mismatch Error\r\n"); return XST_FAILURE; } /* * Setup your video IP that writes to the memory */ /* Setup the write channel */ Status = WriteSetup(&AxiVdma); if (Status != XST_SUCCESS) { xil_printf( "Write channel setup failed %d\r\n", Status); if(Status == XST_VDMA_MISMATCH_ERROR) xil_printf("DMA Mismatch Error\r\n"); return XST_FAILURE; } /* * Setup your video IP that reads from the memory */ /* Setup the read channel */ Status = ReadSetup(&AxiVdma); if (Status != XST_SUCCESS) { xil_printf( "Read channel setup failed %d\r\n", Status); if(Status == XST_VDMA_MISMATCH_ERROR) xil_printf("DMA Mismatch Error\r\n"); return XST_FAILURE; } Status = SetupIntrSystem(&AxiVdma, READ_INTR_ID, WRITE_INTR_ID); if (Status != XST_SUCCESS) { xil_printf( "Setup interrupt system failed %d\r\n", Status); return XST_FAILURE; } /* Register callback functions */ // XAxiVdma_SetCallBack(&AxiVdma, XAXIVDMA_HANDLER_GENERAL, ReadCallBack, // (void *)&AxiVdma, XAXIVDMA_READ); // // XAxiVdma_SetCallBack(&AxiVdma, XAXIVDMA_HANDLER_ERROR, // ReadErrorCallBack, (void *)&AxiVdma, XAXIVDMA_READ); XAxiVdma_SetCallBack(&AxiVdma, XAXIVDMA_HANDLER_GENERAL, WriteCallBack, (void *)&AxiVdma, XAXIVDMA_WRITE); XAxiVdma_SetCallBack(&AxiVdma, XAXIVDMA_HANDLER_ERROR, WriteErrorCallBack, (void *)&AxiVdma, XAXIVDMA_WRITE); /* Enable your video IP interrupts if needed */ /* Start the DMA engine to transfer */ Status = StartTransfer(&AxiVdma); if (Status != XST_SUCCESS) { if(Status == XST_VDMA_MISMATCH_ERROR) xil_printf("DMA Mismatch Error\r\n"); return XST_FAILURE; } /* Enable DMA read and write channel interrupts * * If interrupts overwhelms the system, please do not enable interrupt */ // XAxiVdma_IntrEnable(&AxiVdma, XAXIVDMA_IXR_FRMCNT_MASK, XAXIVDMA_WRITE); // XAxiVdma_IntrEnable(&AxiVdma, XAXIVDMA_IXR_FRMCNT_MASK, XAXIVDMA_READ); /* Every set of frame buffer finish causes a completion interrupt */ // while ((WriteDone < NUM_TEST_FRAME_SETS) && !ReadError && // (ReadDone < NUM_TEST_FRAME_SETS) && !WriteError) { // /* NOP */ // } // if (ReadError || WriteError) { // xil_printf("Test has transfer error %d/%d\r\n", // ReadError, WriteError); // // Status = XST_FAILURE; // } // else { // xil_printf("Test passed\r\n"); // } xil_printf("\r\n--- Exiting vdma_setup() --- \r\n"); // DisableIntrSystem(READ_INTR_ID, WRITE_INTR_ID); if (Status != XST_SUCCESS) { if(Status == XST_VDMA_MISMATCH_ERROR) xil_printf("DMA Mismatch Error\r\n"); return XST_FAILURE; } return XST_SUCCESS; }