int main ()
{
u32 gpio_1_in = 0;
u32 gpio_1_out = 0;
char menu_selection = 0;
char string[4] = "0000";
// Configuration options
u16 mac_addr_dest_byte_5_4 = 0;
u16 mac_addr_dest_byte_3_2 = 0;
u16 mac_addr_dest_byte_1_0 = 0;
u16 mac_addr_src_byte_5_4 = 0;
u16 mac_addr_src_byte_3_2 = 0;
u16 mac_addr_src_byte_1_0 = 0;
u16 ip_addr_dest_byte_3_2 = 0;
u16 ip_addr_dest_byte_1_0 = 0;
u16 ip_addr_src_byte_3_2 = 0;
u16 ip_addr_src_byte_1_0 = 0;
u16 port_dest = 0;
u16 port_src = 0;
u16 payload_size = 0;
u16 fft_size = 0;
u16 threshold_byte_3_2 = 0;
u16 threshold_byte_1_0 = 0;
u16 ctrl_flags = 0;
u8 override = 0;
u8 send_fft = 0;
u8 send_threshold = 0;
u8 send_mag_squared = 0;
u8 send_cnt_pattern = 0;
// User interface
while(TRUE)
{
xil_printf("\r\n");
xil_printf("\r\n");
xil_printf("-----------------------------------------------------------\r\n");
xil_printf("-- CRUSH --\r\n");
xil_printf("-- Cognitive Radio Universal Software Hardware --\r\n");
xil_printf("-- Jonathon Pendlum --\r\n");
xil_printf("-----------------------------------------------------------\r\n");
xil_printf("\r\n");
gpio_1_in = XIo_In32(XPAR_AXI_GPIO_0_BASEADDR);
xil_printf("USRP Connected:\t\t\t");
if ((gpio_1_in & MASK_RX_DATA_CLK_LOCKED) == TRUE) xil_printf("TRUE\r\n");
else xil_printf("FALSE\r\n");
xil_printf("RX Data PLL Phase Offset:\t%d\r\n",(gpio_1_in >> OFFSET_PHASE_CNT) & MASK_PHASE_CNT);
xil_printf("Source MAC Address:\t\t%02x:%02x:%02x:%02x:%02x:%02x\r\n",
mac_addr_src_byte_5_4 >> 8, mac_addr_src_byte_5_4 & 0x00FF, mac_addr_src_byte_3_2 >> 8,
mac_addr_src_byte_3_2 & 0x00FF, mac_addr_src_byte_1_0 >> 8, mac_addr_src_byte_1_0 & 0x00FF);
xil_printf("Destination MAC Address:\t%02x:%02x:%02x:%02x:%02x:%02x\r\n",
mac_addr_dest_byte_5_4 >> 8, mac_addr_dest_byte_5_4 & 0x00FF, mac_addr_dest_byte_3_2 >> 8,
mac_addr_dest_byte_3_2 & 0x00FF, mac_addr_dest_byte_1_0 >> 8, mac_addr_dest_byte_1_0 & 0x00FF);
xil_printf("Source IP Address:\t\t%d.%d.%d.%d\r\n",
ip_addr_src_byte_3_2 >> 8, ip_addr_src_byte_3_2 & 0x00FF,
ip_addr_src_byte_1_0 >> 8, ip_addr_src_byte_1_0 & 0x00FF);
xil_printf("Destination IP Address:\t\t%d.%d.%d.%d\r\n",
ip_addr_dest_byte_3_2 >> 8, ip_addr_dest_byte_3_2 & 0x00FF,
ip_addr_dest_byte_1_0 >> 8, ip_addr_dest_byte_1_0 & 0x00FF);
xil_printf("Source Port Address:\t\t%d\r\n",port_src);
xil_printf("Destination Port Address:\t%d\r\n", port_dest);
xil_printf("Payload Size:\t\t\t%d\r\n", payload_size);
xil_printf("FFT Size:\t\t\t%d\r\n", fft_size);
xil_printf("Threshold:\t\t\t%d\r\n", (threshold_byte_3_2 << 8) + threshold_byte_1_0);
xil_printf("Flags Enabled: ");
if (override == 1) xil_printf("Override ");
if (send_fft == 1) xil_printf("Send FFT ");
if (send_threshold == 1) xil_printf("Send Threshold ");
if (send_mag_squared == 1) xil_printf("Send Mag Squared ");
if (send_cnt_pattern == 1) xil_printf("Send Counting Pattern");
xil_printf("\r\n");
xil_printf("\r\n");
xil_printf("\r\n");
xil_printf("Menu:\r\n");
if (override == 0) xil_printf("[1] Set Override\r\n");
else xil_printf("[1] Clear Override\r\n");
xil_printf("[2] Start Spectrum Sensing (Override)\r\n");
xil_printf("[3] Increment RX Data PLL Phase Offset\r\n");
xil_printf("[4] Decrement RX Data PLL Phase Offset\r\n");
xil_printf("[5] Set USRP Mode\r\n");
xil_printf("[6] Set Network Configuration\r\n");
xil_printf("[7] Set Spectrum Sensing Options (Override)\r\n");
xil_printf("[8] Write All Registers\r\n");
xil_printf("[9] Read All Registers\r\n");
xil_printf("\r\n");
xil_printf("Selection: ");
GetUartBytes(1,&menu_selection);
xil_printf("\r\n");
switch(menu_selection)
{
// Set / Clear override
case '1':
if (override == 0)
{
ctrl_flags += OVERRIDE_BIT;
override = 1;
}
else
{
int main(){
w3_node_init();
// Write some code here that gives a user instructions for controlling your transceiver.
// --- Enable/disable transmitter
// --- Enable/disable receiver
// --- Enable/disable/reset CFO Correction
// --- Enable/disable/reset timing correction
// --- Select output of DAC (to view signals at various stages in your design)
// --- Modify all filter coefficients (both for CFO and timing synchronization) for tuning
//Set up the UART
XUartLite_Initialize(&UartLite, XPAR_UARTLITE_0_DEVICE_ID);
//Set up the Radio - For details about these calls, see http://warp.rice.edu/svn/WARP/PlatformSupport/CustomPeripherals/pcores/radio_controller_v3_00_b/doc/html/api/index.html
// Configure TX enable, RX enable, and Rx HP filter for software control
radio_controller_setCtrlSource(RC_BASEADDR, RC_RFA, (RC_REG0_TXEN_CTRLSRC|RC_REG0_RXEN_CTRLSRC|RC_REG0_RXHP_CTRLSRC), RC_CTRLSRC_REG);
// Configure TX low-pass filter response to have a corner frequency of 18 MHz:
radio_controller_setRadioParam(RC_BASEADDR, RC_RFA, RC_PARAMID_TXLPF_BW, 0x01);
//Enable software Tx Gain control:
radio_controller_setRadioParam(RC_BASEADDR, RC_RFA,RC_PARAMID_TXGAINS_SPI_CTRL_EN, 0x01);
//Enable software Rx Gain control:
radio_controller_setRadioParam(RC_BASEADDR, RC_RFA,RC_PARAMID_RXGAINS_SPI_CTRL_EN, 0x01);
//Initialize the baseband Tx gain to its max value (0 dB)
radio_controller_setRadioParam(RC_BASEADDR, RC_RFA,RC_PARAMID_TXGAIN_BB, 0x00);
//Initialize the RF Tx gain
radio_controller_setRadioParam(RC_BASEADDR, RC_RFA, RC_PARAMID_TXGAIN_RF, TxGain);
// Configure receive HPF cutoff of 30kHz (DC block)
radio_controller_setRadioParam(RC_BASEADDR, RC_RFA, RC_PARAMID_RXHPF_HIGH_CUTOFF_EN, 0x01);
//14MHz Low Pass Filter on RX (our max freq is 10MHz + 2.25MHz)
// 0: 7.5MHz<br>1: 9.5MHz<br>2: 14MHz<br>3: 18MHz
radio_controller_setRadioParam(RC_BASEADDR, RC_RFA, RC_PARAMID_RXLPF_BW, 0x03);
//Initialize the Rx RF Gain (1:0dB, 2:15dB , 3:30dB )
radio_controller_setRadioParam(RC_BASEADDR, RC_RFA,RC_PARAMID_RXGAIN_RF, RxCoarseGain);
//Initialize the Rx baseband Gain
radio_controller_setRadioParam(RC_BASEADDR, RC_RFA, RC_PARAMID_RXGAIN_BB, RxFineGain);
// Enable the receiver by default
// Set center frequency (i.e. choose the WiFi channel)
radio_controller_setCenterFrequency(RC_BASEADDR , RC_RFA, RC_24GHZ, wifiChannel);
//DECLERATION OF VARIABLES
int x = 0; //Variable used for reading UART
Xuint32 dataIn; //Variable used to temporarily store data read from memory using the XIO_In32() function
Xuint32 dataOut; //Variable used to temporarily store data to write to memory using the XIO_Out32() function
XIo_Out32(Delay,43); //Write the desired value for the PA delay
radio_controller_RxEnable(RC_BASEADDR, RC_RFB); //Turn on Receiver RFB
radio_controller_TxEnable(RC_BASEADDR, RC_RFA); //Turn on Transmitter RFA
dataIn = XIo_In32(Delay); //Read in first delay for sanity check
xil_printf("first delay: %d \n \r", dataIn); //Print to terminal for user to look at
XIo_Out32(Controls,0x80000000); //Turn On LTE signal
while(1){
x = XUartLite_RecvByte(STDIN_BASEADDRESS); //Input from UART
////TURN TRAINING ON////
if(x=='t'){
XIo_Out32(Controls,0x04000000); //Turn Off Signal, DPD, learning, and reset
XIo_Out32(Controls,0xF0000000); //Turn On LTE, DPD, and Training
xil_printf("Training Activated \n \r");
}
////COMMANDS TO LOOK AT AND CHANGE DELAY////
if(x=='d'){ //Read current delay
dataIn = XIo_In32(Delay);
xil_printf("Current Delay: %d \n \r", dataIn);
}
if(x=='e'){ //Increase delay
radio_controller_TxRxDisable(RC_BASEADDR, RC_RFA|RC_RFB); //Turn off TX and RX RFB
XIo_Out32(Controls,0x04000000); //Turn Off LTE, DPD, Training, and Reset
dataIn = XIo_In32(Delay); //Read current delay
dataOut = dataIn + 1; //step by 1
XIo_Out32(Delay,dataOut); //Write to delay
dataIn = XIo_In32(Delay); //Read current delay
xil_printf("New Delay: %d \n \r", dataIn);
radio_controller_RxEnable(RC_BASEADDR, RC_RFB); //Turn on Receiver RFB
radio_controller_TxEnable(RC_BASEADDR, RC_RFA); //Turn on Transmitter RFA
XIo_Out32(Controls,0xF0000000); //Turn On LTE, DPD, and Training
}
if(x=='c'){ //Decrease delay
radio_controller_TxRxDisable(RC_BASEADDR, RC_RFA|RC_RFB); //Turn off TX and RX RFB
XIo_Out32(Controls,0x04000000); //Turn Off LTE, DPD, Training, and Reset
dataIn = XIo_In32(Delay); //Read current delay
dataOut = dataIn - 1; //step by 1
XIo_Out32(Delay,dataOut); //Write to delay
dataIn = XIo_In32(Delay); //Read current delay
xil_printf("New Delay: %d \n \r", dataIn);
radio_controller_RxEnable(RC_BASEADDR, RC_RFB); //Turn on Receiver RFB
radio_controller_TxEnable(RC_BASEADDR, RC_RFA); //Turn on Transmitter RFA
XIo_Out32(Controls,0xF0000000); //Turn On LTE, DPD, and Training
}
////REPORT ALL ALPHAS FROM TRAINING////
if(x=='l'){
int i = 0;
for(i = 0;i<Alpha_depth;i=i+4 ){
dataIn = XIo_In32(Alpha_memory+i); //Read alpha
xil_printf("%08x, address: %08x \n \r", dataIn, Alpha_memory+i);
}
}
////COMMANDS FOR CHANGING ALPHA MANUALLY///
if(x=='a'){ //Switch to Manual Alpha
XIo_Out32(Controls,0x04000000); //Turn Off Signal, DPD, learning, and reset
XIo_Out32(Controls,0xC8000000); //Turn On LTE, DPD, and manual alpha
dataIn = XIo_In32(Alpha_user); //Read current user defined alpha
xil_printf("Current Alpha: %08x \n \r", dataIn);
}
if(x=='q'){ //Increase Manual Alpha Real
dataIn = XIo_In32(Alpha_user); //Read current user defined alpha
dataOut = dataIn + 0x01000000; //step by 2^-6 = 0.015625
XIo_Out32(Alpha_user,dataOut); //Write to user defined alpha
dataIn = XIo_In32(Alpha_user); //Read current user defined alpha
xil_printf("New Alpha: %08x \n \r", dataIn);
}
if(x=='z'){ //Decrease Manual Alpha Real
dataIn = XIo_In32(Alpha_user); //Read current user defined alpha
dataOut = dataIn - 0x01000000; //step by -2^-6 = -0.015625
XIo_Out32(Alpha_user,dataOut); //Write to user defined alpha
dataIn = XIo_In32(Alpha_user); //Read current user defined alpha
xil_printf("New Alpha: %08x \n \r", dataIn);
}
if(x=='w'){ //Increase Manual Alpha Imag
dataIn = XIo_In32(Alpha_user); //Read current user defined alpha
dataOut = dataIn + 0x00000100; //step by 2^-6 = 0.015625
XIo_Out32(Alpha_user,dataOut); //Write to user defined alpha
dataIn = XIo_In32(Alpha_user); //Read current user defined alpha
xil_printf("New Alpha: %08x \n \r", dataIn);
}
if(x=='x'){ //Decrease Manual Alpha Imag
dataIn = XIo_In32(Alpha_user); //Read current user defined alpha
dataOut = dataIn - 0x00000100; //step by -2^-6 = -0.015625
XIo_Out32(Alpha_user,dataOut); //Write to user defined alpha
dataIn = XIo_In32(Alpha_user); //Read current user defined alpha
xil_printf("New Alpha: %08x \n \r", dataIn);
}
}
}
/*
*
* Check the interrupt status bits of the Ethernet MAC for errors. Errors
* currently handled are:
* - Receive length FIFO overrun. Indicates data was lost due to the receive
* length FIFO becoming full during the reception of a packet. Only a device
* reset clears this condition.
* - Receive length FIFO underrun. An attempt to read an empty FIFO. Only a
* device reset clears this condition.
* - Transmit status FIFO overrun. Indicates data was lost due to the transmit
* status FIFO becoming full following the transmission of a packet. Only a
* device reset clears this condition.
* - Transmit status FIFO underrun. An attempt to read an empty FIFO. Only a
* device reset clears this condition.
* - Transmit length FIFO overrun. Indicates data was lost due to the transmit
* length FIFO becoming full following the transmission of a packet. Only a
* device reset clears this condition.
* - Transmit length FIFO underrun. An attempt to read an empty FIFO. Only a
* device reset clears this condition.
* - Receive data FIFO overrun. Indicates data was lost due to the receive data
* FIFO becoming full during the reception of a packet.
* - Receive data errors:
* - Receive missed frame error. Valid data was lost by the MAC.
* - Receive collision error. Data was lost by the MAC due to a collision.
* - Receive FCS error. Data was dicarded by the MAC due to FCS error.
* - Receive length field error. Data was dicarded by the MAC due to an invalid
* length field in the packet.
* - Receive short error. Data was dicarded by the MAC because a packet was
* shorter than allowed.
* - Receive long error. Data was dicarded by the MAC because a packet was
* longer than allowed.
* - Receive alignment error. Data was truncated by the MAC because its length
* was not byte-aligned.
*
* @param InstancePtr is a pointer to the XEmac instance to be worked on.
* @param IntrStatus is the contents of the interrupt status register to be checked
*
* @return
*
* None.
*
* @note
*
* This function is intended for internal use only.
*
******************************************************************************/
void XEmac_CheckEmacError(XEmac * InstancePtr, u32 IntrStatus)
{
u32 ResetError = FALSE;
/*
* First check for receive fifo overrun/underrun errors. Most require a
* reset by the user to clear, but the data FIFO overrun error does not.
*/
if (IntrStatus & XEM_EIR_RECV_DFIFO_OVER_MASK) {
InstancePtr->Stats.RecvOverrunErrors++;
InstancePtr->Stats.FifoErrors++;
}
if (IntrStatus & XEM_EIR_RECV_LFIFO_OVER_MASK) {
/*
* Receive Length FIFO overrun interrupts no longer occur in v1.00l
* and later of the EMAC device. Frames are just dropped by the EMAC
* if the length FIFO is full. The user would notice the Receive Missed
* Frame count incrementing without any other errors being reported.
* This code is left here for backward compatibility with v1.00k and
* older EMAC devices.
*/
InstancePtr->Stats.RecvOverrunErrors++;
InstancePtr->Stats.FifoErrors++;
ResetError = TRUE; /* requires a reset */
}
if (IntrStatus & XEM_EIR_RECV_LFIFO_UNDER_MASK) {
InstancePtr->Stats.RecvUnderrunErrors++;
InstancePtr->Stats.FifoErrors++;
ResetError = TRUE; /* requires a reset */
}
/*
* Now check for general receive errors. Get the latest count where
* available, otherwise just bump the statistic so we know the interrupt
* occurred.
*/
if (IntrStatus & XEM_EIR_RECV_ERROR_MASK) {
if (IntrStatus & XEM_EIR_RECV_MISSED_FRAME_MASK) {
/*
* Caused by length FIFO or data FIFO overruns on receive side
*/
InstancePtr->Stats.RecvMissedFrameErrors =
XIo_In32(InstancePtr->BaseAddress +
XEM_RMFC_OFFSET);
}
if (IntrStatus & XEM_EIR_RECV_COLLISION_MASK) {
InstancePtr->Stats.RecvCollisionErrors =
XIo_In32(InstancePtr->BaseAddress + XEM_RCC_OFFSET);
}
if (IntrStatus & XEM_EIR_RECV_FCS_ERROR_MASK) {
InstancePtr->Stats.RecvFcsErrors =
XIo_In32(InstancePtr->BaseAddress +
XEM_RFCSEC_OFFSET);
}
if (IntrStatus & XEM_EIR_RECV_LEN_ERROR_MASK) {
InstancePtr->Stats.RecvLengthFieldErrors++;
}
if (IntrStatus & XEM_EIR_RECV_SHORT_ERROR_MASK) {
InstancePtr->Stats.RecvShortErrors++;
}
if (IntrStatus & XEM_EIR_RECV_LONG_ERROR_MASK) {
InstancePtr->Stats.RecvLongErrors++;
}
if (IntrStatus & XEM_EIR_RECV_ALIGN_ERROR_MASK) {
InstancePtr->Stats.RecvAlignmentErrors =
XIo_In32(InstancePtr->BaseAddress +
XEM_RAEC_OFFSET);
}
/*
* Bump recv interrupts stats only if not scatter-gather DMA (this
* stat gets bumped elsewhere in that case)
*/
if (!XEmac_mIsSgDma(InstancePtr)) {
InstancePtr->Stats.RecvInterrupts++; /* TODO: double bump? */
}
}
/*
* Check for transmit errors. These apply to both DMA and non-DMA modes
* of operation. The entire device should be reset after overruns or
* underruns.
*/
if (IntrStatus & (XEM_EIR_XMIT_SFIFO_OVER_MASK |
XEM_EIR_XMIT_LFIFO_OVER_MASK)) {
InstancePtr->Stats.XmitOverrunErrors++;
InstancePtr->Stats.FifoErrors++;
ResetError = TRUE;
}
if (IntrStatus & (XEM_EIR_XMIT_SFIFO_UNDER_MASK |
XEM_EIR_XMIT_LFIFO_UNDER_MASK)) {
InstancePtr->Stats.XmitUnderrunErrors++;
InstancePtr->Stats.FifoErrors++;
ResetError = TRUE;
}
if (ResetError) {
/*
* If a reset error occurred, disable the EMAC interrupts since the
* reset-causing interrupt(s) is latched in the EMAC - meaning it will
* keep occurring until the device is reset. In order to give the higher
* layer software time to reset the device, we have to disable the
* overrun/underrun interrupts until that happens. We trust that the
* higher layer resets the device. We are able to get away with disabling
* all EMAC interrupts since the only interrupts it generates are for
* error conditions, and we don't care about any more errors right now.
*/
XIIF_V123B_WRITE_IIER(InstancePtr->BaseAddress, 0);
/*
* Invoke the error handler callback, which should result in a reset
* of the device by the upper layer software.
*/
InstancePtr->ErrorHandler(InstancePtr->ErrorRef,
XST_RESET_ERROR);
}
}
/**
*
* This functions receives a single byte using the UART. It is blocking in that
* it waits for the receiver to become non-empty before it reads from the
* receive register.
*
* @param BaseAddress is the base address of the device
*
* @return
*
* The byte of data received.
*
* @note
*
* None.
*
******************************************************************************/
u8 XUartLite_RecvByte(u32 BaseAddress)
{
while (XUartLite_mIsReceiveEmpty(BaseAddress)) ;
return (u8) XIo_In32(BaseAddress + XUL_RX_FIFO_OFFSET);
}
static int labx_audio_meters_ioctl_cdev(struct inode *inode, struct file *filp,
unsigned int command, unsigned long arg)
{
struct labx_audio_meters_pdev *audio_meters_pdev = (struct labx_audio_meters_pdev*)filp->private_data;
switch(command) {
case IOC_AM_SET_COEFFICIENT:
XIo_Out32(AUDIO_METERS_REGISTER(audio_meters_pdev, AUDIO_METERS_COEFFICIENT_REG), (u32)arg);
break;
case IOC_AM_GET_METER_COUNT:
if (copy_to_user((void __user*)arg, &audio_meters_pdev->numChannels, sizeof(u32)) != 0) {
return (-EFAULT);
}
break;
case IOC_AM_READ_METERS:
{
u32 timeout = 1000000;
u32 meterDataCount = 0;
u32 meterDataValue = 0;
/* Copy the number of meter values that the buffer can hold */
if(copy_from_user(&meterDataCount, (void __user*)arg, sizeof(u32)) != 0) {
return(-EFAULT);
}
arg += sizeof(u32);
/* Make sure that no more than the supported channels are being read */
if (meterDataCount > audio_meters_pdev->numChannels) {
return(-EINVAL);
}
/* Switch meter data banks to snapshot the values */
XIo_Out32(AUDIO_METERS_REGISTER(audio_meters_pdev, AUDIO_METERS_VALUE_REG), 0);
/* Wait for meter data to be ready. TODO: use the interrupt instead of this spin-loop */
while ((XIo_In32(AUDIO_METERS_REGISTER(audio_meters_pdev, AUDIO_METERS_STATUS_REG)) & AUDIO_METERS_STATUS_READY) == 0) {
if (timeout-- == 0) {
printk("Meter read timeout\n");
break;
}
}
while(meterDataCount-- > 0) {
meterDataValue = XIo_In32(AUDIO_METERS_REGISTER(audio_meters_pdev, AUDIO_METERS_VALUE_REG));
if(copy_to_user((void __user*)arg, &meterDataValue, sizeof(u32)) != 0) {
return(-EFAULT);
}
arg += sizeof(u32);
}
}
break;
default:
/* We don't recognize this command */
return(-EINVAL);
}
/* Command handled without incident, return success */
return(0);
}