/*
* @brief Common function to abort ongoing transmission.
*
* @param[in] handle UART APP handle pointer of type UART_t*
*
* @return UART_STATUS_t
* UART_SUCCESS: If the transmission is aborted.<BR>
* UART_STATUS_FAILURE: If the channel is not transmitting.<BR>
* UART_STATUS_MODE_MISMATCH: If the configured mode is Direct.<BR>
*
*/
UART_STATUS_t UART_AbortTransmit(const UART_t *const handle)
{
UART_STATUS_t ret_stat = UART_STATUS_SUCCESS;
#ifdef UART_TX_DMA_USED
const UART_DMA_CONFIG_t * ptr_dma_config = handle->config->transmit_dma_config;
XMC_DMA_t * ptr_gpdma = handle->config->global_dma->dma;
#endif
XMC_ASSERT("UART_AbortTransmit: UART APP handle invalid", ((handle != NULL)&&
(handle->runtime != NULL)))
/*Reset the user buffer pointer to null*/
handle->runtime->tx_busy = false;
handle->runtime->tx_data = NULL;
switch(handle->config->transmit_mode)
{
#ifdef UART_TX_INTERRUPT_USED
case UART_TRANSFER_MODE_INTERRUPT:
/*Disable the transmit interrupts*/
if (handle->config->tx_fifo_size != XMC_USIC_CH_FIFO_DISABLED)
{
/*Disable the transmit FIFO event*/
XMC_USIC_CH_TXFIFO_DisableEvent(handle->channel,(uint32_t)XMC_USIC_CH_TXFIFO_EVENT_CONF_STANDARD);
XMC_USIC_CH_TXFIFO_Flush(handle->channel);
}
else
{
/*Disable the standard transmit event*/
XMC_USIC_CH_DisableEvent(handle->channel, (uint32_t)XMC_USIC_CH_EVENT_TRANSMIT_BUFFER);
}
XMC_USIC_CH_SetTransmitBufferStatus(handle->channel, XMC_USIC_CH_TBUF_STATUS_SET_IDLE);
break;
#endif
#ifdef UART_TX_DMA_USED
case UART_TRANSFER_MODE_DMA:
/*Disable the standard transmit event*/
if (XMC_DMA_CH_IsEnabled(ptr_gpdma, ptr_dma_config->dma_channel))
{
XMC_DMA_CH_Disable(ptr_gpdma, ptr_dma_config->dma_channel);
while(XMC_DMA_CH_IsEnabled(ptr_gpdma, ptr_dma_config->dma_channel)==true)
{
}
XMC_USIC_CH_DisableEvent(handle->channel, (uint32_t)XMC_USIC_CH_EVENT_TRANSMIT_BUFFER);
}
XMC_USIC_CH_SetTransmitBufferStatus(handle->channel, XMC_USIC_CH_TBUF_STATUS_SET_IDLE);
break;
#endif
default:
ret_stat = UART_STATUS_MODE_MISMATCH;
break;
}
return ret_stat;
}
/*
* @brief Common function to abort ongoing reception.
*
* @param[in] handle UART APP handle pointer of type UART_t*
*
* @return UART_STATUS_t
* UART_SUCCESS: If the reception is aborted.<BR>
* UART_STATUS_FAILURE : If the channel is not busy.<BR>
* UART_STATUS_MODE_MISMATCH: If the configured mode is Direct.<BR>
*
*/
UART_STATUS_t UART_AbortReceive(const UART_t *const handle)
{
UART_STATUS_t ret_stat = UART_STATUS_SUCCESS;
#ifdef UART_RX_DMA_USED
const UART_DMA_CONFIG_t * ptr_dma_config = handle->config->receive_dma_config;
XMC_DMA_t * ptr_gpdma = handle->config->global_dma->dma;
#endif
XMC_ASSERT("UART_AbortReceive: UART APP handle invalid", ((handle != NULL)&&
(handle->runtime != NULL)))
/*Reset the user buffer pointer to null*/
handle->runtime->rx_busy = false;
handle->runtime->rx_data = NULL;
switch(handle->config->receive_mode)
{
#ifdef UART_RX_INTERRUPT_USED
case UART_TRANSFER_MODE_INTERRUPT:
/*Disable the receive interrupts*/
if (handle->config->rx_fifo_size != XMC_USIC_CH_FIFO_DISABLED)
{
XMC_USIC_CH_RXFIFO_DisableEvent(handle->channel,
((uint32_t)XMC_USIC_CH_RXFIFO_EVENT_CONF_STANDARD |
(uint32_t)XMC_USIC_CH_RXFIFO_EVENT_CONF_ALTERNATE));
}
else
{
XMC_UART_CH_DisableEvent(handle->channel,
((uint32_t)XMC_USIC_CH_EVENT_STANDARD_RECEIVE |
(uint32_t)XMC_USIC_CH_EVENT_ALTERNATIVE_RECEIVE));
}
break;
#endif
#ifdef UART_RX_DMA_USED
case UART_TRANSFER_MODE_DMA:
/*Disable the receive interrupts*/
if (XMC_DMA_CH_IsEnabled(ptr_gpdma, ptr_dma_config->dma_channel))
{
XMC_DMA_CH_Disable(ptr_gpdma, ptr_dma_config->dma_channel);
while(XMC_DMA_CH_IsEnabled(ptr_gpdma, ptr_dma_config->dma_channel)==true)
{
}
XMC_UART_CH_DisableEvent(handle->channel,
((uint32_t)XMC_USIC_CH_EVENT_STANDARD_RECEIVE |
(uint32_t)XMC_USIC_CH_EVENT_ALTERNATIVE_RECEIVE));
}
break;
#endif
default:
ret_stat = UART_STATUS_MODE_MISMATCH;
break;
}
return ret_stat;
}
/* Initialize DMA channel */
XMC_DMA_CH_STATUS_t XMC_DMA_CH_Init(XMC_DMA_t *const dma, const uint8_t channel, const XMC_DMA_CH_CONFIG_t *const config)
{
XMC_DMA_CH_STATUS_t status;
uint8_t line;
uint8_t peripheral;
if (XMC_DMA_IsEnabled(dma) == true)
{
if (XMC_DMA_CH_IsEnabled(dma, channel) == false)
{
dma->CH[channel].SAR = config->src_addr;
dma->CH[channel].DAR = config->dst_addr;
dma->CH[channel].LLP = (uint32_t)config->linked_list_pointer;
dma->CH[channel].CTLH = (uint32_t)config->block_size;
dma->CH[channel].CTLL = config->control;
dma->CH[channel].CFGL = (uint32_t)((uint32_t)config->priority |
(uint32_t)GPDMA0_CH_CFGL_HS_SEL_SRC_Msk |
(uint32_t)GPDMA0_CH_CFGL_HS_SEL_DST_Msk);
if ((dma == XMC_DMA0) && (channel < (uint8_t)2))
{
/* Configure scatter and gather */
dma->CH[channel].SGR = config->src_gather_control;
dma->CH[channel].DSR = config->dst_scatter_control;
}
if (config->dst_handshaking == XMC_DMA_CH_DST_HANDSHAKING_HARDWARE)
{
/* Hardware handshaking interface configuration */
if ((config->transfer_flow == (uint32_t)XMC_DMA_CH_TRANSFER_FLOW_M2P_DMA) ||
(config->transfer_flow == (uint32_t)XMC_DMA_CH_TRANSFER_FLOW_P2P_DMA))
{
#if defined(GPDMA1)
if (dma == XMC_DMA0)
{
#endif
line = config->dst_peripheral_request & GPDMA0_CH_CFGH_PER_Msk;
#if defined(GPDMA1)
}
else
{
line = config->dst_peripheral_request & GPDMA1_CH_CFGH_PER_Msk;
}
#endif
peripheral = config->dst_peripheral_request >> GPDMA_CH_CFGH_PER_BITSIZE;
dma->CH[channel].CFGH |= (uint32_t)((uint32_t)line << GPDMA0_CH_CFGH_DEST_PER_Pos);
XMC_DMA_EnableRequestLine(dma, line, peripheral);
dma->CH[channel].CFGL &= (uint32_t)~GPDMA0_CH_CFGL_HS_SEL_DST_Msk;
}
}
if (config->src_handshaking == XMC_DMA_CH_SRC_HANDSHAKING_HARDWARE)
{
if ((config->transfer_flow == (uint32_t)XMC_DMA_CH_TRANSFER_FLOW_P2M_DMA) ||
(config->transfer_flow == (uint32_t)XMC_DMA_CH_TRANSFER_FLOW_P2P_DMA))
{
#if defined(GPDMA1)
if (dma == XMC_DMA0)
{
#endif
line = config->src_peripheral_request & GPDMA0_CH_CFGH_PER_Msk;
#if defined(GPDMA1)
}
else
{
line = config->src_peripheral_request & GPDMA1_CH_CFGH_PER_Msk;
}
#endif
peripheral = config->src_peripheral_request >> GPDMA_CH_CFGH_PER_BITSIZE;
dma->CH[channel].CFGH |= (uint32_t)((uint32_t)line << GPDMA0_CH_CFGH_SRC_PER_Pos);
XMC_DMA_EnableRequestLine(dma, line, peripheral);
dma->CH[channel].CFGL &= (uint32_t)~GPDMA0_CH_CFGL_HS_SEL_SRC_Msk;
}
}
XMC_DMA_CH_ClearEventStatus(dma, channel, (uint32_t)((uint32_t)XMC_DMA_CH_EVENT_TRANSFER_COMPLETE |
(uint32_t)XMC_DMA_CH_EVENT_BLOCK_TRANSFER_COMPLETE |
(uint32_t)XMC_DMA_CH_EVENT_SRC_TRANSACTION_COMPLETE |
(uint32_t)XMC_DMA_CH_EVENT_DST_TRANSACTION_COMPLETE |
(uint32_t)XMC_DMA_CH_EVENT_ERROR));
switch (config->transfer_type)
{
case XMC_DMA_CH_TRANSFER_TYPE_SINGLE_BLOCK:
break;
case XMC_DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_CONTIGUOUS_DSTADR_RELOAD:
dma->CH[channel].CFGL |= (uint32_t)GPDMA0_CH_CFGL_RELOAD_DST_Msk;
break;
case XMC_DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_RELOAD_DSTADR_CONTIGUOUS:
dma->CH[channel].CFGL |= (uint32_t)GPDMA0_CH_CFGL_RELOAD_SRC_Msk;
break;
case XMC_DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_RELOAD_DSTADR_RELOAD:
dma->CH[channel].CFGL |= (uint32_t)((uint32_t)GPDMA0_CH_CFGL_RELOAD_DST_Msk |
(uint32_t)GPDMA0_CH_CFGL_RELOAD_SRC_Msk);
break;
case XMC_DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_CONTIGUOUS_DSTADR_LINKED:
dma->CH[channel].CTLL |= (uint32_t)GPDMA0_CH_CTLL_LLP_DST_EN_Msk;
break;
case XMC_DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_RELOAD_DSTADR_LINKED:
dma->CH[channel].CFGL |= (uint32_t)GPDMA0_CH_CFGL_RELOAD_SRC_Msk;
dma->CH[channel].CTLL |= (uint32_t)GPDMA0_CH_CTLL_LLP_DST_EN_Msk;
break;
case XMC_DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_LINKED_DSTADR_CONTIGUOUS:
dma->CH[channel].CTLL |= (uint32_t)GPDMA0_CH_CTLL_LLP_SRC_EN_Msk;
break;
case XMC_DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_LINKED_DSTADR_RELOAD:
dma->CH[channel].CFGL |= (uint32_t)GPDMA0_CH_CFGL_RELOAD_DST_Msk;
dma->CH[channel].CTLL |= (uint32_t)GPDMA0_CH_CTLL_LLP_SRC_EN_Msk;
break;
case XMC_DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_LINKED_DSTADR_LINKED:
dma->CH[channel].CTLL |= (uint32_t)((uint32_t)GPDMA0_CH_CTLL_LLP_SRC_EN_Msk |
(uint32_t)GPDMA0_CH_CTLL_LLP_DST_EN_Msk);
break;
default:
break;
}
status = XMC_DMA_CH_STATUS_OK;
}
else
{
