/*
* This function enables interrupts and connects interrupt service routines declared in
* an interrupt vector table
*/
void fnEnableInterrupts(intc *psIntc, const ivt_t *prgsIvt, unsigned int csIVectors)
{
unsigned int isIVector;
Xil_AssertVoid(psIntc != NULL);
Xil_AssertVoid(psIntc->IsReady == XIL_COMPONENT_IS_READY);
/* Hook up interrupt service routines from IVT */
for (isIVector = 0; isIVector < csIVectors; isIVector++)
{
#ifdef __MICROBLAZE__
XIntc_Connect(psIntc, prgsIvt[isIVector].id, prgsIvt[isIVector].handler, prgsIvt[isIVector].pvCallbackRef);
/* Enable the interrupt vector at the interrupt controller */
XIntc_Enable(psIntc, prgsIvt[isIVector].id);
#else
XScuGic_SetPriorityTriggerType(psIntc, prgsIvt[isIVector].id, 0xA0, 0x3);
XScuGic_Connect(psIntc, prgsIvt[isIVector].id, prgsIvt[isIVector].handler, prgsIvt[isIVector].pvCallbackRef);
XScuGic_Enable(psIntc, prgsIvt[isIVector].id);
#endif
}
Xil_ExceptionInit();
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT, (Xil_ExceptionHandler)INTC_HANDLER, psIntc);
Xil_ExceptionEnable();
}
static void init_interrupt()
{
Xil_ExceptionInit();
if ((icconf = XScuGic_LookupConfig(XPAR_PS7_SCUGIC_0_DEVICE_ID))
== NULL)
return;
if (XScuGic_CfgInitialize(&ic, icconf, icconf->CpuBaseAddress) !=
XST_SUCCESS)
return;
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT,
(Xil_ExceptionHandler) XScuGic_InterruptHandler, &ic);
if (XScuGic_Connect(&ic, PL_INT_ID, interrupt_handler,
NULL) != XST_SUCCESS)
return;
XScuGic_SetPriorityTriggerType(&ic, PL_INT_ID, 0, /*highest priority*/
3); /* 3 - rising edge, 1 - active high */
XScuGic_Enable(&ic, PL_INT_ID);
Xil_ExceptionEnable();
}
static int SetupIntrSystem(XScuGic * IntcInstancePtr, XAxiDma * AxiDmaPtr, u16 TxIntrId)
{
int Status;
XScuGic_Config *IntcConfig;
/*
* Initialize the interrupt controller driver so that it is ready to
* use.
*/
IntcConfig = XScuGic_LookupConfig(XPAR_SCUGIC_SINGLE_DEVICE_ID);
if (NULL == IntcConfig) {
return XST_FAILURE;
}
Status = XScuGic_CfgInitialize(IntcInstancePtr, IntcConfig,IntcConfig->CpuBaseAddress);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
XScuGic_SetPriorityTriggerType(IntcInstancePtr, TxIntrId, 0xA0, 0x3);
/*
* Connect the device driver handler that will be called when an
* interrupt for the device occurs, the handler defined above performs
* the specific interrupt processing for the device.
*/
Status = XScuGic_Connect(IntcInstancePtr, TxIntrId,(Xil_InterruptHandler)TxIntrHandler,AxiDmaPtr);
if (Status != XST_SUCCESS) {
return Status;
}
XScuGic_Enable(IntcInstancePtr, TxIntrId);
/* Enable interrupts from the hardware */
Xil_ExceptionInit();
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,(Xil_ExceptionHandler)XScuGic_InterruptHandler,(void *)IntcInstancePtr);
Xil_ExceptionEnable();
return XST_SUCCESS;
}
void vInitialiseTimerForIntQueueTest( void )
{
BaseType_t xStatus;
TmrCntrSetup *pxTimerSettings;
extern XScuGic xInterruptController;
BaseType_t xTimer;
XTtcPs *pxTimerInstance;
XTtcPs_Config *pxTimerConfiguration;
const uint8_t ucRisingEdge = 3;
for( xTimer = 0; xTimer < tmrTIMERS_USED; xTimer++ )
{
/* Look up the timer's configuration. */
pxTimerInstance = &( xTimerInstances[ xTimer ] );
pxTimerConfiguration = XTtcPs_LookupConfig( xDeviceIDs[ xTimer ] );
configASSERT( pxTimerConfiguration );
pxTimerSettings = &( xTimerSettings[ xTimer ] );
/* Initialise the device. */
xStatus = XTtcPs_CfgInitialize( pxTimerInstance, pxTimerConfiguration, pxTimerConfiguration->BaseAddress );
if( xStatus != XST_SUCCESS )
{
/* Not sure how to do this before XTtcPs_CfgInitialize is called
as pxTimerInstance is set within XTtcPs_CfgInitialize(). */
XTtcPs_Stop( pxTimerInstance );
xStatus = XTtcPs_CfgInitialize( pxTimerInstance, pxTimerConfiguration, pxTimerConfiguration->BaseAddress );
configASSERT( xStatus == XST_SUCCESS );
}
/* Set the options. */
XTtcPs_SetOptions( pxTimerInstance, pxTimerSettings->Options );
/* The timer frequency is preset in the pxTimerSettings structure.
Derive the values for the other structure members. */
XTtcPs_CalcIntervalFromFreq( pxTimerInstance, pxTimerSettings->OutputHz, &( pxTimerSettings->Interval ), &( pxTimerSettings->Prescaler ) );
/* Set the interval and prescale. */
XTtcPs_SetInterval( pxTimerInstance, pxTimerSettings->Interval );
XTtcPs_SetPrescaler( pxTimerInstance, pxTimerSettings->Prescaler );
/* The priority must be the lowest possible. */
XScuGic_SetPriorityTriggerType( &xInterruptController, xInterruptIDs[ xTimer ], uxInterruptPriorities[ xTimer ] << portPRIORITY_SHIFT, ucRisingEdge );
/* Connect to the interrupt controller. */
xStatus = XScuGic_Connect( &xInterruptController, xInterruptIDs[ xTimer ], ( Xil_InterruptHandler ) prvTimerHandler, ( void * ) pxTimerInstance );
configASSERT( xStatus == XST_SUCCESS);
/* Enable the interrupt in the GIC. */
XScuGic_Enable( &xInterruptController, xInterruptIDs[ xTimer ] );
/* Enable the interrupts in the timer. */
XTtcPs_EnableInterrupts( pxTimerInstance, XTTCPS_IXR_INTERVAL_MASK );
/* Start the timer. */
XTtcPs_Start( pxTimerInstance );
}
}
/**
* This function setups the interrupt system so interrupts can occur for the
* IIC device. The function is application-specific since the actual system may
* or may not have an interrupt controller. The IIC device could be directly
* connected to a processor without an interrupt controller. The user should
* modify this function to fit the application.
*
* @param IicInstPtr contains a pointer to the instance of the IIC device
* which is going to be connected to the interrupt controller.
*
* @return XST_SUCCESS if successful else XST_FAILURE.
*
* @note None.
*
******************************************************************************/
static int SetupInterruptSystem(XIIC_LIB *I2cLibPtr)
{
int Status;
XIIC *I2cInstancePtr;
INTC *IntcPtr;
I2cInstancePtr = &I2cLibPtr->I2cInstance;
IntcPtr = &I2cLibPtr->IntcInstance;
XScuGic_Config *IntcConfig;
/*
* Initialize the interrupt controller driver so that it is ready to
* use.
*/
IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID);
if (NULL == IntcConfig) {
return XST_FAILURE;
}
Status = XScuGic_CfgInitialize(IntcPtr, IntcConfig,
IntcConfig->CpuBaseAddress);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
XScuGic_SetPriorityTriggerType(IntcPtr, IIC_INTR_ID, 0xA0, 0x3);
/*
* Connect the interrupt handler that will be called when an
* interrupt occurs for the device.
*/
Status = XScuGic_Connect(IntcPtr, IIC_INTR_ID,
(Xil_InterruptHandler) XIicPs_MasterInterruptHandler,
I2cInstancePtr);
if (Status != XST_SUCCESS) {
return Status;
}
/*
* Enable the interrupt for the IIC device.
*/
XScuGic_Enable(IntcPtr, IIC_INTR_ID);
/*
* Initialize the exception table and register the interrupt
* controller handler with the exception table
*/
Xil_ExceptionInit();
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
(Xil_ExceptionHandler) INTC_HANDLER, IntcPtr);
/* Enable non-critical exceptions */Xil_ExceptionEnable();
return XST_SUCCESS;
}
/*
* The application must provide a function that configures a peripheral to
* create the FreeRTOS tick interrupt, then define configSETUP_TICK_INTERRUPT()
* in FreeRTOSConfig.h to call the function. This file contains a function
* that is suitable for use on the Zynq SoC.
*/
void vConfigureTickInterrupt( void )
{
static XScuGic xInterruptController; /* Interrupt controller instance */
BaseType_t xStatus;
extern void FreeRTOS_Tick_Handler( void );
XScuTimer_Config *pxTimerConfig;
XScuGic_Config *pxGICConfig;
const uint8_t ucRisingEdge = 3;
/* This function is called with the IRQ interrupt disabled, and the IRQ
interrupt should be left disabled. It is enabled automatically when the
scheduler is started. */
/* Ensure XScuGic_CfgInitialize() has been called. In this demo it has
already been called from prvSetupHardware() in main(). */
pxGICConfig = XScuGic_LookupConfig( XPAR_SCUGIC_SINGLE_DEVICE_ID );
xStatus = XScuGic_CfgInitialize( &xInterruptController, pxGICConfig, pxGICConfig->CpuBaseAddress );
configASSERT( xStatus == XST_SUCCESS );
( void ) xStatus; /* Remove compiler warning if configASSERT() is not defined. */
/* The priority must be the lowest possible. */
XScuGic_SetPriorityTriggerType( &xInterruptController, XPAR_SCUTIMER_INTR, portLOWEST_USABLE_INTERRUPT_PRIORITY << portPRIORITY_SHIFT, ucRisingEdge );
/* Install the FreeRTOS tick handler. */
xStatus = XScuGic_Connect( &xInterruptController, XPAR_SCUTIMER_INTR, (Xil_ExceptionHandler) FreeRTOS_Tick_Handler, ( void * ) &xTimer );
configASSERT( xStatus == XST_SUCCESS );
( void ) xStatus; /* Remove compiler warning if configASSERT() is not defined. */
/* Initialise the timer. */
pxTimerConfig = XScuTimer_LookupConfig( XPAR_SCUTIMER_DEVICE_ID );
xStatus = XScuTimer_CfgInitialize( &xTimer, pxTimerConfig, pxTimerConfig->BaseAddr );
configASSERT( xStatus == XST_SUCCESS );
( void ) xStatus; /* Remove compiler warning if configASSERT() is not defined. */
/* Enable Auto reload mode. */
XScuTimer_EnableAutoReload( &xTimer );
/* Ensure there is no prescale. */
XScuTimer_SetPrescaler( &xTimer, 0 );
/* Load the timer counter register. */
XScuTimer_LoadTimer( &xTimer, XSCUTIMER_CLOCK_HZ / configTICK_RATE_HZ );
/* Start the timer counter and then wait for it to timeout a number of
times. */
XScuTimer_Start( &xTimer );
/* Enable the interrupt for the xTimer in the interrupt controller. */
XScuGic_Enable( &xInterruptController, XPAR_SCUTIMER_INTR );
/* Enable the interrupt in the xTimer itself. */
vClearTickInterrupt();
XScuTimer_EnableInterrupt( &xTimer );
}
/*
* The application must provide a function that configures a peripheral to
* create the FreeRTOS tick interrupt, then define configSETUP_TICK_INTERRUPT()
* in FreeRTOSConfig.h to call the function. This file contains a function
* that is suitable for use on the Zynq SoC.
*/
void vConfigureTickInterrupt( void )
{
XTtcPs_Config *pxTimerConfig;
BaseType_t xStatus;
XScuGic_Config *pxGICConfig;
static XScuGic xInterruptController; /* Interrupt controller instance */
uint16_t usInterval;
uint8_t ucPrescale = 0;
const uint8_t ucRisingEdge = 3;
/* This function is called with the IRQ interrupt disabled, and the IRQ
interrupt should be left disabled. It is enabled automatically when the
scheduler is started. */
/* Ensure XScuGic_CfgInitialize() has been called. In this demo it has
already been called from prvSetupHardware() in main(). */
pxGICConfig = XScuGic_LookupConfig( XPAR_SCUGIC_SINGLE_DEVICE_ID );
xStatus = XScuGic_CfgInitialize( &xInterruptController, pxGICConfig, pxGICConfig->CpuBaseAddress );
configASSERT( xStatus == XST_SUCCESS );
( void ) xStatus; /* Remove compiler warning if configASSERT() is not defined. */
/* The interrupt priority must be the lowest possible. */
XScuGic_SetPriorityTriggerType( &xInterruptController, tickINTERRUPT_ID, portLOWEST_USABLE_INTERRUPT_PRIORITY << portPRIORITY_SHIFT, ucRisingEdge );
/* Install the FreeRTOS tick handler. */
xStatus = XScuGic_Connect( &xInterruptController, tickINTERRUPT_ID, (Xil_ExceptionHandler) FreeRTOS_Tick_Handler, NULL );
configASSERT( xStatus == XST_SUCCESS );
( void ) xStatus; /* Remove compiler warning if configASSERT() is not defined. */
/* Initialise the Triple Timer Counter (TTC) that is going to be used to
generate the tick interrupt. */
pxTimerConfig = XTtcPs_LookupConfig( tickTTC_ID );
xStatus = XTtcPs_CfgInitialize( &xTimerInstance, pxTimerConfig, pxTimerConfig->BaseAddress );
configASSERT( xStatus == XST_SUCCESS );
( void ) xStatus; /* Remove compiler warning if configASSERT() is not defined. */
/* Configure the interval to be the require tick rate. */
XTtcPs_CalcIntervalFromFreq( &xTimerInstance, configTICK_RATE_HZ, &usInterval, &ucPrescale );
XTtcPs_SetInterval( &xTimerInstance, usInterval );
XTtcPs_SetPrescaler( &xTimerInstance, ucPrescale );
/* Interval mode used. */
XTtcPs_SetOptions( &xTimerInstance, XTTCPS_OPTION_INTERVAL_MODE | XTTCPS_OPTION_WAVE_DISABLE );
/* Start the timer. */
XTtcPs_Start( &xTimerInstance );
/* Enable the interrupt in the interrupt controller. */
XScuGic_Enable( &xInterruptController, tickINTERRUPT_ID );
/* Enable the interrupt in the timer itself. */
XTtcPs_EnableInterrupts( &xTimerInstance, XTTCPS_IXR_INTERVAL_MASK );
}
/**
* This function sets up the interrupt system for the example. The processing
* contained in this function assumes the hardware system was built with
* and interrupt controller.
*
* @param None.
*
* @return A status indicating XST_SUCCESS or a value that is contained in
* xstatus.h.
*
* @note None.
*
*****************************************************************************/
int zed_ali3_controller_demo_SetupInterruptSystem(zed_ali3_controller_demo_t *pDemo)
{
int Result;
/*
* Initialize the interrupt controller driver so that it is ready to
* use.
*/
pDemo->pIntcConfig = XScuGic_LookupConfig(pDemo->uDeviceId_IRQ_Touch);
if (NULL == pDemo->pIntcConfig) {
return XST_FAILURE;
}
Result = XScuGic_CfgInitialize(&(pDemo->Intc), pDemo->pIntcConfig,
pDemo->pIntcConfig->CpuBaseAddress);
if (Result != XST_SUCCESS) {
return XST_FAILURE;
}
XScuGic_SetPriorityTriggerType(&(pDemo->Intc), pDemo->uInterruptId_IRQ_Touch,
0xA0, 0x3);
/*
* Connect the interrupt handler that will be called when an
* interrupt occurs for the device.
*/
Result = XScuGic_Connect(&(pDemo->Intc), pDemo->uInterruptId_IRQ_Touch,
(Xil_ExceptionHandler)TouchIsr, pDemo);
if (Result != XST_SUCCESS) {
return Result;
}
/*
* Enable the PS interrupts for the touch controller hardware device.
*/
XScuGic_Enable(&(pDemo->Intc), pDemo->uInterruptId_IRQ_Touch);
/*
* Initialize the exception table and register the interrupt
* controller handler with the exception table
*/
Xil_ExceptionInit();
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
(Xil_ExceptionHandler)XScuGic_InterruptHandler, &(pDemo->Intc));
/* Enable non-critical exceptions */
Xil_ExceptionEnable();
return XST_SUCCESS;
}
void vConfigureTickInterrupt( void )
{
BaseType_t xStatus;
XTtcPs_Config *pxTimerConfiguration;
uint16_t usInterval;
uint8_t ucPrescale;
const uint8_t ucLevelSensitive = 1;
extern XScuGic xInterruptController;
pxTimerConfiguration = XTtcPs_LookupConfig( XPAR_XTTCPS_3_DEVICE_ID );
/* Initialise the device. */
xStatus = XTtcPs_CfgInitialize( &xRTOSTickTimerInstance, pxTimerConfiguration, pxTimerConfiguration->BaseAddress );
if( xStatus != XST_SUCCESS )
{
/* Not sure how to do this before XTtcPs_CfgInitialize is called as
*xRTOSTickTimerInstance is set within XTtcPs_CfgInitialize(). */
XTtcPs_Stop( &xRTOSTickTimerInstance );
xStatus = XTtcPs_CfgInitialize( &xRTOSTickTimerInstance, pxTimerConfiguration, pxTimerConfiguration->BaseAddress );
configASSERT( xStatus == XST_SUCCESS );
}
/* Set the options. */
XTtcPs_SetOptions( &xRTOSTickTimerInstance, ( XTTCPS_OPTION_INTERVAL_MODE | XTTCPS_OPTION_WAVE_DISABLE ) );
/* Derive values from the tick rate. */
XTtcPs_CalcIntervalFromFreq( &xRTOSTickTimerInstance, configTICK_RATE_HZ, &( usInterval ), &( ucPrescale ) );
/* Set the interval and prescale. */
XTtcPs_SetInterval( &xRTOSTickTimerInstance, usInterval );
XTtcPs_SetPrescaler( &xRTOSTickTimerInstance, ucPrescale );
/* The priority must be the lowest possible. */
XScuGic_SetPriorityTriggerType( &xInterruptController, XPAR_XTTCPS_3_INTR, portLOWEST_USABLE_INTERRUPT_PRIORITY << portPRIORITY_SHIFT, ucLevelSensitive );
/* Connect to the interrupt controller. */
xStatus = XScuGic_Connect( &xInterruptController, XPAR_XTTCPS_3_INTR, (Xil_ExceptionHandler) FreeRTOS_Tick_Handler, ( void * ) &xRTOSTickTimerInstance );
configASSERT( xStatus == XST_SUCCESS);
/* Enable the interrupt in the GIC. */
XScuGic_Enable( &xInterruptController, XPAR_XTTCPS_3_INTR );
/* Enable the interrupts in the timer. */
XTtcPs_EnableInterrupts( &xRTOSTickTimerInstance, XTTCPS_IXR_INTERVAL_MASK );
/* Start the timer. */
XTtcPs_Start( &xRTOSTickTimerInstance );
}
/* Init FIFO interrupt */
int audioRxTx_start(audioRxTx_t *pThis)
{
/* initialize interrupt handler */
XScuGic *pGic; // pointer to GIC interrupt driver
pGic = prvGetInterruptControllerInstance(); // retrieve pointer to initialized instance
// connect FIFO interrupt handler
XScuGic_Connect(pGic, XPS_FPGA15_INT_ID, (Xil_ExceptionHandler) audioRxTx_isr, (void*) pThis);
// enable IRQ interrupt at GIC
XScuGic_Enable(pGic, XPS_FPGA15_INT_ID);
// define priority and trigger type for AXI Stream FIFO IRQ
XScuGic_SetPriorityTriggerType(pGic, XPS_FPGA15_INT_ID, 0xA0, 0x3);
/* Enable IRQ in processor core */
Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ);
return 1;
}
/**
* This function sets up the interrupt system for the example. The processing
* contained in this funtion assumes the hardware system was built with
* and interrupt controller.
*
* @param None.
*
* @return A status indicating XST_SUCCESS or a value that is contained in
* xstatus.h.
*
* @note None.
*
*****************************************************************************/
int SetupInterruptSystem()
{
int Result;
INTC *IntcInstancePtr = &Intc;
#ifdef XPAR_INTC_0_DEVICE_ID
/*
* Initialize the interrupt controller driver so that it's ready to use.
* specify the device ID that was generated in xparameters.h
*/
Result = XIntc_Initialize(IntcInstancePtr, INTC_DEVICE_ID);
if (Result != XST_SUCCESS) {
return Result;
}
/* Hook up interrupt service routine */
XIntc_Connect(IntcInstancePtr, INTC_GPIO_INTERRUPT_ID,
(Xil_ExceptionHandler)GpioIsr, &Gpio);
/* Enable the interrupt vector at the interrupt controller */
XIntc_Enable(IntcInstancePtr, INTC_GPIO_INTERRUPT_ID);
/*
* Start the interrupt controller such that interrupts are recognized
* and handled by the processor
*/
Result = XIntc_Start(IntcInstancePtr, XIN_REAL_MODE);
if (Result != XST_SUCCESS) {
return Result;
}
#else
XScuGic_Config *IntcConfig;
/*
* Initialize the interrupt controller driver so that it is ready to
* use.
*/
IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID);
if (NULL == IntcConfig) {
return XST_FAILURE;
}
Result = XScuGic_CfgInitialize(IntcInstancePtr, IntcConfig,
IntcConfig->CpuBaseAddress);
if (Result != XST_SUCCESS) {
return XST_FAILURE;
}
XScuGic_SetPriorityTriggerType(IntcInstancePtr, INTC_GPIO_INTERRUPT_ID,
0xA0, 0x3);
/*
* Connect the interrupt handler that will be called when an
* interrupt occurs for the device.
*/
Result = XScuGic_Connect(IntcInstancePtr, INTC_GPIO_INTERRUPT_ID,
(Xil_ExceptionHandler)GpioIsr, &Gpio);
if (Result != XST_SUCCESS) {
return Result;
}
/*
* Enable the interrupt for the GPIO device.
*/
XScuGic_Enable(IntcInstancePtr, INTC_GPIO_INTERRUPT_ID);
#endif
/*
* Enable the GPIO channel interrupts so that push button can be
* detected and enable interrupts for the GPIO device
*/
XGpio_InterruptEnable(&Gpio, BUTTON_INTERRUPT);
XGpio_InterruptGlobalEnable(&Gpio);
/*
* Initialize the exception table and register the interrupt
* controller handler with the exception table
*/
Xil_ExceptionInit();
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
(Xil_ExceptionHandler)INTC_HANDLER, IntcInstancePtr);
/* Enable non-critical exceptions */
Xil_ExceptionEnable();
return XST_SUCCESS;
}
int ScuGicInterrupt_Init() {
int Status;
/*
* Initialize the interrupt controller driver so that it is ready to
* use.
* */
Xil_ExceptionInit();
GicConfig = XScuGic_LookupConfig(XPAR_PS7_SCUGIC_0_DEVICE_ID);
if (NULL == GicConfig) {
return XST_FAILURE;
}
Status = XScuGic_CfgInitialize(&InterruptController, GicConfig,
GicConfig->CpuBaseAddress);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
// **** Setup the Interrupt System *****
// * Connect the interrupt controller interrupt handler to the hardware
// * interrupt handling logic in the ARM processor.
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT,
(Xil_ExceptionHandler) XScuGic_InterruptHandler,
(void *) &InterruptController);
// * Connect a device driver handler that will be called when an
// * interrupt for the device occurs, the device driver handler performs
// * the specific interrupt processing for the device
Status = XScuGic_Connect(&InterruptController,
XPAR_FABRIC_CAM_INTERFACE_0_VSYNC_NEGEDGE_INTR,
(Xil_ExceptionHandler) AXI_INTERRUPT_VsyncIntr_Handler,
(void *) &InterruptController);
XScuGic_Enable(&InterruptController,
XPAR_FABRIC_CAM_INTERFACE_0_VSYNC_NEGEDGE_INTR);
// Enable interrupts in the ARM
Xil_ExceptionEnable();
//Only used for edge sensitive Interrupts
XScuGic_SetPriorityTriggerType(&InterruptController,
XPAR_FABRIC_CAM_INTERFACE_0_VSYNC_NEGEDGE_INTR, 0xa0, 3);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
// CE_TOP_Interrupt
Status = XScuGic_Connect(&InterruptController,
XPAR_FABRIC_CE_TOP_0_INTERRUPT_INTR,
(Xil_InterruptHandler) AXI_INTERRUPT_CEIntr_Handler,
(void *) &hlsCE);
if (Status != XST_SUCCESS) {
return Status;
}
XScuGic_Enable(&InterruptController, XPAR_FABRIC_CE_TOP_0_INTERRUPT_INTR);
XScuGic_SetPriorityTriggerType(&InterruptController,
XPAR_FABRIC_CE_TOP_0_INTERRUPT_INTR, 0x90, 3);
// ME_TOP_Interrupt
Status = XScuGic_Connect(&InterruptController,
XPAR_FABRIC_MATCHINGENGINE32_TOP_0_INTERRUPT_INTR,
(Xil_InterruptHandler) AXI_INTERRUPT_MEIntr_Handler,
(void *) &hlsME);
if (Status != XST_SUCCESS) {
return Status;
}
XScuGic_Enable(&InterruptController,
XPAR_FABRIC_MATCHINGENGINE32_TOP_0_INTERRUPT_INTR);
XScuGic_SetPriorityTriggerType(&InterruptController,
XPAR_FABRIC_MATCHINGENGINE32_TOP_0_INTERRUPT_INTR, 0x70, 3);
// EEE_TOP_Interrupt
Status = XScuGic_Connect(&InterruptController,
XPAR_FABRIC_EEE_TOP_0_INTERRUPT_INTR,
(Xil_InterruptHandler) AXI_INTERRUPT_EEEIntr_Handler,
(void *) &hlsEEE);
if (Status != XST_SUCCESS) {
return Status;
}
XScuGic_Enable(&InterruptController, XPAR_FABRIC_EEE_TOP_0_INTERRUPT_INTR);
XScuGic_SetPriorityTriggerType(&InterruptController,
XPAR_FABRIC_EEE_TOP_0_INTERRUPT_INTR, 0x60, 3);
// ECE_TOP_Interrupt
Status = XScuGic_Connect(&InterruptController,
XPAR_FABRIC_ECE_TOP_0_INTERRUPT_INTR,
(Xil_InterruptHandler) AXI_INTERRUPT_ECEIntr_Handler,
(void *) &hlsECE);
if (Status != XST_SUCCESS) {
return Status;
}
XScuGic_Enable(&InterruptController, XPAR_FABRIC_ECE_TOP_0_INTERRUPT_INTR);
XScuGic_SetPriorityTriggerType(&InterruptController,
XPAR_FABRIC_ECE_TOP_0_INTERRUPT_INTR, 0x50, 3);
return XST_SUCCESS;
}
/**
* This function setups the interrupt system such that interrupts can occur
* for the timer counter. This function is application specific since the actual
* system may or may not have an interrupt controller. The timer counter could
* be directly connected to a processor without an interrupt controller. The
* user should modify this function to fit the application.
*
* @param IntcInstancePtr is a pointer to the Interrupt Controller
* driver Instance.
* @param TmrCtrInstancePtr is a pointer to the XTmrCtr driver Instance.
* @param DeviceId is the XPAR_<TmrCtr_instance>_DEVICE_ID value from
* xparameters.h.
* @param IntrId is XPAR_<INTC_instance>_<TmrCtr_instance>_VEC_ID
* value from xparameters.h.
* @param TmrCtrNumber is the number of the timer to which this
* handler is associated with.
*
* @return XST_SUCCESS if the Test is successful, otherwise XST_FAILURE.
*
* @note This function contains an infinite loop such that if interrupts
* are not working it may never return.
*
******************************************************************************/
static int TmrCtrSetupIntrSystem(INTC* IntcInstancePtr,
XTmrCtr* TmrCtrInstancePtr,
u16 DeviceId,
u16 IntrId,
u8 TmrCtrNumber)
{
int Status;
#ifdef XPAR_INTC_0_DEVICE_ID
#ifndef TESTAPP_GEN
/*
* Initialize the interrupt controller driver so that
* it's ready to use, specify the device ID that is generated in
* xparameters.h
*/
Status = XIntc_Initialize(IntcInstancePtr, INTC_DEVICE_ID);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
#endif
/*
* Connect a device driver handler that will be called when an interrupt
* for the device occurs, the device driver handler performs the specific
* interrupt processing for the device
*/
Status = XIntc_Connect(IntcInstancePtr, IntrId,
(XInterruptHandler)XTmrCtr_InterruptHandler,
(void *)TmrCtrInstancePtr);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
#ifndef TESTAPP_GEN
/*
* Start the interrupt controller such that interrupts are enabled for
* all devices that cause interrupts, specific real mode so that
* the timer counter can cause interrupts thru the interrupt controller.
*/
Status = XIntc_Start(IntcInstancePtr, XIN_REAL_MODE);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
#endif
/*
* Enable the interrupt for the timer counter
*/
XIntc_Enable(IntcInstancePtr, IntrId);
#else
#ifndef TESTAPP_GEN
XScuGic_Config *IntcConfig;
/*
* Initialize the interrupt controller driver so that it is ready to
* use.
*/
IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID);
if (NULL == IntcConfig) {
return XST_FAILURE;
}
Status = XScuGic_CfgInitialize(IntcInstancePtr, IntcConfig,
IntcConfig->CpuBaseAddress);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
#endif /* TESTAPP_GEN */
XScuGic_SetPriorityTriggerType(IntcInstancePtr, IntrId,
0xA0, 0x3);
/*
* Connect the interrupt handler that will be called when an
* interrupt occurs for the device.
*/
Status = XScuGic_Connect(IntcInstancePtr, IntrId,
(Xil_ExceptionHandler)XTmrCtr_InterruptHandler,
TmrCtrInstancePtr);
if (Status != XST_SUCCESS) {
return Status;
}
/*
* Enable the interrupt for the Timer device.
*/
XScuGic_Enable(IntcInstancePtr, IntrId);
#endif /* XPAR_INTC_0_DEVICE_ID */
#ifndef TESTAPP_GEN
/*
* Initialize the exception table.
*/
Xil_ExceptionInit();
/*
* Register the interrupt controller handler with the exception table.
*/
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
(Xil_ExceptionHandler)
INTC_HANDLER,
IntcInstancePtr);
/*
* Enable non-critical exceptions.
*/
Xil_ExceptionEnable();
#endif
return XST_SUCCESS;
}
/**
*
* This function setups the interrupt system such that interrupts can occur
* for the FIFO device. This function is application specific since the
* actual system may or may not have an interrupt controller. The FIFO
* could be directly connected to a processor without an interrupt controller.
* The user should modify this function to fit the application.
*
* @param InstancePtr contains a pointer to the instance of the FIFO
* component which is going to be connected to the interrupt
* controller.
*
* @return XST_SUCCESS if successful, otherwise XST_FAILURE.
*
* @note None.
*
****************************************************************************/
int SetupInterruptSystem(INTC *IntcInstancePtr, XLlFifo *InstancePtr,
u16 FifoIntrId)
{
int Status;
#ifdef XPAR_INTC_0_DEVICE_ID
/*
* Initialize the interrupt controller driver so that it is ready to
* use.
*/
Status = XIntc_Initialize(IntcInstancePtr, INTC_DEVICE_ID);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Connect a device driver handler that will be called when an interrupt
* for the device occurs, the device driver handler performs the
* specific interrupt processing for the device.
*/
Status = XIntc_Connect(IntcInstancePtr, FifoIntrId,
(XInterruptHandler)FifoHandler,
(void *)InstancePtr);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Start the interrupt controller such that interrupts are enabled for
* all devices that cause interrupts, specific real mode so that
* the FIFO can cause interrupts through the interrupt controller.
*/
Status = XIntc_Start(IntcInstancePtr, XIN_REAL_MODE);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Enable the interrupt for the AXI FIFO device.
*/
XIntc_Enable(IntcInstancePtr, FifoIntrId);
#else
XScuGic_Config *IntcConfig;
/*
* Initialize the interrupt controller driver so that it is ready to
* use.
*/
IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID);
if (NULL == IntcConfig) {
return XST_FAILURE;
}
Status = XScuGic_CfgInitialize(IntcInstancePtr, IntcConfig,
IntcConfig->CpuBaseAddress);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
XScuGic_SetPriorityTriggerType(IntcInstancePtr, FifoIntrId, 0xA0, 0x3);
/*
* Connect the device driver handler that will be called when an
* interrupt for the device occurs, the handler defined above performs
* the specific interrupt processing for the device.
*/
Status = XScuGic_Connect(IntcInstancePtr, FifoIntrId,
(Xil_InterruptHandler)FifoHandler,
InstancePtr);
if (Status != XST_SUCCESS) {
return Status;
}
XScuGic_Enable(IntcInstancePtr, FifoIntrId);
#endif
/*
* Initialize the exception table.
*/
Xil_ExceptionInit();
/*
* Register the interrupt controller handler with the exception table.
*/
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
(Xil_ExceptionHandler)INTC_HANDLER,
(void *)IntcInstancePtr);;
/*
* Enable exceptions.
*/
Xil_ExceptionEnable();
return XST_SUCCESS;
}
void FreeRTOS_SetupTickInterrupt( void )
{
BaseType_t xStatus;
XTtcPs_Config *pxTimerConfiguration;
XInterval usInterval;
uint8_t ucPrescale;
const uint8_t ucLevelSensitive = 1;
XScuGic_Config *pxInterruptControllerConfig;
/* Initialize the interrupt controller driver. */
pxInterruptControllerConfig = XScuGic_LookupConfig( configINTERRUPT_CONTROLLER_DEVICE_ID );
XScuGic_CfgInitialize( &xInterruptController,
pxInterruptControllerConfig,
pxInterruptControllerConfig->CpuBaseAddress );
/* Connect the interrupt controller interrupt handler to the hardware
interrupt handling logic in the ARM processor. */
Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_IRQ_INT,
( Xil_ExceptionHandler ) XScuGic_InterruptHandler,
&xInterruptController);
/* Enable interrupts in the ARM. */
Xil_ExceptionEnable();
pxTimerConfiguration = XTtcPs_LookupConfig( configTIMER_ID );
/* Initialise the device. */
xStatus = XTtcPs_CfgInitialize( &xTimerInstance, pxTimerConfiguration, pxTimerConfiguration->BaseAddress );
if( xStatus != XST_SUCCESS )
{
/* Not sure how to do this before XTtcPs_CfgInitialize is called as
*xRTOSTickTimerInstance is set within XTtcPs_CfgInitialize(). */
XTtcPs_Stop( &xTimerInstance );
xStatus = XTtcPs_CfgInitialize( &xTimerInstance, pxTimerConfiguration, pxTimerConfiguration->BaseAddress );
configASSERT( xStatus == XST_SUCCESS );
}
/* Set the options. */
XTtcPs_SetOptions( &xTimerInstance, ( XTTCPS_OPTION_INTERVAL_MODE | XTTCPS_OPTION_WAVE_DISABLE ) );
/* Derive values from the tick rate. */
XTtcPs_CalcIntervalFromFreq( &xTimerInstance, configTICK_RATE_HZ, &( usInterval ), &( ucPrescale ) );
/* Set the interval and prescale. */
XTtcPs_SetInterval( &xTimerInstance, usInterval );
XTtcPs_SetPrescaler( &xTimerInstance, ucPrescale );
/* The priority must be the lowest possible. */
XScuGic_SetPriorityTriggerType( &xInterruptController, configTIMER_INTERRUPT_ID, portLOWEST_USABLE_INTERRUPT_PRIORITY << portPRIORITY_SHIFT, ucLevelSensitive );
/* Connect to the interrupt controller. */
XScuGic_Connect( &xInterruptController,
configTIMER_INTERRUPT_ID,
( Xil_InterruptHandler ) FreeRTOS_Tick_Handler,
( void * ) &xTimerInstance );
/* Enable the interrupt in the GIC. */
XScuGic_Enable( &xInterruptController, configTIMER_INTERRUPT_ID );
/* Enable the interrupts in the timer. */
XTtcPs_EnableInterrupts( &xTimerInstance, XTTCPS_IXR_INTERVAL_MASK );
/* Start the timer. */
XTtcPs_Start( &xTimerInstance );
}
static int SetupIntrSystem(XScuGic *IntcInstancePtr, XAxiCdma *InstancePtr,
u32 IntrId)
{
int Status;
#ifndef TESTAPP_GEN
/*
* Initialize the interrupt controller driver
*/
XScuGic_Config *IntcConfig;
/*
* Initialize the interrupt controller driver so that it is ready to
* use.
*/
IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID);
if (NULL == IntcConfig) {
return XST_FAILURE;
}
Status = XScuGic_CfgInitialize(IntcInstancePtr, IntcConfig,
IntcConfig->CpuBaseAddress);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
#endif
XScuGic_SetPriorityTriggerType(IntcInstancePtr, IntrId, 0xA0, 0x3);
/*
* Connect the device driver handler that will be called when an
* interrupt for the device occurs, the handler defined above performs
* the specific interrupt processing for the device.
*/
Status = XScuGic_Connect(IntcInstancePtr, IntrId,
(Xil_InterruptHandler)XAxiCdma_IntrHandler,
InstancePtr);
if (Status != XST_SUCCESS) {
return Status;
}
/*
* Enable the interrupt for the DMA device.
*/
XScuGic_Enable(IntcInstancePtr, IntrId);
#ifndef TESTAPP_GEN
Xil_ExceptionInit();
/*
* Connect the interrupt controller interrupt handler to the hardware
* interrupt handling logic in the processor.
*/
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT,
(Xil_ExceptionHandler)XScuGic_InterruptHandler,
IntcInstancePtr);
/*
* Enable interrupts in the Processor.
*/
Xil_ExceptionEnable();
#endif /* TESTAPP_GEN */
return XST_SUCCESS;
}
/***************************************************************************//**
* @brief adc_capture
*******************************************************************************/
int32_t adc_capture(adc_core core,
uint32_t no_of_samples,
uint32_t start_address)
{
uint32_t reg_val;
uint32_t transfer_id;
uint32_t length;
length = (no_of_samples * core.no_of_channels * ((core.resolution + 7) / 8));
adc_dmac_write(core, ADC_DMAC_REG_CTRL, 0x0);
adc_dmac_write(core, ADC_DMAC_REG_CTRL, ADC_DMAC_CTRL_ENABLE);
adc_dmac_write(core, ADC_DMAC_REG_IRQ_MASK, 0x0);
adc_dmac_read(core, ADC_DMAC_REG_TRANSFER_ID, &transfer_id);
adc_dmac_read(core, ADC_DMAC_REG_IRQ_PENDING, ®_val);
adc_dmac_write(core, ADC_DMAC_REG_IRQ_PENDING, reg_val);
#ifndef ADC_DMAC_INTERRUPTS
adc_dmac_write(core, ADC_DMAC_REG_DEST_ADDRESS, start_address);
adc_dmac_write(core, ADC_DMAC_REG_DEST_STRIDE, 0x0);
adc_dmac_write(core, ADC_DMAC_REG_X_LENGTH, length - 1);
adc_dmac_write(core, ADC_DMAC_REG_Y_LENGTH, 0x0);
adc_dmac_write(core, ADC_DMAC_REG_START_TRANSFER, 0x1);
/* Wait until the new transfer is queued. */
do {
adc_dmac_read(core, ADC_DMAC_REG_START_TRANSFER, ®_val);
}
while(reg_val == 1);
/* Wait until the current transfer is completed. */
do {
adc_dmac_read(core, ADC_DMAC_REG_IRQ_PENDING, ®_val);
}
while(reg_val != (ADC_DMAC_IRQ_SOT | ADC_DMAC_IRQ_EOT));
adc_dmac_write(core, ADC_DMAC_REG_IRQ_PENDING, reg_val);
/* Wait until the transfer with the ID transfer_id is completed. */
do {
adc_dmac_read(core, ADC_DMAC_REG_TRANSFER_DONE, ®_val);
}
while((reg_val & (1 << transfer_id)) != (1 << transfer_id));
#else
XScuGic_Config *gic_config;
XScuGic gic;
int32_t status;
gic_config = XScuGic_LookupConfig(XPAR_PS7_SCUGIC_0_DEVICE_ID);
if(gic_config == NULL)
xil_printf("Error\n");
status = XScuGic_CfgInitialize(&gic, gic_config, gic_config->CpuBaseAddress);
if(status)
xil_printf("Error\n");
XScuGic_SetPriorityTriggerType(&gic, ADC_DMAC_INT_ID, 0x0, 0x3);
status = XScuGic_Connect(&gic, ADC_DMAC_INT_ID, (Xil_ExceptionHandler)adc_dmac_isr, NULL);
if(status)
xil_printf("Error\n");
XScuGic_Enable(&gic, ADC_DMAC_INT_ID);
Xil_ExceptionInit();
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT, (Xil_ExceptionHandler)XScuGic_InterruptHandler, (void *)&gic);
Xil_ExceptionEnable();
adc_dmac_start_address = start_address;
adc_dmac_write(core, ADC_DMAC_REG_DEST_ADDRESS, adc_dmac_start_address);
adc_dmac_write(core, ADC_DMAC_REG_DEST_STRIDE, 0x0);
adc_dmac_write(core, ADC_DMAC_REG_X_LENGTH, ADC_DMAC_TRANSFER_SIZE - 1);
adc_dmac_write(core, ADC_DMAC_REG_Y_LENGTH, 0x0);
adc_dmac_write(core, ADC_DMAC_REG_START_TRANSFER, 0x1);
while(adc_dmac_start_address < (start_address + length + ADC_DMAC_TRANSFER_SIZE));
adc_dmac_write(core, ADC_DMAC_REG_CTRL, 0x0);
#endif
return 0;
}
static int SetupIntrSystem(INTC * IntcInstancePtr,
XAxiDma * AxiDmaPtr, u16 TxIntrId,
u16 RxIntrId, int RingIndex)
{
int Status;
#ifdef XPAR_INTC_0_DEVICE_ID
/* Initialize the interrupt controller and connect the ISRs */
Status = XIntc_Initialize(IntcInstancePtr, INTC_DEVICE_ID);
if (Status != XST_SUCCESS) {
xil_printf("Failed init intc\r\n");
return XST_FAILURE;
}
Status = XIntc_Connect(IntcInstancePtr, TxIntrId,
(XInterruptHandler) TxIntrHandler, AxiDmaPtr);
if (Status != XST_SUCCESS) {
xil_printf("Failed tx connect intc\r\n");
return XST_FAILURE;
}
Status = XIntc_Connect(IntcInstancePtr, RxIntrId,
(XInterruptHandler) RxIntrHandler, AxiDmaPtr);
if (Status != XST_SUCCESS) {
xil_printf("Failed rx connect intc\r\n");
return XST_FAILURE;
}
/* Start the interrupt controller */
Status = XIntc_Start(IntcInstancePtr, XIN_REAL_MODE);
if (Status != XST_SUCCESS) {
xil_printf("Failed to start intc\r\n");
return XST_FAILURE;
}
XIntc_Enable(IntcInstancePtr, TxIntrId);
XIntc_Enable(IntcInstancePtr, RxIntrId);
#else
XScuGic_Config *IntcConfig;
/*
* Initialize the interrupt controller driver so that it is ready to
* use.
*/
IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID);
if (NULL == IntcConfig) {
return XST_FAILURE;
}
Status = XScuGic_CfgInitialize(IntcInstancePtr, IntcConfig,
IntcConfig->CpuBaseAddress);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
XScuGic_SetPriorityTriggerType(IntcInstancePtr, TxIntrId, 0xA0, 0x3);
XScuGic_SetPriorityTriggerType(IntcInstancePtr, RxIntrId, 0xA0, 0x3);
/*
* Connect the device driver handler that will be called when an
* interrupt for the device occurs, the handler defined above performs
* the specific interrupt processing for the device.
*/
Status = XScuGic_Connect(IntcInstancePtr, TxIntrId,
(Xil_InterruptHandler)TxIntrHandler,
AxiDmaPtr);
if (Status != XST_SUCCESS) {
return Status;
}
Status = XScuGic_Connect(IntcInstancePtr, RxIntrId,
(Xil_InterruptHandler)RxIntrHandler,
AxiDmaPtr);
if (Status != XST_SUCCESS) {
return Status;
}
XScuGic_Enable(IntcInstancePtr, TxIntrId);
XScuGic_Enable(IntcInstancePtr, RxIntrId);
#endif
/* Enable interrupts from the hardware */
Xil_ExceptionInit();
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
(Xil_ExceptionHandler)INTC_HANDLER,
(void *)IntcInstancePtr);
Xil_ExceptionEnable();
return XST_SUCCESS;
}
/**
* This function sets up the interrupt system such that interrupts caused by
* Hot-Plug-Detect (HPD) events and pulses are handled. This function is
* application-specific for systems that have an interrupt controller connected
* to the processor. The user should modify this function to fit the
* application.
*
* @param InstancePtr is a pointer to the XDptx instance.
* @param IntcPtr is a pointer to the interrupt instance.
* @param IntrId is the unique device ID of the interrupt controller.
* @param DpIntrId is the interrupt ID of the DisplayPort TX connection to
* the interrupt controller.
* @param HpdEventHandler is a pointer to the handler called when an HPD
* event occurs.
* @param HpdPulseHandler is a pointer to the handler called when an HPD
* pulse occurs.
*
* @return
* - XST_SUCCESS if the interrupt system was successfully set up.
* - XST_FAILURE otherwise.
*
* @note An interrupt controller must be present in the system, connected
* to the processor and the DisplayPort TX core.
*
*******************************************************************************/
static u32 Dptx_SetupInterruptHandler(XDptx *InstancePtr, INTC *IntcPtr,
u16 IntrId, u16 DpIntrId, XDptx_HpdEventHandler HpdEventHandler,
XDptx_HpdPulseHandler HpdPulseHandler)
{
u32 Status;
/* Set the HPD interrupt handlers. */
XDptx_SetHpdEventHandler(InstancePtr, HpdEventHandler, InstancePtr);
XDptx_SetHpdPulseHandler(InstancePtr, HpdPulseHandler, InstancePtr);
/* Initialize interrupt controller driver. */
#ifdef XPAR_INTC_0_DEVICE_ID
Status = XIntc_Initialize(IntcPtr, IntrId);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
#else
XScuGic_Config *IntcConfig;
IntcConfig = XScuGic_LookupConfig(IntrId);
Status = XScuGic_CfgInitialize(IntcPtr, IntcConfig,
IntcConfig->CpuBaseAddress);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
XScuGic_SetPriorityTriggerType(IntcPtr, DpIntrId, 0xA0, 0x1);
#endif /* XPAR_INTC_0_DEVICE_ID */
/* Connect the device driver handler that will be called when an
* interrupt for the device occurs, the handler defined above performs
* the specific interrupt processing for the device. */
#ifdef XPAR_INTC_0_DEVICE_ID
Status = XIntc_Connect(IntcPtr, DpIntrId,
(XInterruptHandler)XDptx_HpdInterruptHandler, InstancePtr);
#else
Status = XScuGic_Connect(IntcPtr, DpIntrId,
(Xil_InterruptHandler)XDptx_HpdInterruptHandler, InstancePtr);
#endif /* XPAR_INTC_0_DEVICE_ID */
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/* Start the interrupt controller. */
#ifdef XPAR_INTC_0_DEVICE_ID
Status = XIntc_Start(IntcPtr, XIN_REAL_MODE);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
XIntc_Enable(IntcPtr, DpIntrId);
#else
XScuGic_Enable(IntcPtr, DpIntrId);
#endif /* XPAR_INTC_0_DEVICE_ID */
/* Initialize the exception table. */
Xil_ExceptionInit();
/* Register the interrupt controller handler with the exception table. */
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
(Xil_ExceptionHandler)INTC_HANDLER, IntcPtr);
/* Enable exceptions. */
Xil_ExceptionEnable();
return XST_SUCCESS;
}
/***************************************************************************
* Looks up the current config and initializes psGenericInterruptController(GIC)
***************************************************************************/
void init_GIC()
{
int Status;
XScuGic_Config *Config;
/* Initialize GIC */
Config = XScuGic_LookupConfig(INTCONTROLLER_DEVICE_ID);
Status = XScuGic_CfgInitialize(&InterruptInstancePtr, Config, Config->CpuBaseAddress);
if(Status != XST_FAILURE) {
xil_printf("InterruptConroller initialized!\n \r");
}
/* Connect to the handler */
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT,(Xil_ExceptionHandler)XScuGic_InterruptHandler,&InterruptInstancePtr);
Xil_ExceptionEnable();
/* ADC setup */
Status = XScuGic_Connect(&InterruptInstancePtr,ADC_WIZ_INT_ID,(Xil_ExceptionHandler) ADC_Intr_Handler, (void *) &InterruptInstancePtr);
XScuGic_Enable(&InterruptInstancePtr,ADC_WIZ_INT_ID);
XScuGic_SetPriorityTriggerType(&InterruptInstancePtr,ADC_WIZ_INT_ID,0xA0,0x3);
if(Status != XST_FAILURE) {
xil_printf("ADC interrupts OK!!\n \r");
}
/* UART0 setup */
XUartPs_SetInterruptMask(&Uart0InstancePtr, UART0_INT_MASK);
XUartPs_SetHandler(&Uart0InstancePtr, (XUartPs_Handler) UART_Intr_Handler,(void *) UART0_DEVICE_ID);
//XUartPs_InterruptHandler(&Uart1InstancePtr);
if(Status != XST_FAILURE) {
xil_printf("UART0 interrupts OK!!\n \r");
}
/* UART1 setup */
*Intrpt_en_reg1 = UART1_INT_MASK;
*Intrpt_dis_reg1 = 0xFFFFFD3D;
xil_printf("Interruptmask for UART1 = %x \n \r",XUartPs_GetInterruptMask(&Uart1InstancePtr));
/*XUartPs_SetInterruptMask(&Uart1InstancePtr, UART1_INT_MASK);
xil_printf("Interruptmask for UART1 = %x \n \r",XUartPs_GetInterruptMask(&Uart1InstancePtr));
XUartPs_SetHandler(&Uart1InstancePtr,(XUartPs_Handler) UART_Intr_Handler,(void *) UART1_DEVICE_ID);*/
Status = XScuGic_Connect(&InterruptInstancePtr,UART1_INT_ID,(Xil_ExceptionHandler) UART_Intr_Handler, (void *) &InterruptInstancePtr);
XScuGic_Enable(&InterruptInstancePtr,UART1_INT_ID);
XScuGic_SetPriorityTriggerType(&InterruptInstancePtr,UART1_INT_ID,0xA0,0x3);
if(Status != XST_FAILURE) {
xil_printf("UART1 interrupts OK!!\n \r");
}
/* Buttons setup */
Status = XScuGic_Connect(&InterruptInstancePtr,GPIO_BTNS_INT_ID,(Xil_ExceptionHandler) BTNS_Intr_Handler, (void *) &InterruptInstancePtr);
XScuGic_Enable(&InterruptInstancePtr,GPIO_BTNS_INT_ID);
XScuGic_SetPriorityTriggerType(&InterruptInstancePtr,GPIO_BTNS_INT_ID,0xA0,0x3);
if(Status != XST_FAILURE) {
xil_printf("BUTTONS interrupts OK!!\n \r");
}
}
/* TMP3_SetupInterruptSystem()
**
** Parameters:
** InstancePtr: PmodTMP3 object to get data from
** interruptDeviceID: Device ID of the interrupt controller
** interruptID: The vector ID of the TMP3 I2C interrupt
**
** Return Value:
** A status indicating XST_SUCCESS or a value that is contained in
** xstatus.h.
**
** Errors:
** none
**
** Description:
** This function sets up the interrupt system for the example. The processing
** contained in this function assumes the hardware system was built with
** and interrupt controller.
**
*****************************************************************************/
int TMP3_SetupInterruptSystem(PmodTMP3* InstancePtr, u32 interruptDeviceID, u32 interruptID, void* SendHandler, void* ReceiveHandler)
{
int Result;
#ifdef XPAR_XINTC_NUM_INSTANCES
INTC *IntcInstancePtr = &InstancePtr->intc;
/*
* Initialize the interrupt controller driver so that it's ready to use.
* specify the device ID that was generated in xparameters.h
*/
Result = XIntc_Initialize(IntcInstancePtr, interruptDeviceID);
if (Result != XST_SUCCESS) {
return Result;
}
/* Hook up interrupt service routine */
XIntc_Connect(IntcInstancePtr, interruptID,
(Xil_ExceptionHandler)XIic_InterruptHandler, &InstancePtr->TMP3Iic);
/* Enable the interrupt vector at the interrupt controller */
XIntc_Enable(IntcInstancePtr, interruptID);
/*
* Start the interrupt controller such that interrupts are recognized
* and handled by the processor
*/
Result = XIntc_Start(IntcInstancePtr, XIN_REAL_MODE);
if (Result != XST_SUCCESS) {
return Result;
}
XIic_SetSendHandler(&InstancePtr->TMP3Iic, InstancePtr, (XIic_Handler)SendHandler);
XIic_SetRecvHandler(&InstancePtr->TMP3Iic, InstancePtr, (XIic_Handler)ReceiveHandler);
/*
* Initialize the exception table and register the interrupt
* controller handler with the exception table
*/
Xil_ExceptionInit();
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
(Xil_ExceptionHandler)INTC_HANDLER, IntcInstancePtr);
/* Enable non-critical exceptions */
Xil_ExceptionEnable();
#endif
#ifdef XPAR_SCUGIC_0_DEVICE_ID
INTC *IntcInstancePtr = &InstancePtr->intc;
XScuGic_Config *IntcConfig;
/*
* Initialize the interrupt controller driver so that it is ready to
* use.
*/
IntcConfig = XScuGic_LookupConfig(interruptDeviceID);
if (NULL == IntcConfig) {
return XST_FAILURE;
}
Result = XScuGic_CfgInitialize(IntcInstancePtr, IntcConfig,
IntcConfig->CpuBaseAddress);
if (Result != XST_SUCCESS) {
return XST_FAILURE;
}
XScuGic_SetPriorityTriggerType(IntcInstancePtr, interruptID,
0xA0, 0x3);
/*
* Connect the interrupt handler that will be called when an
* interrupt occurs for the device.
*/
Result = XScuGic_Connect(IntcInstancePtr, interruptID,
(Xil_ExceptionHandler)XIic_InterruptHandler, &InstancePtr->TMP3Iic);
if (Result != XST_SUCCESS) {
return Result;
}
/*
* Enable the interrupt for the device.
*/
XScuGic_Enable(IntcInstancePtr, interruptID);
XIic_SetSendHandler(&InstancePtr->TMP3Iic, InstancePtr, (XIic_Handler)SendHandler);
XIic_SetRecvHandler(&InstancePtr->TMP3Iic, InstancePtr, (XIic_Handler)ReceiveHandler);
XIic_SetStatusHandler(&InstancePtr->TMP3Iic, InstancePtr, (XIic_Handler)StatusHandler);
/*
* Initialize the exception table and register the interrupt
* controller handler with the exception table
*/
Xil_ExceptionInit();
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
(Xil_ExceptionHandler)INTC_HANDLER, IntcInstancePtr);
/* Enable non-critical exceptions */
Xil_ExceptionEnable();
#endif
return XST_SUCCESS;
}
/**
*
* This function setups the interrupt system such that interrupts can occur
* for the EmacLite device. This function is application specific since the
* actual system may or may not have an interrupt controller. The EmacLite
* could be directly connected to a processor without an interrupt controller.
* The user should modify this function to fit the application.
*
* @param IntcInstancePtr is a pointer to the instance of the Intc.
* @param EmacLiteInstPtr is a pointer to the instance of the EmacLite.
* @param EmacLiteIntrId is the interrupt ID and is typically
* XPAR_<INTC_instance>_<EMACLITE_instance>_VEC_ID
* value from xparameters.h
*
* @return XST_SUCCESS if successful, otherwise XST_FAILURE.
*
* @note None.
*
******************************************************************************/
static int EmacLiteSetupIntrSystem(INTC *IntcInstancePtr,
XEmacLite *EmacLiteInstPtr, u16 EmacLiteIntrId)
{
int Status;
#ifdef XPAR_INTC_0_DEVICE_ID
#ifndef TESTAPP_GEN
/*
* Initialize the interrupt controller driver so that it is ready to
* use.
*/
Status = XIntc_Initialize(IntcInstancePtr, INTC_DEVICE_ID);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
#endif
/*
* Connect a device driver handler that will be called when an interrupt
* for the device occurs, the device driver handler performs the
* specific interrupt processing for the device.
*/
Status = XIntc_Connect(IntcInstancePtr,
EmacLiteIntrId,
XEmacLite_InterruptHandler,
(void *)(EmacLiteInstPtr));
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
#ifndef TESTAPP_GEN
/*
* Start the interrupt controller such that interrupts are enabled for
* all devices that cause interrupts, specific real mode so that
* the EmacLite can cause interrupts thru the interrupt controller.
*/
Status = XIntc_Start(IntcInstancePtr, XIN_REAL_MODE);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
#endif
/*
* Enable the interrupt for the EmacLite in the Interrupt controller.
*/
XIntc_Enable(IntcInstancePtr, EmacLiteIntrId);
#else /* SCUGIC */
#ifndef TESTAPP_GEN
XScuGic_Config *IntcConfig;
/*
* Initialize the interrupt controller driver so that it is ready to
* use.
*/
IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID);
if (NULL == IntcConfig) {
return XST_FAILURE;
}
Status = XScuGic_CfgInitialize(IntcInstancePtr, IntcConfig,
IntcConfig->CpuBaseAddress);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
#endif
XScuGic_SetPriorityTriggerType(IntcInstancePtr, EmacLiteIntrId,
0xA0, 0x3);
/*
* Connect the interrupt handler that will be called when an
* interrupt occurs for the device.
*/
Status = XScuGic_Connect(IntcInstancePtr, EmacLiteIntrId,
(Xil_ExceptionHandler)XEmacLite_InterruptHandler,
EmacLiteInstPtr);
if (Status != XST_SUCCESS) {
return Status;
}
/*
* Enable the interrupt for the Can device.
*/
XScuGic_Enable(IntcInstancePtr, EmacLiteIntrId);
#endif
#ifndef TESTAPP_GEN
/*
* Initialize the exception table.
*/
Xil_ExceptionInit();
/*
* Register the interrupt controller handler with the exception table.
*/
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
(Xil_ExceptionHandler) INTC_HANDLER,
IntcInstancePtr);
/*
* Enable non-critical exceptions.
*/
Xil_ExceptionEnable();
#endif /* TESTAPP_GEN */
return XST_SUCCESS;
}
/**
*
* This function sets up the interrupt system so interrupts can occur for the
* CAN. This function is application-specific since the actual system may or
* may not have an interrupt controller. The CAN could be directly connected
* to a processor without an interrupt controller. The user should modify this
* function to fit the application.
*
* @para InstancePtr is a pointer to the instance of the CAN
* which is going to be connected to the interrupt controller.
*
* @return XST_SUCCESS if successful, otherwise XST_FAILURE.
*
* @note None.
*
****************************************************************************/
static int SetupInterruptSystem(XCan *InstancePtr)
{
static INTC InterruptController;
int Status;
#ifdef XPAR_INTC_0_DEVICE_ID
/*
* Initialize the interrupt controller driver so that it's ready to use.
* INTC_DEVICE_ID specifies the XINTC device ID that is generated in
* xparameters.h.
*/
Status = XIntc_Initialize(&InterruptController, INTC_DEVICE_ID);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Connect the device driver handler that will be called when an interrupt
* for the device occurs, the device driver handler performs the specific
* interrupt processing for the device.
*/
Status = XIntc_Connect(&InterruptController,
CAN_INTR_VEC_ID,
(XInterruptHandler)XCan_IntrHandler,
InstancePtr);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Start the interrupt controller so interrupts are enabled for all
* devices that cause interrupts. Specify real mode so that the CAN
* can cause interrupts through the interrupt controller.
*/
Status = XIntc_Start(&InterruptController, XIN_REAL_MODE);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Enable the interrupt for the CAN.
*/
XIntc_Enable(&InterruptController, CAN_INTR_VEC_ID);
#else /* SCUGIC */
XScuGic_Config *IntcConfig;
/*
* Initialize the interrupt controller driver so that it is ready to
* use.
*/
IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID);
if (NULL == IntcConfig) {
return XST_FAILURE;
}
Status = XScuGic_CfgInitialize(&InterruptController, IntcConfig,
IntcConfig->CpuBaseAddress);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
XScuGic_SetPriorityTriggerType(&InterruptController, CAN_INTR_VEC_ID,
0xA0, 0x3);
/*
* Connect the interrupt handler that will be called when an
* interrupt occurs for the device.
*/
Status = XScuGic_Connect(&InterruptController, CAN_INTR_VEC_ID,
(Xil_ExceptionHandler)XCan_IntrHandler,
InstancePtr);
if (Status != XST_SUCCESS) {
return Status;
}
/*
* Enable the interrupt for the Can device.
*/
XScuGic_Enable(&InterruptController, CAN_INTR_VEC_ID);
#endif
/*
* Initialize the exception table.
*/
Xil_ExceptionInit();
/*
* Register the interrupt controller handler with the exception table.
*/
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
(Xil_ExceptionHandler)INTC_HANDLER,
&InterruptController);
/*
* Enable exceptions.
*/
Xil_ExceptionEnable();
return XST_SUCCESS;
}
